1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2d308c013SSimon Glass /* 3d308c013SSimon Glass * Copyright (c) 2015 Google, Inc 4d308c013SSimon Glass */ 5d308c013SSimon Glass 6d308c013SSimon Glass #ifndef __S5M8767_H_ 7d308c013SSimon Glass #define __S5M8767_H_ 8d308c013SSimon Glass 9d308c013SSimon Glass enum s5m8767_regnum { 10d308c013SSimon Glass S5M8767_BUCK1 = 0, 11d308c013SSimon Glass S5M8767_BUCK2, 12d308c013SSimon Glass S5M8767_BUCK3, 13d308c013SSimon Glass S5M8767_BUCK4, 14d308c013SSimon Glass S5M8767_BUCK5, 15d308c013SSimon Glass S5M8767_BUCK6, 16d308c013SSimon Glass S5M8767_BUCK7, 17d308c013SSimon Glass S5M8767_BUCK8, 18d308c013SSimon Glass S5M8767_BUCK9, 19d308c013SSimon Glass S5M8767_LDO1, 20d308c013SSimon Glass S5M8767_LDO2, 21d308c013SSimon Glass S5M8767_LDO3, 22d308c013SSimon Glass S5M8767_LDO4, 23d308c013SSimon Glass S5M8767_LDO5, 24d308c013SSimon Glass S5M8767_LDO6, 25d308c013SSimon Glass S5M8767_LDO7, 26d308c013SSimon Glass S5M8767_LDO8, 27d308c013SSimon Glass S5M8767_LDO9, 28d308c013SSimon Glass S5M8767_LDO10, 29d308c013SSimon Glass S5M8767_LDO11, 30d308c013SSimon Glass S5M8767_LDO12, 31d308c013SSimon Glass S5M8767_LDO13, 32d308c013SSimon Glass S5M8767_LDO14, 33d308c013SSimon Glass S5M8767_LDO15, 34d308c013SSimon Glass S5M8767_LDO16, 35d308c013SSimon Glass S5M8767_LDO17, 36d308c013SSimon Glass S5M8767_LDO18, 37d308c013SSimon Glass S5M8767_LDO19, 38d308c013SSimon Glass S5M8767_LDO20, 39d308c013SSimon Glass S5M8767_LDO21, 40d308c013SSimon Glass S5M8767_LDO22, 41d308c013SSimon Glass S5M8767_LDO23, 42d308c013SSimon Glass S5M8767_LDO24, 43d308c013SSimon Glass S5M8767_LDO25, 44d308c013SSimon Glass S5M8767_LDO26, 45d308c013SSimon Glass S5M8767_LDO27, 46d308c013SSimon Glass S5M8767_LDO28, 47d308c013SSimon Glass S5M8767_EN32KHZ_CP, 48d308c013SSimon Glass 49d308c013SSimon Glass S5M8767_NUM_OF_REGS, 50d308c013SSimon Glass }; 51d308c013SSimon Glass 52d308c013SSimon Glass struct sec_voltage_desc { 53d308c013SSimon Glass int max; 54d308c013SSimon Glass int min; 55d308c013SSimon Glass int step; 56d308c013SSimon Glass }; 57d308c013SSimon Glass 58d308c013SSimon Glass /** 59d308c013SSimon Glass * struct s5m8767_para - s5m8767 register parameters 60d308c013SSimon Glass * @param vol_addr i2c address of the given buck/ldo register 61d308c013SSimon Glass * @param vol_bitpos bit position to be set or clear within register 62d308c013SSimon Glass * @param vol_bitmask bit mask value 63d308c013SSimon Glass * @param reg_enaddr control register address, which enable the given 64d308c013SSimon Glass * given buck/ldo. 65d308c013SSimon Glass * @param reg_enbiton value to be written to buck/ldo to make it ON 66d308c013SSimon Glass * @param vol Voltage information 67d308c013SSimon Glass */ 68d308c013SSimon Glass struct s5m8767_para { 69d308c013SSimon Glass enum s5m8767_regnum regnum; 70d308c013SSimon Glass u8 vol_addr; 71d308c013SSimon Glass u8 vol_bitpos; 72d308c013SSimon Glass u8 vol_bitmask; 73d308c013SSimon Glass u8 reg_enaddr; 74d308c013SSimon Glass u8 reg_enbiton; 75d308c013SSimon Glass const struct sec_voltage_desc *vol; 76d308c013SSimon Glass }; 77d308c013SSimon Glass 78d308c013SSimon Glass /* Drivers name */ 79d308c013SSimon Glass #define S5M8767_LDO_DRIVER "s5m8767_ldo" 80d308c013SSimon Glass #define S5M8767_BUCK_DRIVER "s5m8767_buck" 81d308c013SSimon Glass 82d308c013SSimon Glass int s5m8767_enable_32khz_cp(struct udevice *dev); 83d308c013SSimon Glass 84d308c013SSimon Glass #endif /* __S5M8767_PMIC_H_ */ 85