1*d308c013SSimon Glass /* 2*d308c013SSimon Glass * Copyright (c) 2015 Google, Inc 3*d308c013SSimon Glass * 4*d308c013SSimon Glass * SPDX-License-Identifier: GPL-2.0+ 5*d308c013SSimon Glass */ 6*d308c013SSimon Glass 7*d308c013SSimon Glass #ifndef __S5M8767_H_ 8*d308c013SSimon Glass #define __S5M8767_H_ 9*d308c013SSimon Glass 10*d308c013SSimon Glass enum s5m8767_regnum { 11*d308c013SSimon Glass S5M8767_BUCK1 = 0, 12*d308c013SSimon Glass S5M8767_BUCK2, 13*d308c013SSimon Glass S5M8767_BUCK3, 14*d308c013SSimon Glass S5M8767_BUCK4, 15*d308c013SSimon Glass S5M8767_BUCK5, 16*d308c013SSimon Glass S5M8767_BUCK6, 17*d308c013SSimon Glass S5M8767_BUCK7, 18*d308c013SSimon Glass S5M8767_BUCK8, 19*d308c013SSimon Glass S5M8767_BUCK9, 20*d308c013SSimon Glass S5M8767_LDO1, 21*d308c013SSimon Glass S5M8767_LDO2, 22*d308c013SSimon Glass S5M8767_LDO3, 23*d308c013SSimon Glass S5M8767_LDO4, 24*d308c013SSimon Glass S5M8767_LDO5, 25*d308c013SSimon Glass S5M8767_LDO6, 26*d308c013SSimon Glass S5M8767_LDO7, 27*d308c013SSimon Glass S5M8767_LDO8, 28*d308c013SSimon Glass S5M8767_LDO9, 29*d308c013SSimon Glass S5M8767_LDO10, 30*d308c013SSimon Glass S5M8767_LDO11, 31*d308c013SSimon Glass S5M8767_LDO12, 32*d308c013SSimon Glass S5M8767_LDO13, 33*d308c013SSimon Glass S5M8767_LDO14, 34*d308c013SSimon Glass S5M8767_LDO15, 35*d308c013SSimon Glass S5M8767_LDO16, 36*d308c013SSimon Glass S5M8767_LDO17, 37*d308c013SSimon Glass S5M8767_LDO18, 38*d308c013SSimon Glass S5M8767_LDO19, 39*d308c013SSimon Glass S5M8767_LDO20, 40*d308c013SSimon Glass S5M8767_LDO21, 41*d308c013SSimon Glass S5M8767_LDO22, 42*d308c013SSimon Glass S5M8767_LDO23, 43*d308c013SSimon Glass S5M8767_LDO24, 44*d308c013SSimon Glass S5M8767_LDO25, 45*d308c013SSimon Glass S5M8767_LDO26, 46*d308c013SSimon Glass S5M8767_LDO27, 47*d308c013SSimon Glass S5M8767_LDO28, 48*d308c013SSimon Glass S5M8767_EN32KHZ_CP, 49*d308c013SSimon Glass 50*d308c013SSimon Glass S5M8767_NUM_OF_REGS, 51*d308c013SSimon Glass }; 52*d308c013SSimon Glass 53*d308c013SSimon Glass struct sec_voltage_desc { 54*d308c013SSimon Glass int max; 55*d308c013SSimon Glass int min; 56*d308c013SSimon Glass int step; 57*d308c013SSimon Glass }; 58*d308c013SSimon Glass 59*d308c013SSimon Glass /** 60*d308c013SSimon Glass * struct s5m8767_para - s5m8767 register parameters 61*d308c013SSimon Glass * @param vol_addr i2c address of the given buck/ldo register 62*d308c013SSimon Glass * @param vol_bitpos bit position to be set or clear within register 63*d308c013SSimon Glass * @param vol_bitmask bit mask value 64*d308c013SSimon Glass * @param reg_enaddr control register address, which enable the given 65*d308c013SSimon Glass * given buck/ldo. 66*d308c013SSimon Glass * @param reg_enbiton value to be written to buck/ldo to make it ON 67*d308c013SSimon Glass * @param vol Voltage information 68*d308c013SSimon Glass */ 69*d308c013SSimon Glass struct s5m8767_para { 70*d308c013SSimon Glass enum s5m8767_regnum regnum; 71*d308c013SSimon Glass u8 vol_addr; 72*d308c013SSimon Glass u8 vol_bitpos; 73*d308c013SSimon Glass u8 vol_bitmask; 74*d308c013SSimon Glass u8 reg_enaddr; 75*d308c013SSimon Glass u8 reg_enbiton; 76*d308c013SSimon Glass const struct sec_voltage_desc *vol; 77*d308c013SSimon Glass }; 78*d308c013SSimon Glass 79*d308c013SSimon Glass /* Drivers name */ 80*d308c013SSimon Glass #define S5M8767_LDO_DRIVER "s5m8767_ldo" 81*d308c013SSimon Glass #define S5M8767_BUCK_DRIVER "s5m8767_buck" 82*d308c013SSimon Glass 83*d308c013SSimon Glass int s5m8767_enable_32khz_cp(struct udevice *dev); 84*d308c013SSimon Glass 85*d308c013SSimon Glass #endif /* __S5M8767_PMIC_H_ */ 86