1*762161b0SHou Zhiqiang /* 2*762161b0SHou Zhiqiang * Copyright 2016 Freescale Semiconductor, Inc. 3*762161b0SHou Zhiqiang * Hou Zhiqiang <Zhiqiang.Hou@freescale.com> 4*762161b0SHou Zhiqiang * 5*762161b0SHou Zhiqiang * SPDX-License-Identifier: GPL-2.0+ 6*762161b0SHou Zhiqiang */ 7*762161b0SHou Zhiqiang 8*762161b0SHou Zhiqiang #ifndef __MC34VR500_H_ 9*762161b0SHou Zhiqiang #define __MC34VR500_H_ 10*762161b0SHou Zhiqiang 11*762161b0SHou Zhiqiang #include <power/pmic.h> 12*762161b0SHou Zhiqiang 13*762161b0SHou Zhiqiang #define MC34VR500_I2C_ADDR 0x08 14*762161b0SHou Zhiqiang 15*762161b0SHou Zhiqiang /* Drivers name */ 16*762161b0SHou Zhiqiang #define MC34VR500_REGULATOR_DRIVER "mc34vr500_regulator" 17*762161b0SHou Zhiqiang 18*762161b0SHou Zhiqiang /* Register map */ 19*762161b0SHou Zhiqiang enum { 20*762161b0SHou Zhiqiang MC34VR500_DEVICEID = 0x00, 21*762161b0SHou Zhiqiang 22*762161b0SHou Zhiqiang MC34VR500_SILICONREVID = 0x03, 23*762161b0SHou Zhiqiang MC34VR500_FABID, 24*762161b0SHou Zhiqiang MC34VR500_INTSTAT0, 25*762161b0SHou Zhiqiang MC34VR500_INTMASK0, 26*762161b0SHou Zhiqiang MC34VR500_INTSENSE0, 27*762161b0SHou Zhiqiang MC34VR500_INTSTAT1, 28*762161b0SHou Zhiqiang MC34VR500_INTMASK1, 29*762161b0SHou Zhiqiang MC34VR500_INTSENSE1, 30*762161b0SHou Zhiqiang 31*762161b0SHou Zhiqiang MC34VR500_INTSTAT4 = 0x11, 32*762161b0SHou Zhiqiang MC34VR500_INTMASK4, 33*762161b0SHou Zhiqiang MC34VR500_INTSENSE4, 34*762161b0SHou Zhiqiang 35*762161b0SHou Zhiqiang MC34VR500_PWRCTL = 0x1B, 36*762161b0SHou Zhiqiang 37*762161b0SHou Zhiqiang MC34VR500_SW1VOLT = 0x2E, 38*762161b0SHou Zhiqiang MC34VR500_SW1STBY, 39*762161b0SHou Zhiqiang MC34VR500_SW1OFF, 40*762161b0SHou Zhiqiang MC34VR500_SW1MODE, 41*762161b0SHou Zhiqiang MC34VR500_SW1CONF, 42*762161b0SHou Zhiqiang MC34VR500_SW2VOLT, 43*762161b0SHou Zhiqiang MC34VR500_SW2STBY, 44*762161b0SHou Zhiqiang MC34VR500_SW2OFF, 45*762161b0SHou Zhiqiang MC34VR500_SW2MODE, 46*762161b0SHou Zhiqiang MC34VR500_SW2CONF, 47*762161b0SHou Zhiqiang 48*762161b0SHou Zhiqiang MC34VR500_SW3VOLT = 0x3C, 49*762161b0SHou Zhiqiang MC34VR500_SW3STBY, 50*762161b0SHou Zhiqiang MC34VR500_SW3OFF, 51*762161b0SHou Zhiqiang MC34VR500_SW3MODE, 52*762161b0SHou Zhiqiang MC34VR500_SW3CONF, 53*762161b0SHou Zhiqiang 54*762161b0SHou Zhiqiang MC34VR500_SW4VOLT = 0x4A, 55*762161b0SHou Zhiqiang MC34VR500_SW4STBY, 56*762161b0SHou Zhiqiang MC34VR500_SW4OFF, 57*762161b0SHou Zhiqiang MC34VR500_SW4MODE, 58*762161b0SHou Zhiqiang MC34VR500_SW4CONF, 59*762161b0SHou Zhiqiang 60*762161b0SHou Zhiqiang MC34VR500_REFOUTCRTRL = 0x6A, 61*762161b0SHou Zhiqiang 62*762161b0SHou Zhiqiang MC34VR500_LDO1CTL = 0x6D, 63*762161b0SHou Zhiqiang MC34VR500_LDO2CTL, 64*762161b0SHou Zhiqiang MC34VR500_LDO3CTL, 65*762161b0SHou Zhiqiang MC34VR500_LDO4CTL, 66*762161b0SHou Zhiqiang MC34VR500_LDO5CTL, 67*762161b0SHou Zhiqiang 68*762161b0SHou Zhiqiang MC34VR500_PAGE_REGISTER = 0x7F, 69*762161b0SHou Zhiqiang 70*762161b0SHou Zhiqiang /* Internal RAM */ 71*762161b0SHou Zhiqiang MC34VR500_SW1_VOLT = 0xA8, 72*762161b0SHou Zhiqiang MC34VR500_SW1_SEQ, 73*762161b0SHou Zhiqiang MC34VR500_SW1_CONFIG, 74*762161b0SHou Zhiqiang 75*762161b0SHou Zhiqiang MC34VR500_SW2_VOLT = 0xAC, 76*762161b0SHou Zhiqiang MC34VR500_SW2_SEQ, 77*762161b0SHou Zhiqiang MC34VR500_SW2_CONFIG, 78*762161b0SHou Zhiqiang 79*762161b0SHou Zhiqiang MC34VR500_SW3_VOLT = 0xB0, 80*762161b0SHou Zhiqiang MC34VR500_SW3_SEQ, 81*762161b0SHou Zhiqiang MC34VR500_SW3_CONFIG, 82*762161b0SHou Zhiqiang 83*762161b0SHou Zhiqiang MC34VR500_SW4_VOLT = 0xB8, 84*762161b0SHou Zhiqiang MC34VR500_SW4_SEQ, 85*762161b0SHou Zhiqiang MC34VR500_SW4_CONFIG, 86*762161b0SHou Zhiqiang 87*762161b0SHou Zhiqiang MC34VR500_REFOUT_SEQ = 0xC4, 88*762161b0SHou Zhiqiang 89*762161b0SHou Zhiqiang MC34VR500_LDO1_VOLT = 0xCC, 90*762161b0SHou Zhiqiang MC34VR500_LDO1_SEQ, 91*762161b0SHou Zhiqiang 92*762161b0SHou Zhiqiang MC34VR500_LDO2_VOLT = 0xD0, 93*762161b0SHou Zhiqiang MC34VR500_LDO2_SEQ, 94*762161b0SHou Zhiqiang 95*762161b0SHou Zhiqiang MC34VR500_LDO3_VOLT = 0xD4, 96*762161b0SHou Zhiqiang MC34VR500_LDO3_SEQ, 97*762161b0SHou Zhiqiang 98*762161b0SHou Zhiqiang MC34VR500_LDO4_VOLT = 0xD8, 99*762161b0SHou Zhiqiang MC34VR500_LDO4_SEQ, 100*762161b0SHou Zhiqiang 101*762161b0SHou Zhiqiang MC34VR500_LDO5_VOLT = 0xDC, 102*762161b0SHou Zhiqiang MC34VR500_LDO5_SEQ, 103*762161b0SHou Zhiqiang 104*762161b0SHou Zhiqiang MC34VR500_PU_CONFIG1 = 0xE0, 105*762161b0SHou Zhiqiang 106*762161b0SHou Zhiqiang MC34VR500_TBB_POR = 0xE4, 107*762161b0SHou Zhiqiang 108*762161b0SHou Zhiqiang MC34VR500_PWRGD_EN = 0xE8, 109*762161b0SHou Zhiqiang 110*762161b0SHou Zhiqiang MC34VR500_NUM_OF_REGS, 111*762161b0SHou Zhiqiang }; 112*762161b0SHou Zhiqiang 113*762161b0SHou Zhiqiang /* Registor offset based on SWxVOLT register */ 114*762161b0SHou Zhiqiang #define MC34VR500_VOLT_OFFSET 0 115*762161b0SHou Zhiqiang #define MC34VR500_STBY_OFFSET 1 116*762161b0SHou Zhiqiang #define MC34VR500_OFF_OFFSET 2 117*762161b0SHou Zhiqiang #define MC34VR500_MODE_OFFSET 3 118*762161b0SHou Zhiqiang #define MC34VR500_CONF_OFFSET 4 119*762161b0SHou Zhiqiang 120*762161b0SHou Zhiqiang #define SW_MODE_MASK 0xf 121*762161b0SHou Zhiqiang #define SW_MODE_SHIFT 0 122*762161b0SHou Zhiqiang 123*762161b0SHou Zhiqiang #define LDO_VOL_MASK 0xf 124*762161b0SHou Zhiqiang #define LDO_EN (1 << 4) 125*762161b0SHou Zhiqiang #define LDO_MODE_SHIFT 4 126*762161b0SHou Zhiqiang #define LDO_MODE_MASK (1 << 4) 127*762161b0SHou Zhiqiang #define LDO_MODE_OFF 0 128*762161b0SHou Zhiqiang #define LDO_MODE_ON 1 129*762161b0SHou Zhiqiang 130*762161b0SHou Zhiqiang #define REFOUTEN (1 << 4) 131*762161b0SHou Zhiqiang 132*762161b0SHou Zhiqiang /* 133*762161b0SHou Zhiqiang * Regulator Mode Control 134*762161b0SHou Zhiqiang * 135*762161b0SHou Zhiqiang * OFF: The regulator is switched off and the output voltage is discharged. 136*762161b0SHou Zhiqiang * PFM: In this mode, the regulator is always in PFM mode, which is useful 137*762161b0SHou Zhiqiang * at light loads for optimized efficiency. 138*762161b0SHou Zhiqiang * PWM: In this mode, the regulator is always in PWM mode operation 139*762161b0SHou Zhiqiang * regardless of load conditions. 140*762161b0SHou Zhiqiang * APS: In this mode, the regulator moves automatically between pulse 141*762161b0SHou Zhiqiang * skipping mode and PWM mode depending on load conditions. 142*762161b0SHou Zhiqiang * 143*762161b0SHou Zhiqiang * SWxMODE[3:0] 144*762161b0SHou Zhiqiang * Normal Mode | Standby Mode | value 145*762161b0SHou Zhiqiang * OFF OFF 0x0 146*762161b0SHou Zhiqiang * PWM OFF 0x1 147*762161b0SHou Zhiqiang * PFM OFF 0x3 148*762161b0SHou Zhiqiang * APS OFF 0x4 149*762161b0SHou Zhiqiang * PWM PWM 0x5 150*762161b0SHou Zhiqiang * PWM APS 0x6 151*762161b0SHou Zhiqiang * APS APS 0x8 152*762161b0SHou Zhiqiang * APS PFM 0xc 153*762161b0SHou Zhiqiang * PWM PFM 0xd 154*762161b0SHou Zhiqiang */ 155*762161b0SHou Zhiqiang #define OFF_OFF 0x0 156*762161b0SHou Zhiqiang #define PWM_OFF 0x1 157*762161b0SHou Zhiqiang #define PFM_OFF 0x3 158*762161b0SHou Zhiqiang #define APS_OFF 0x4 159*762161b0SHou Zhiqiang #define PWM_PWM 0x5 160*762161b0SHou Zhiqiang #define PWM_APS 0x6 161*762161b0SHou Zhiqiang #define APS_APS 0x8 162*762161b0SHou Zhiqiang #define APS_PFM 0xc 163*762161b0SHou Zhiqiang #define PWM_PFM 0xd 164*762161b0SHou Zhiqiang 165*762161b0SHou Zhiqiang int power_mc34vr500_init(unsigned char bus); 166*762161b0SHou Zhiqiang #endif /* __MC34VR500_PMIC_H_ */ 167