1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Samsung Electronics 4 * Rajeshwari Shinde <rajeshwari.s@samsung.com> 5 */ 6 7 #ifndef __MAX77686_H_ 8 #define __MAX77686_H_ 9 10 #include <power/pmic.h> 11 12 enum { 13 MAX77686_REG_PMIC_ID = 0x0, 14 MAX77686_REG_PMIC_INTSRC, 15 MAX77686_REG_PMIC_INT1, 16 MAX77686_REG_PMIC_INT2, 17 MAX77686_REG_PMIC_INT1MSK, 18 MAX77686_REG_PMIC_INT2MSK, 19 20 MAX77686_REG_PMIC_STATUS1, 21 MAX77686_REG_PMIC_STATUS2, 22 23 MAX77686_REG_PMIC_PWRON, 24 MAX77686_REG_PMIC_ONOFFDELAY, 25 MAX77686_REG_PMIC_MRSTB, 26 27 MAX77686_REG_PMIC_BUCK1CRTL = 0x10, 28 MAX77686_REG_PMIC_BUCK1OUT, 29 MAX77686_REG_PMIC_BUCK2CTRL1, 30 MAX77686_REG_PMIC_BUCK234FREQ, 31 MAX77686_REG_PMIC_BUCK2DVS1, 32 MAX77686_REG_PMIC_BUCK2DVS2, 33 MAX77686_REG_PMIC_BUCK2DVS3, 34 MAX77686_REG_PMIC_BUCK2DVS4, 35 MAX77686_REG_PMIC_BUCK2DVS5, 36 MAX77686_REG_PMIC_BUCK2DVS6, 37 MAX77686_REG_PMIC_BUCK2DVS7, 38 MAX77686_REG_PMIC_BUCK2DVS8, 39 MAX77686_REG_PMIC_BUCK3CTRL, 40 MAX77686_REG_PMIC_BUCK3DVS1 = 0x1e, 41 MAX77686_REG_PMIC_BUCK3DVS2, 42 MAX77686_REG_PMIC_BUCK3DVS3, 43 MAX77686_REG_PMIC_BUCK3DVS4, 44 MAX77686_REG_PMIC_BUCK3DVS5, 45 MAX77686_REG_PMIC_BUCK3DVS6, 46 MAX77686_REG_PMIC_BUCK3DVS7, 47 MAX77686_REG_PMIC_BUCK3DVS8, 48 MAX77686_REG_PMIC_BUCK4CTRL1, 49 MAX77686_REG_PMIC_BUCK4DVS1 = 0x28, 50 MAX77686_REG_PMIC_BUCK4DVS2, 51 MAX77686_REG_PMIC_BUCK4DVS3, 52 MAX77686_REG_PMIC_BUCK4DVS4, 53 MAX77686_REG_PMIC_BUCK4DVS5, 54 MAX77686_REG_PMIC_BUCK4DVS6, 55 MAX77686_REG_PMIC_BUCK4DVS7, 56 MAX77686_REG_PMIC_BUCK4DVS8, 57 MAX77686_REG_PMIC_BUCK5CTRL, 58 MAX77686_REG_PMIC_BUCK5OUT, 59 MAX77686_REG_PMIC_BUCK6CRTL, 60 MAX77686_REG_PMIC_BUCK6OUT, 61 MAX77686_REG_PMIC_BUCK7CRTL, 62 MAX77686_REG_PMIC_BUCK7OUT, 63 MAX77686_REG_PMIC_BUCK8CRTL, 64 MAX77686_REG_PMIC_BUCK8OUT, 65 MAX77686_REG_PMIC_BUCK9CRTL, 66 MAX77686_REG_PMIC_BUCK9OUT, 67 68 MAX77686_REG_PMIC_LDO1CTRL1 = 0x40, 69 MAX77686_REG_PMIC_LDO2CTRL1, 70 MAX77686_REG_PMIC_LDO3CTRL1, 71 MAX77686_REG_PMIC_LDO4CTRL1, 72 MAX77686_REG_PMIC_LDO5CTRL1, 73 MAX77686_REG_PMIC_LDO6CTRL1, 74 MAX77686_REG_PMIC_LDO7CTRL1, 75 MAX77686_REG_PMIC_LDO8CTRL1, 76 MAX77686_REG_PMIC_LDO9CTRL1, 77 MAX77686_REG_PMIC_LDO10CTRL1, 78 MAX77686_REG_PMIC_LDO11CTRL1, 79 MAX77686_REG_PMIC_LDO12CTRL1, 80 MAX77686_REG_PMIC_LDO13CTRL1, 81 MAX77686_REG_PMIC_LDO14CTRL1, 82 MAX77686_REG_PMIC_LDO15CTRL1, 83 MAX77686_REG_PMIC_LDO16CTRL1, 84 MAX77686_REG_PMIC_LDO17CTRL1, 85 MAX77686_REG_PMIC_LDO18CTRL1, 86 MAX77686_REG_PMIC_LDO19CTRL1, 87 MAX77686_REG_PMIC_LDO20CTRL1, 88 MAX77686_REG_PMIC_LDO21CTRL1, 89 MAX77686_REG_PMIC_LDO22CTRL1, 90 MAX77686_REG_PMIC_LDO23CTRL1, 91 MAX77686_REG_PMIC_LDO24CTRL1, 92 MAX77686_REG_PMIC_LDO25CTRL1, 93 MAX77686_REG_PMIC_LDO26CTRL1, 94 MAX77686_REG_PMIC_LDO1CTRL2, 95 MAX77686_REG_PMIC_LDO2CTRL2, 96 MAX77686_REG_PMIC_LDO3CTRL2, 97 MAX77686_REG_PMIC_LDO4CTRL2, 98 MAX77686_REG_PMIC_LDO5CTRL2, 99 MAX77686_REG_PMIC_LDO6CTRL2, 100 MAX77686_REG_PMIC_LDO7CTRL2, 101 MAX77686_REG_PMIC_LDO8CTRL2, 102 MAX77686_REG_PMIC_LDO9CTRL2, 103 MAX77686_REG_PMIC_LDO10CTRL2, 104 MAX77686_REG_PMIC_LDO11CTRL2, 105 MAX77686_REG_PMIC_LDO12CTRL2, 106 MAX77686_REG_PMIC_LDO13CTRL2, 107 MAX77686_REG_PMIC_LDO14CTRL2, 108 MAX77686_REG_PMIC_LDO15CTRL2, 109 MAX77686_REG_PMIC_LDO16CTRL2, 110 MAX77686_REG_PMIC_LDO17CTRL2, 111 MAX77686_REG_PMIC_LDO18CTRL2, 112 MAX77686_REG_PMIC_LDO19CTRL2, 113 MAX77686_REG_PMIC_LDO20CTRL2, 114 MAX77686_REG_PMIC_LDO21CTRL2, 115 MAX77686_REG_PMIC_LDO22CTRL2, 116 MAX77686_REG_PMIC_LDO23CTRL2, 117 MAX77686_REG_PMIC_LDO24CTRL2, 118 MAX77686_REG_PMIC_LDO25CTRL2, 119 MAX77686_REG_PMIC_LDO26CTRL2, 120 121 MAX77686_REG_PMIC_BBAT = 0x7e, 122 MAX77686_REG_PMIC_32KHZ, 123 124 MAX77686_NUM_OF_REGS, 125 }; 126 127 /* I2C device address for pmic max77686 */ 128 #define MAX77686_I2C_ADDR (0x12 >> 1) 129 #define MAX77686_LDO_NUM 26 130 #define MAX77686_BUCK_NUM 9 131 132 /* Drivers name */ 133 #define MAX77686_LDO_DRIVER "max77686_ldo" 134 #define MAX77686_BUCK_DRIVER "max77686_buck" 135 136 enum { 137 REG_DISABLE = 0, 138 REG_ENABLE 139 }; 140 141 enum { 142 LDO_OFF = 0, 143 LDO_ON, 144 145 DIS_LDO = (0x00 << 6), 146 EN_LDO = (0x3 << 6), 147 }; 148 149 enum { 150 OPMODE_OFF = 0, 151 OPMODE_LPM, 152 OPMODE_STANDBY, 153 OPMODE_STANDBY_LPM, 154 OPMODE_ON, 155 }; 156 157 #ifdef CONFIG_POWER 158 int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV); 159 int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode); 160 int max77686_set_buck_voltage(struct pmic *p, int buck, ulong uV); 161 int max77686_set_buck_mode(struct pmic *p, int buck, char opmode); 162 #endif 163 164 #define MAX77686_LDO_VOLT_MAX_HEX 0x3f 165 #define MAX77686_LDO_VOLT_MASK 0x3f 166 #define MAX77686_LDO_MODE_MASK 0xc0 167 #define MAX77686_LDO_MODE_OFF (0x00 << 0x06) 168 #define MAX77686_LDO_MODE_LPM (0x01 << 0x06) 169 #define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06) 170 #define MAX77686_LDO_MODE_STANDBY_LPM (0x02 << 0x06) 171 #define MAX77686_LDO_MODE_ON (0x03 << 0x06) 172 #define MAX77686_BUCK234_VOLT_MAX_HEX 0xff 173 #define MAX77686_BUCK234_VOLT_MASK 0xff 174 #define MAX77686_BUCK_VOLT_MAX_HEX 0x3f 175 #define MAX77686_BUCK_VOLT_MASK 0x3f 176 #define MAX77686_BUCK_MODE_MASK 0x03 177 #define MAX77686_BUCK_MODE_SHIFT_1 0x00 178 #define MAX77686_BUCK_MODE_SHIFT_2 0x04 179 #define MAX77686_BUCK_MODE_OFF 0x00 180 #define MAX77686_BUCK_MODE_STANDBY 0x01 181 #define MAX77686_BUCK_MODE_LPM 0x02 182 #define MAX77686_BUCK_MODE_ON 0x03 183 184 /* For regulator hex<->volt conversion */ 185 #define MAX77686_LDO_UV_MIN 800000 /* Minimum LDO uV value */ 186 #define MAX77686_LDO_UV_LSTEP 25000 /* uV lower value step */ 187 #define MAX77686_LDO_UV_HSTEP 50000 /* uV higher value step */ 188 #define MAX77686_BUCK_UV_LMIN 600000 /* Lower minimun BUCK value */ 189 #define MAX77686_BUCK_UV_HMIN 750000 /* Higher minimun BUCK value */ 190 #define MAX77686_BUCK_UV_LSTEP 12500 /* uV lower value step */ 191 #define MAX77686_BUCK_UV_HSTEP 50000 /* uV higher value step */ 192 193 /* Buck1 1 volt value */ 194 #define MAX77686_BUCK1OUT_1V 0x5 195 /* Buck1 1.05 volt value */ 196 #define MAX77686_BUCK1OUT_1_05V 0x6 197 #define MAX77686_BUCK1CTRL_EN (3 << 0) 198 /* Buck2 1.3 volt value */ 199 #define MAX77686_BUCK2DVS1_1_3V 0x38 200 #define MAX77686_BUCK2CTRL_ON (1 << 4) 201 /* Buck3 1.0125 volt value */ 202 #define MAX77686_BUCK3DVS1_1_0125V 0x21 203 #define MAX77686_BUCK3CTRL_ON (1 << 4) 204 /* Buck4 1.2 volt value */ 205 #define MAX77686_BUCK4DVS1_1_2V 0x30 206 #define MAX77686_BUCK4CTRL_ON (1 << 4) 207 /* LDO2 1.5 volt value */ 208 #define MAX77686_LD02CTRL1_1_5V 0x1c 209 /* LDO3 1.8 volt value */ 210 #define MAX77686_LD03CTRL1_1_8V 0x14 211 /* LDO5 1.8 volt value */ 212 #define MAX77686_LD05CTRL1_1_8V 0x14 213 /* LDO10 1.8 volt value */ 214 #define MAX77686_LD10CTRL1_1_8V 0x14 215 /* 216 * MAX77686_REG_PMIC_32KHZ set to 32KH CP 217 * output is activated 218 */ 219 #define MAX77686_32KHCP_EN (1 << 1) 220 /* 221 * MAX77686_REG_PMIC_BBAT set to 222 * Back up batery charger on and 223 * limit voltage setting to 3.5v 224 */ 225 #define MAX77686_BBCHOSTEN (1 << 0) 226 #define MAX77686_BBCVS_3_5V (3 << 3) 227 #endif /* __MAX77686_PMIC_H_ */ 228