1*242b2f0cSPeter Griffin /* 2*242b2f0cSPeter Griffin * (C) Copyright 2015 Linaro 3*242b2f0cSPeter Griffin * Peter Griffin <peter.griffin@linaro.org> 4*242b2f0cSPeter Griffin * 5*242b2f0cSPeter Griffin * SPDX-License-Identifier: GPL-2.0+ 6*242b2f0cSPeter Griffin */ 7*242b2f0cSPeter Griffin 8*242b2f0cSPeter Griffin #ifndef __HI6553_PMIC_H__ 9*242b2f0cSPeter Griffin #define __HI6553_PMIC_H__ 10*242b2f0cSPeter Griffin 11*242b2f0cSPeter Griffin /* Registers */ 12*242b2f0cSPeter Griffin enum { 13*242b2f0cSPeter Griffin HI6553_VERSION_REG = 0x000, 14*242b2f0cSPeter Griffin HI6553_ENABLE2_LDO1_8 = 0x029, 15*242b2f0cSPeter Griffin HI6553_DISABLE2_LDO1_8, 16*242b2f0cSPeter Griffin HI6553_ONOFF_STATUS2_LDO1_8, 17*242b2f0cSPeter Griffin HI6553_ENABLE3_LDO9_16, 18*242b2f0cSPeter Griffin HI6553_DISABLE3_LDO9_16, 19*242b2f0cSPeter Griffin HI6553_ONOFF_STATUS3_LDO9_16, 20*242b2f0cSPeter Griffin 21*242b2f0cSPeter Griffin HI6553_DISABLE6_XO_CLK = 0x036, 22*242b2f0cSPeter Griffin HI6553_PERI_EN_MARK = 0x040, 23*242b2f0cSPeter Griffin HI6553_BUCK2_REG1 = 0x04a, 24*242b2f0cSPeter Griffin HI6553_BUCK2_REG5 = 0x04e, 25*242b2f0cSPeter Griffin HI6553_BUCK2_REG6, 26*242b2f0cSPeter Griffin 27*242b2f0cSPeter Griffin HI6553_BUCK3_REG3 = 0x054, 28*242b2f0cSPeter Griffin HI6553_BUCK3_REG5 = 0x056, 29*242b2f0cSPeter Griffin HI6553_BUCK3_REG6, 30*242b2f0cSPeter Griffin HI6553_BUCK4_REG2 = 0x05b, 31*242b2f0cSPeter Griffin HI6553_BUCK4_REG5 = 0x05e, 32*242b2f0cSPeter Griffin HI6553_BUCK4_REG6, 33*242b2f0cSPeter Griffin 34*242b2f0cSPeter Griffin HI6553_CLK_TOP0 = 0x063, 35*242b2f0cSPeter Griffin HI6553_CLK_TOP3 = 0x066, 36*242b2f0cSPeter Griffin HI6553_CLK_TOP4, 37*242b2f0cSPeter Griffin HI6553_VSET_BUCK2_ADJ = 0x06d, 38*242b2f0cSPeter Griffin HI6553_VSET_BUCK3_ADJ, 39*242b2f0cSPeter Griffin HI6553_LDO7_REG_ADJ = 0x078, 40*242b2f0cSPeter Griffin HI6553_LDO10_REG_ADJ = 0x07b, 41*242b2f0cSPeter Griffin HI6553_LDO19_REG_ADJ = 0x084, 42*242b2f0cSPeter Griffin HI6553_LDO20_REG_ADJ, 43*242b2f0cSPeter Griffin HI6553_DR_LED_CTRL = 0x098, 44*242b2f0cSPeter Griffin HI6553_DR_OUT_CTRL, 45*242b2f0cSPeter Griffin HI6553_DR3_ISET, 46*242b2f0cSPeter Griffin HI6553_DR3_START_DEL, 47*242b2f0cSPeter Griffin HI6553_DR4_ISET, 48*242b2f0cSPeter Griffin HI6553_DR4_START_DEL, 49*242b2f0cSPeter Griffin HI6553_DR345_TIM_CONF0 = 0x0a0, 50*242b2f0cSPeter Griffin HI6553_NP_REG_ADJ1 = 0x0be, 51*242b2f0cSPeter Griffin HI6553_NP_REG_CHG = 0x0c0, 52*242b2f0cSPeter Griffin HI6553_BUCK01_CTRL2 = 0x0d9, 53*242b2f0cSPeter Griffin HI6553_BUCK0_CTRL1 = 0x0dd, 54*242b2f0cSPeter Griffin HI6553_BUCK0_CTRL5 = 0x0e1, 55*242b2f0cSPeter Griffin HI6553_BUCK0_CTRL7 = 0x0e3, 56*242b2f0cSPeter Griffin HI6553_BUCK1_CTRL1 = 0x0e8, 57*242b2f0cSPeter Griffin HI6553_BUCK1_CTRL5 = 0x0ec, 58*242b2f0cSPeter Griffin HI6553_BUCK1_CTRL7 = 0x0ef, 59*242b2f0cSPeter Griffin HI6553_CLK19M2_600_586_EN = 0x0fe, 60*242b2f0cSPeter Griffin }; 61*242b2f0cSPeter Griffin 62*242b2f0cSPeter Griffin #define HI6553_DISABLE6_XO_CLK_BB (1 << 0) 63*242b2f0cSPeter Griffin #define HI6553_DISABLE6_XO_CLK_CONN (1 << 1) 64*242b2f0cSPeter Griffin #define HI6553_DISABLE6_XO_CLK_NFC (1 << 2) 65*242b2f0cSPeter Griffin #define HI6553_DISABLE6_XO_CLK_RF1 (1 << 3) 66*242b2f0cSPeter Griffin #define HI6553_DISABLE6_XO_CLK_RF2 (1 << 4) 67*242b2f0cSPeter Griffin 68*242b2f0cSPeter Griffin #define HI6553_LED_START_DELAY_TIME 0x00 69*242b2f0cSPeter Griffin #define HI6553_LED_ELEC_VALUE 0x07 70*242b2f0cSPeter Griffin #define HI6553_LED_LIGHT_TIME 0xf0 71*242b2f0cSPeter Griffin #define HI6553_LED_GREEN_ENABLE (1 << 1) 72*242b2f0cSPeter Griffin #define HI6553_LED_OUT_CTRL 0x00 73*242b2f0cSPeter Griffin 74*242b2f0cSPeter Griffin #define HI6553_PMU_V300 0x30 75*242b2f0cSPeter Griffin #define HI6553_PMU_V310 0x31 76*242b2f0cSPeter Griffin 77*242b2f0cSPeter Griffin int power_hi6553_init(u8 *base); 78*242b2f0cSPeter Griffin 79*242b2f0cSPeter Griffin #endif /* __HI6553_PMIC_H__ */ 80