xref: /openbmc/u-boot/include/phy.h (revision dfb42fc9)
1 /*
2  * Copyright 2011 Freescale Semiconductor, Inc.
3  *	Andy Fleming <afleming@freescale.com>
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  *
7  * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
8  */
9 
10 #ifndef _PHY_H
11 #define _PHY_H
12 
13 #include <linux/list.h>
14 #include <linux/mii.h>
15 #include <linux/ethtool.h>
16 #include <linux/mdio.h>
17 
18 #define PHY_MAX_ADDR 32
19 
20 #define PHY_BASIC_FEATURES	(SUPPORTED_10baseT_Half | \
21 				 SUPPORTED_10baseT_Full | \
22 				 SUPPORTED_100baseT_Half | \
23 				 SUPPORTED_100baseT_Full | \
24 				 SUPPORTED_Autoneg | \
25 				 SUPPORTED_TP | \
26 				 SUPPORTED_MII)
27 
28 #define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
29 				 SUPPORTED_1000baseT_Half | \
30 				 SUPPORTED_1000baseT_Full)
31 
32 #define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
33 				SUPPORTED_10000baseT_Full)
34 
35 #define PHY_ANEG_TIMEOUT	4000
36 
37 
38 typedef enum {
39 	PHY_INTERFACE_MODE_MII,
40 	PHY_INTERFACE_MODE_GMII,
41 	PHY_INTERFACE_MODE_SGMII,
42 	PHY_INTERFACE_MODE_QSGMII,
43 	PHY_INTERFACE_MODE_TBI,
44 	PHY_INTERFACE_MODE_RMII,
45 	PHY_INTERFACE_MODE_RGMII,
46 	PHY_INTERFACE_MODE_RGMII_ID,
47 	PHY_INTERFACE_MODE_RGMII_RXID,
48 	PHY_INTERFACE_MODE_RGMII_TXID,
49 	PHY_INTERFACE_MODE_RTBI,
50 	PHY_INTERFACE_MODE_XGMII,
51 	PHY_INTERFACE_MODE_NONE	/* Must be last */
52 } phy_interface_t;
53 
54 static const char *phy_interface_strings[] = {
55 	[PHY_INTERFACE_MODE_MII]		= "mii",
56 	[PHY_INTERFACE_MODE_GMII]		= "gmii",
57 	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
58 	[PHY_INTERFACE_MODE_QSGMII]		= "qsgmii",
59 	[PHY_INTERFACE_MODE_TBI]		= "tbi",
60 	[PHY_INTERFACE_MODE_RMII]		= "rmii",
61 	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
62 	[PHY_INTERFACE_MODE_RGMII_ID]		= "rgmii-id",
63 	[PHY_INTERFACE_MODE_RGMII_RXID]		= "rgmii-rxid",
64 	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
65 	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
66 	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
67 	[PHY_INTERFACE_MODE_NONE]		= "",
68 };
69 
70 static inline const char *phy_string_for_interface(phy_interface_t i)
71 {
72 	/* Default to unknown */
73 	if (i > PHY_INTERFACE_MODE_NONE)
74 		i = PHY_INTERFACE_MODE_NONE;
75 
76 	return phy_interface_strings[i];
77 }
78 
79 
80 struct phy_device;
81 
82 #define MDIO_NAME_LEN 32
83 
84 struct mii_dev {
85 	struct list_head link;
86 	char name[MDIO_NAME_LEN];
87 	void *priv;
88 	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
89 	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
90 			u16 val);
91 	int (*reset)(struct mii_dev *bus);
92 	struct phy_device *phymap[PHY_MAX_ADDR];
93 	u32 phy_mask;
94 };
95 
96 /* struct phy_driver: a structure which defines PHY behavior
97  *
98  * uid will contain a number which represents the PHY.  During
99  * startup, the driver will poll the PHY to find out what its
100  * UID--as defined by registers 2 and 3--is.  The 32-bit result
101  * gotten from the PHY will be masked to
102  * discard any bits which may change based on revision numbers
103  * unimportant to functionality
104  *
105  */
106 struct phy_driver {
107 	char *name;
108 	unsigned int uid;
109 	unsigned int mask;
110 	unsigned int mmds;
111 
112 	u32 features;
113 
114 	/* Called to do any driver startup necessities */
115 	/* Will be called during phy_connect */
116 	int (*probe)(struct phy_device *phydev);
117 
118 	/* Called to configure the PHY, and modify the controller
119 	 * based on the results.  Should be called after phy_connect */
120 	int (*config)(struct phy_device *phydev);
121 
122 	/* Called when starting up the controller */
123 	int (*startup)(struct phy_device *phydev);
124 
125 	/* Called when bringing down the controller */
126 	int (*shutdown)(struct phy_device *phydev);
127 
128 	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
129 	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
130 			u16 val);
131 	struct list_head list;
132 };
133 
134 struct phy_device {
135 	/* Information about the PHY type */
136 	/* And management functions */
137 	struct mii_dev *bus;
138 	struct phy_driver *drv;
139 	void *priv;
140 
141 	struct eth_device *dev;
142 
143 	/* forced speed & duplex (no autoneg)
144 	 * partner speed & duplex & pause (autoneg)
145 	 */
146 	int speed;
147 	int duplex;
148 
149 	/* The most recently read link state */
150 	int link;
151 	int port;
152 	phy_interface_t interface;
153 
154 	u32 advertising;
155 	u32 supported;
156 	u32 mmds;
157 
158 	int autoneg;
159 	int addr;
160 	int pause;
161 	int asym_pause;
162 	u32 phy_id;
163 	u32 flags;
164 };
165 
166 struct fixed_link {
167 	int phy_id;
168 	int duplex;
169 	int link_speed;
170 	int pause;
171 	int asym_pause;
172 };
173 
174 static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
175 {
176 	struct mii_dev *bus = phydev->bus;
177 
178 	return bus->read(bus, phydev->addr, devad, regnum);
179 }
180 
181 static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
182 			u16 val)
183 {
184 	struct mii_dev *bus = phydev->bus;
185 
186 	return bus->write(bus, phydev->addr, devad, regnum, val);
187 }
188 
189 #ifdef CONFIG_PHYLIB_10G
190 extern struct phy_driver gen10g_driver;
191 
192 /* For now, XGMII is the only 10G interface */
193 static inline int is_10g_interface(phy_interface_t interface)
194 {
195 	return interface == PHY_INTERFACE_MODE_XGMII;
196 }
197 
198 #endif
199 
200 int phy_init(void);
201 int phy_reset(struct phy_device *phydev);
202 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
203 		phy_interface_t interface);
204 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
205 struct phy_device *phy_connect(struct mii_dev *bus, int addr,
206 				struct eth_device *dev,
207 				phy_interface_t interface);
208 int phy_startup(struct phy_device *phydev);
209 int phy_config(struct phy_device *phydev);
210 int phy_shutdown(struct phy_device *phydev);
211 int phy_register(struct phy_driver *drv);
212 int genphy_config_aneg(struct phy_device *phydev);
213 int genphy_restart_aneg(struct phy_device *phydev);
214 int genphy_update_link(struct phy_device *phydev);
215 int genphy_parse_link(struct phy_device *phydev);
216 int genphy_config(struct phy_device *phydev);
217 int genphy_startup(struct phy_device *phydev);
218 int genphy_shutdown(struct phy_device *phydev);
219 int gen10g_config(struct phy_device *phydev);
220 int gen10g_startup(struct phy_device *phydev);
221 int gen10g_shutdown(struct phy_device *phydev);
222 int gen10g_discover_mmds(struct phy_device *phydev);
223 
224 int phy_atheros_init(void);
225 int phy_broadcom_init(void);
226 int phy_davicom_init(void);
227 int phy_et1011c_init(void);
228 int phy_lxt_init(void);
229 int phy_marvell_init(void);
230 int phy_micrel_init(void);
231 int phy_natsemi_init(void);
232 int phy_realtek_init(void);
233 int phy_smsc_init(void);
234 int phy_teranetics_init(void);
235 int phy_vitesse_init(void);
236 
237 int board_phy_config(struct phy_device *phydev);
238 
239 /* PHY UIDs for various PHYs that are referenced in external code */
240 #define PHY_UID_TN2020	0x00a19410
241 
242 #endif
243