1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Andy Fleming <afleming@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h 8 */ 9 10 #ifndef _PHY_H 11 #define _PHY_H 12 13 #include <linux/list.h> 14 #include <linux/mii.h> 15 #include <linux/ethtool.h> 16 #include <linux/mdio.h> 17 18 #define PHY_FIXED_ID 0xa5a55a5a 19 20 #define PHY_MAX_ADDR 32 21 22 #define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ 23 24 #define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ 25 SUPPORTED_TP | \ 26 SUPPORTED_MII) 27 28 #define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ 29 SUPPORTED_10baseT_Full) 30 31 #define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ 32 SUPPORTED_100baseT_Full) 33 34 #define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ 35 SUPPORTED_1000baseT_Full) 36 37 #define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \ 38 PHY_100BT_FEATURES | \ 39 PHY_DEFAULT_FEATURES) 40 41 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ 42 PHY_1000BT_FEATURES) 43 44 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ 45 SUPPORTED_10000baseT_Full) 46 47 #ifndef PHY_ANEG_TIMEOUT 48 #define PHY_ANEG_TIMEOUT 4000 49 #endif 50 51 52 typedef enum { 53 PHY_INTERFACE_MODE_MII, 54 PHY_INTERFACE_MODE_GMII, 55 PHY_INTERFACE_MODE_SGMII, 56 PHY_INTERFACE_MODE_SGMII_2500, 57 PHY_INTERFACE_MODE_QSGMII, 58 PHY_INTERFACE_MODE_TBI, 59 PHY_INTERFACE_MODE_RMII, 60 PHY_INTERFACE_MODE_RGMII, 61 PHY_INTERFACE_MODE_RGMII_ID, 62 PHY_INTERFACE_MODE_RGMII_RXID, 63 PHY_INTERFACE_MODE_RGMII_TXID, 64 PHY_INTERFACE_MODE_RTBI, 65 PHY_INTERFACE_MODE_XGMII, 66 PHY_INTERFACE_MODE_NONE, /* Must be last */ 67 68 PHY_INTERFACE_MODE_COUNT, 69 } phy_interface_t; 70 71 static const char *phy_interface_strings[] = { 72 [PHY_INTERFACE_MODE_MII] = "mii", 73 [PHY_INTERFACE_MODE_GMII] = "gmii", 74 [PHY_INTERFACE_MODE_SGMII] = "sgmii", 75 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", 76 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", 77 [PHY_INTERFACE_MODE_TBI] = "tbi", 78 [PHY_INTERFACE_MODE_RMII] = "rmii", 79 [PHY_INTERFACE_MODE_RGMII] = "rgmii", 80 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", 81 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", 82 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", 83 [PHY_INTERFACE_MODE_RTBI] = "rtbi", 84 [PHY_INTERFACE_MODE_XGMII] = "xgmii", 85 [PHY_INTERFACE_MODE_NONE] = "", 86 }; 87 88 static inline const char *phy_string_for_interface(phy_interface_t i) 89 { 90 /* Default to unknown */ 91 if (i > PHY_INTERFACE_MODE_NONE) 92 i = PHY_INTERFACE_MODE_NONE; 93 94 return phy_interface_strings[i]; 95 } 96 97 98 struct phy_device; 99 100 #define MDIO_NAME_LEN 32 101 102 struct mii_dev { 103 struct list_head link; 104 char name[MDIO_NAME_LEN]; 105 void *priv; 106 int (*read)(struct mii_dev *bus, int addr, int devad, int reg); 107 int (*write)(struct mii_dev *bus, int addr, int devad, int reg, 108 u16 val); 109 int (*reset)(struct mii_dev *bus); 110 struct phy_device *phymap[PHY_MAX_ADDR]; 111 u32 phy_mask; 112 }; 113 114 /* struct phy_driver: a structure which defines PHY behavior 115 * 116 * uid will contain a number which represents the PHY. During 117 * startup, the driver will poll the PHY to find out what its 118 * UID--as defined by registers 2 and 3--is. The 32-bit result 119 * gotten from the PHY will be masked to 120 * discard any bits which may change based on revision numbers 121 * unimportant to functionality 122 * 123 */ 124 struct phy_driver { 125 char *name; 126 unsigned int uid; 127 unsigned int mask; 128 unsigned int mmds; 129 130 u32 features; 131 132 /* Called to do any driver startup necessities */ 133 /* Will be called during phy_connect */ 134 int (*probe)(struct phy_device *phydev); 135 136 /* Called to configure the PHY, and modify the controller 137 * based on the results. Should be called after phy_connect */ 138 int (*config)(struct phy_device *phydev); 139 140 /* Called when starting up the controller */ 141 int (*startup)(struct phy_device *phydev); 142 143 /* Called when bringing down the controller */ 144 int (*shutdown)(struct phy_device *phydev); 145 146 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); 147 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, 148 u16 val); 149 struct list_head list; 150 }; 151 152 struct phy_device { 153 /* Information about the PHY type */ 154 /* And management functions */ 155 struct mii_dev *bus; 156 struct phy_driver *drv; 157 void *priv; 158 159 #ifdef CONFIG_DM_ETH 160 struct udevice *dev; 161 #else 162 struct eth_device *dev; 163 #endif 164 165 /* forced speed & duplex (no autoneg) 166 * partner speed & duplex & pause (autoneg) 167 */ 168 int speed; 169 int duplex; 170 171 /* The most recently read link state */ 172 int link; 173 int port; 174 phy_interface_t interface; 175 176 u32 advertising; 177 u32 supported; 178 u32 mmds; 179 180 int autoneg; 181 int addr; 182 int pause; 183 int asym_pause; 184 u32 phy_id; 185 u32 flags; 186 }; 187 188 struct fixed_link { 189 int phy_id; 190 int duplex; 191 int link_speed; 192 int pause; 193 int asym_pause; 194 }; 195 196 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) 197 { 198 struct mii_dev *bus = phydev->bus; 199 200 return bus->read(bus, phydev->addr, devad, regnum); 201 } 202 203 static inline int phy_write(struct phy_device *phydev, int devad, int regnum, 204 u16 val) 205 { 206 struct mii_dev *bus = phydev->bus; 207 208 return bus->write(bus, phydev->addr, devad, regnum, val); 209 } 210 211 #ifdef CONFIG_PHYLIB_10G 212 extern struct phy_driver gen10g_driver; 213 214 /* For now, XGMII is the only 10G interface */ 215 static inline int is_10g_interface(phy_interface_t interface) 216 { 217 return interface == PHY_INTERFACE_MODE_XGMII; 218 } 219 220 #endif 221 222 int phy_init(void); 223 int phy_reset(struct phy_device *phydev); 224 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, 225 phy_interface_t interface); 226 #ifdef CONFIG_DM_ETH 227 void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); 228 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 229 struct udevice *dev, 230 phy_interface_t interface); 231 #else 232 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); 233 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 234 struct eth_device *dev, 235 phy_interface_t interface); 236 #endif 237 int phy_startup(struct phy_device *phydev); 238 int phy_config(struct phy_device *phydev); 239 int phy_shutdown(struct phy_device *phydev); 240 int phy_register(struct phy_driver *drv); 241 int phy_set_supported(struct phy_device *phydev, u32 max_speed); 242 int genphy_config_aneg(struct phy_device *phydev); 243 int genphy_restart_aneg(struct phy_device *phydev); 244 int genphy_update_link(struct phy_device *phydev); 245 int genphy_parse_link(struct phy_device *phydev); 246 int genphy_config(struct phy_device *phydev); 247 int genphy_startup(struct phy_device *phydev); 248 int genphy_shutdown(struct phy_device *phydev); 249 int gen10g_config(struct phy_device *phydev); 250 int gen10g_startup(struct phy_device *phydev); 251 int gen10g_shutdown(struct phy_device *phydev); 252 int gen10g_discover_mmds(struct phy_device *phydev); 253 254 int phy_mv88e61xx_init(void); 255 int phy_aquantia_init(void); 256 int phy_atheros_init(void); 257 int phy_broadcom_init(void); 258 int phy_cortina_init(void); 259 int phy_davicom_init(void); 260 int phy_et1011c_init(void); 261 int phy_lxt_init(void); 262 int phy_marvell_init(void); 263 int phy_micrel_init(void); 264 int phy_natsemi_init(void); 265 int phy_realtek_init(void); 266 int phy_smsc_init(void); 267 int phy_teranetics_init(void); 268 int phy_ti_init(void); 269 int phy_vitesse_init(void); 270 int phy_xilinx_init(void); 271 int phy_mscc_init(void); 272 int phy_fixed_init(void); 273 274 int board_phy_config(struct phy_device *phydev); 275 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); 276 277 /** 278 * phy_get_interface_by_name() - Look up a PHY interface name 279 * 280 * @str: PHY interface name, e.g. "mii" 281 * @return PHY_INTERFACE_MODE_... value, or -1 if not found 282 */ 283 int phy_get_interface_by_name(const char *str); 284 285 /** 286 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 287 * is RGMII (all variants) 288 * @phydev: the phy_device struct 289 */ 290 static inline bool phy_interface_is_rgmii(struct phy_device *phydev) 291 { 292 return phydev->interface >= PHY_INTERFACE_MODE_RGMII && 293 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; 294 } 295 296 /** 297 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface 298 * is SGMII (all variants) 299 * @phydev: the phy_device struct 300 */ 301 static inline bool phy_interface_is_sgmii(struct phy_device *phydev) 302 { 303 return phydev->interface >= PHY_INTERFACE_MODE_SGMII && 304 phydev->interface <= PHY_INTERFACE_MODE_QSGMII; 305 } 306 307 /* PHY UIDs for various PHYs that are referenced in external code */ 308 #define PHY_UID_CS4340 0x13e51002 309 #define PHY_UID_TN2020 0x00a19410 310 311 #endif 312