1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011 Freescale Semiconductor, Inc. 4 * Andy Fleming <afleming@gmail.com> 5 * 6 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h 7 */ 8 9 #ifndef _PHY_H 10 #define _PHY_H 11 12 #include <linux/list.h> 13 #include <linux/mii.h> 14 #include <linux/ethtool.h> 15 #include <linux/mdio.h> 16 17 #define PHY_FIXED_ID 0xa5a55a5a 18 19 #define PHY_MAX_ADDR 32 20 21 #define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ 22 23 #define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ 24 SUPPORTED_TP | \ 25 SUPPORTED_MII) 26 27 #define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ 28 SUPPORTED_10baseT_Full) 29 30 #define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ 31 SUPPORTED_100baseT_Full) 32 33 #define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ 34 SUPPORTED_1000baseT_Full) 35 36 #define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \ 37 PHY_100BT_FEATURES | \ 38 PHY_DEFAULT_FEATURES) 39 40 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ 41 PHY_1000BT_FEATURES) 42 43 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ 44 SUPPORTED_10000baseT_Full) 45 46 #ifndef PHY_ANEG_TIMEOUT 47 #define PHY_ANEG_TIMEOUT 4000 48 #endif 49 50 51 typedef enum { 52 PHY_INTERFACE_MODE_MII, 53 PHY_INTERFACE_MODE_GMII, 54 PHY_INTERFACE_MODE_SGMII, 55 PHY_INTERFACE_MODE_SGMII_2500, 56 PHY_INTERFACE_MODE_QSGMII, 57 PHY_INTERFACE_MODE_TBI, 58 PHY_INTERFACE_MODE_RMII, 59 PHY_INTERFACE_MODE_RGMII, 60 PHY_INTERFACE_MODE_RGMII_ID, 61 PHY_INTERFACE_MODE_RGMII_RXID, 62 PHY_INTERFACE_MODE_RGMII_TXID, 63 PHY_INTERFACE_MODE_RTBI, 64 PHY_INTERFACE_MODE_XGMII, 65 PHY_INTERFACE_MODE_XAUI, 66 PHY_INTERFACE_MODE_RXAUI, 67 PHY_INTERFACE_MODE_SFI, 68 PHY_INTERFACE_MODE_NONE, /* Must be last */ 69 70 PHY_INTERFACE_MODE_COUNT, 71 } phy_interface_t; 72 73 static const char *phy_interface_strings[] = { 74 [PHY_INTERFACE_MODE_MII] = "mii", 75 [PHY_INTERFACE_MODE_GMII] = "gmii", 76 [PHY_INTERFACE_MODE_SGMII] = "sgmii", 77 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", 78 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", 79 [PHY_INTERFACE_MODE_TBI] = "tbi", 80 [PHY_INTERFACE_MODE_RMII] = "rmii", 81 [PHY_INTERFACE_MODE_RGMII] = "rgmii", 82 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", 83 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", 84 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", 85 [PHY_INTERFACE_MODE_RTBI] = "rtbi", 86 [PHY_INTERFACE_MODE_XGMII] = "xgmii", 87 [PHY_INTERFACE_MODE_XAUI] = "xaui", 88 [PHY_INTERFACE_MODE_RXAUI] = "rxaui", 89 [PHY_INTERFACE_MODE_SFI] = "sfi", 90 [PHY_INTERFACE_MODE_NONE] = "", 91 }; 92 93 static inline const char *phy_string_for_interface(phy_interface_t i) 94 { 95 /* Default to unknown */ 96 if (i > PHY_INTERFACE_MODE_NONE) 97 i = PHY_INTERFACE_MODE_NONE; 98 99 return phy_interface_strings[i]; 100 } 101 102 103 struct phy_device; 104 105 #define MDIO_NAME_LEN 32 106 107 struct mii_dev { 108 struct list_head link; 109 char name[MDIO_NAME_LEN]; 110 void *priv; 111 int (*read)(struct mii_dev *bus, int addr, int devad, int reg); 112 int (*write)(struct mii_dev *bus, int addr, int devad, int reg, 113 u16 val); 114 int (*reset)(struct mii_dev *bus); 115 struct phy_device *phymap[PHY_MAX_ADDR]; 116 u32 phy_mask; 117 }; 118 119 /* struct phy_driver: a structure which defines PHY behavior 120 * 121 * uid will contain a number which represents the PHY. During 122 * startup, the driver will poll the PHY to find out what its 123 * UID--as defined by registers 2 and 3--is. The 32-bit result 124 * gotten from the PHY will be masked to 125 * discard any bits which may change based on revision numbers 126 * unimportant to functionality 127 * 128 */ 129 struct phy_driver { 130 char *name; 131 unsigned int uid; 132 unsigned int mask; 133 unsigned int mmds; 134 135 u32 features; 136 137 /* Called to do any driver startup necessities */ 138 /* Will be called during phy_connect */ 139 int (*probe)(struct phy_device *phydev); 140 141 /* Called to configure the PHY, and modify the controller 142 * based on the results. Should be called after phy_connect */ 143 int (*config)(struct phy_device *phydev); 144 145 /* Called when starting up the controller */ 146 int (*startup)(struct phy_device *phydev); 147 148 /* Called when bringing down the controller */ 149 int (*shutdown)(struct phy_device *phydev); 150 151 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); 152 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, 153 u16 val); 154 struct list_head list; 155 }; 156 157 struct phy_device { 158 /* Information about the PHY type */ 159 /* And management functions */ 160 struct mii_dev *bus; 161 struct phy_driver *drv; 162 void *priv; 163 164 #ifdef CONFIG_DM_ETH 165 struct udevice *dev; 166 #else 167 struct eth_device *dev; 168 #endif 169 170 /* forced speed & duplex (no autoneg) 171 * partner speed & duplex & pause (autoneg) 172 */ 173 int speed; 174 int duplex; 175 176 /* The most recently read link state */ 177 int link; 178 int port; 179 phy_interface_t interface; 180 181 u32 advertising; 182 u32 supported; 183 u32 mmds; 184 185 int autoneg; 186 int addr; 187 int pause; 188 int asym_pause; 189 u32 phy_id; 190 u32 flags; 191 }; 192 193 struct fixed_link { 194 int phy_id; 195 int duplex; 196 int link_speed; 197 int pause; 198 int asym_pause; 199 }; 200 201 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) 202 { 203 struct mii_dev *bus = phydev->bus; 204 205 return bus->read(bus, phydev->addr, devad, regnum); 206 } 207 208 static inline int phy_write(struct phy_device *phydev, int devad, int regnum, 209 u16 val) 210 { 211 struct mii_dev *bus = phydev->bus; 212 213 return bus->write(bus, phydev->addr, devad, regnum, val); 214 } 215 216 #ifdef CONFIG_PHYLIB_10G 217 extern struct phy_driver gen10g_driver; 218 219 /* For now, XGMII is the only 10G interface */ 220 static inline int is_10g_interface(phy_interface_t interface) 221 { 222 return interface == PHY_INTERFACE_MODE_XGMII; 223 } 224 225 #endif 226 227 int phy_init(void); 228 int phy_reset(struct phy_device *phydev); 229 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, 230 phy_interface_t interface); 231 #ifdef CONFIG_DM_ETH 232 void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); 233 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 234 struct udevice *dev, 235 phy_interface_t interface); 236 #else 237 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); 238 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 239 struct eth_device *dev, 240 phy_interface_t interface); 241 #endif 242 int phy_startup(struct phy_device *phydev); 243 int phy_config(struct phy_device *phydev); 244 int phy_shutdown(struct phy_device *phydev); 245 int phy_register(struct phy_driver *drv); 246 int phy_set_supported(struct phy_device *phydev, u32 max_speed); 247 int genphy_config_aneg(struct phy_device *phydev); 248 int genphy_restart_aneg(struct phy_device *phydev); 249 int genphy_update_link(struct phy_device *phydev); 250 int genphy_parse_link(struct phy_device *phydev); 251 int genphy_config(struct phy_device *phydev); 252 int genphy_startup(struct phy_device *phydev); 253 int genphy_shutdown(struct phy_device *phydev); 254 int gen10g_config(struct phy_device *phydev); 255 int gen10g_startup(struct phy_device *phydev); 256 int gen10g_shutdown(struct phy_device *phydev); 257 int gen10g_discover_mmds(struct phy_device *phydev); 258 259 int phy_b53_init(void); 260 int phy_mv88e61xx_init(void); 261 int phy_aquantia_init(void); 262 int phy_atheros_init(void); 263 int phy_broadcom_init(void); 264 int phy_cortina_init(void); 265 int phy_davicom_init(void); 266 int phy_et1011c_init(void); 267 int phy_lxt_init(void); 268 int phy_marvell_init(void); 269 int phy_micrel_ksz8xxx_init(void); 270 int phy_micrel_ksz90x1_init(void); 271 int phy_meson_gxl_init(void); 272 int phy_natsemi_init(void); 273 int phy_realtek_init(void); 274 int phy_smsc_init(void); 275 int phy_teranetics_init(void); 276 int phy_ti_init(void); 277 int phy_vitesse_init(void); 278 int phy_xilinx_init(void); 279 int phy_mscc_init(void); 280 int phy_fixed_init(void); 281 282 int board_phy_config(struct phy_device *phydev); 283 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); 284 285 /** 286 * phy_get_interface_by_name() - Look up a PHY interface name 287 * 288 * @str: PHY interface name, e.g. "mii" 289 * @return PHY_INTERFACE_MODE_... value, or -1 if not found 290 */ 291 int phy_get_interface_by_name(const char *str); 292 293 /** 294 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 295 * is RGMII (all variants) 296 * @phydev: the phy_device struct 297 */ 298 static inline bool phy_interface_is_rgmii(struct phy_device *phydev) 299 { 300 return phydev->interface >= PHY_INTERFACE_MODE_RGMII && 301 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; 302 } 303 304 /** 305 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface 306 * is SGMII (all variants) 307 * @phydev: the phy_device struct 308 */ 309 static inline bool phy_interface_is_sgmii(struct phy_device *phydev) 310 { 311 return phydev->interface >= PHY_INTERFACE_MODE_SGMII && 312 phydev->interface <= PHY_INTERFACE_MODE_QSGMII; 313 } 314 315 /* PHY UIDs for various PHYs that are referenced in external code */ 316 #define PHY_UID_CS4340 0x13e51002 317 #define PHY_UID_TN2020 0x00a19410 318 319 #endif 320