1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Andy Fleming <afleming@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h 8 */ 9 10 #ifndef _PHY_H 11 #define _PHY_H 12 13 #include <linux/list.h> 14 #include <linux/mii.h> 15 #include <linux/ethtool.h> 16 #include <linux/mdio.h> 17 18 #define PHY_MAX_ADDR 32 19 20 #define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ 21 SUPPORTED_10baseT_Full | \ 22 SUPPORTED_100baseT_Half | \ 23 SUPPORTED_100baseT_Full | \ 24 SUPPORTED_Autoneg | \ 25 SUPPORTED_TP | \ 26 SUPPORTED_MII) 27 28 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ 29 SUPPORTED_1000baseT_Half | \ 30 SUPPORTED_1000baseT_Full) 31 32 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ 33 SUPPORTED_10000baseT_Full) 34 35 #ifndef PHY_ANEG_TIMEOUT 36 #define PHY_ANEG_TIMEOUT 4000 37 #endif 38 39 40 typedef enum { 41 PHY_INTERFACE_MODE_MII, 42 PHY_INTERFACE_MODE_GMII, 43 PHY_INTERFACE_MODE_SGMII, 44 PHY_INTERFACE_MODE_SGMII_2500, 45 PHY_INTERFACE_MODE_QSGMII, 46 PHY_INTERFACE_MODE_TBI, 47 PHY_INTERFACE_MODE_RMII, 48 PHY_INTERFACE_MODE_RGMII, 49 PHY_INTERFACE_MODE_RGMII_ID, 50 PHY_INTERFACE_MODE_RGMII_RXID, 51 PHY_INTERFACE_MODE_RGMII_TXID, 52 PHY_INTERFACE_MODE_RTBI, 53 PHY_INTERFACE_MODE_XGMII, 54 PHY_INTERFACE_MODE_NONE /* Must be last */ 55 } phy_interface_t; 56 57 static const char *phy_interface_strings[] = { 58 [PHY_INTERFACE_MODE_MII] = "mii", 59 [PHY_INTERFACE_MODE_GMII] = "gmii", 60 [PHY_INTERFACE_MODE_SGMII] = "sgmii", 61 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", 62 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", 63 [PHY_INTERFACE_MODE_TBI] = "tbi", 64 [PHY_INTERFACE_MODE_RMII] = "rmii", 65 [PHY_INTERFACE_MODE_RGMII] = "rgmii", 66 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", 67 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", 68 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", 69 [PHY_INTERFACE_MODE_RTBI] = "rtbi", 70 [PHY_INTERFACE_MODE_XGMII] = "xgmii", 71 [PHY_INTERFACE_MODE_NONE] = "", 72 }; 73 74 static inline const char *phy_string_for_interface(phy_interface_t i) 75 { 76 /* Default to unknown */ 77 if (i > PHY_INTERFACE_MODE_NONE) 78 i = PHY_INTERFACE_MODE_NONE; 79 80 return phy_interface_strings[i]; 81 } 82 83 84 struct phy_device; 85 86 #define MDIO_NAME_LEN 32 87 88 struct mii_dev { 89 struct list_head link; 90 char name[MDIO_NAME_LEN]; 91 void *priv; 92 int (*read)(struct mii_dev *bus, int addr, int devad, int reg); 93 int (*write)(struct mii_dev *bus, int addr, int devad, int reg, 94 u16 val); 95 int (*reset)(struct mii_dev *bus); 96 struct phy_device *phymap[PHY_MAX_ADDR]; 97 u32 phy_mask; 98 }; 99 100 /* struct phy_driver: a structure which defines PHY behavior 101 * 102 * uid will contain a number which represents the PHY. During 103 * startup, the driver will poll the PHY to find out what its 104 * UID--as defined by registers 2 and 3--is. The 32-bit result 105 * gotten from the PHY will be masked to 106 * discard any bits which may change based on revision numbers 107 * unimportant to functionality 108 * 109 */ 110 struct phy_driver { 111 char *name; 112 unsigned int uid; 113 unsigned int mask; 114 unsigned int mmds; 115 116 u32 features; 117 118 /* Called to do any driver startup necessities */ 119 /* Will be called during phy_connect */ 120 int (*probe)(struct phy_device *phydev); 121 122 /* Called to configure the PHY, and modify the controller 123 * based on the results. Should be called after phy_connect */ 124 int (*config)(struct phy_device *phydev); 125 126 /* Called when starting up the controller */ 127 int (*startup)(struct phy_device *phydev); 128 129 /* Called when bringing down the controller */ 130 int (*shutdown)(struct phy_device *phydev); 131 132 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); 133 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, 134 u16 val); 135 struct list_head list; 136 }; 137 138 struct phy_device { 139 /* Information about the PHY type */ 140 /* And management functions */ 141 struct mii_dev *bus; 142 struct phy_driver *drv; 143 void *priv; 144 145 struct eth_device *dev; 146 147 /* forced speed & duplex (no autoneg) 148 * partner speed & duplex & pause (autoneg) 149 */ 150 int speed; 151 int duplex; 152 153 /* The most recently read link state */ 154 int link; 155 int port; 156 phy_interface_t interface; 157 158 u32 advertising; 159 u32 supported; 160 u32 mmds; 161 162 int autoneg; 163 int addr; 164 int pause; 165 int asym_pause; 166 u32 phy_id; 167 u32 flags; 168 }; 169 170 struct fixed_link { 171 int phy_id; 172 int duplex; 173 int link_speed; 174 int pause; 175 int asym_pause; 176 }; 177 178 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) 179 { 180 struct mii_dev *bus = phydev->bus; 181 182 return bus->read(bus, phydev->addr, devad, regnum); 183 } 184 185 static inline int phy_write(struct phy_device *phydev, int devad, int regnum, 186 u16 val) 187 { 188 struct mii_dev *bus = phydev->bus; 189 190 return bus->write(bus, phydev->addr, devad, regnum, val); 191 } 192 193 #ifdef CONFIG_PHYLIB_10G 194 extern struct phy_driver gen10g_driver; 195 196 /* For now, XGMII is the only 10G interface */ 197 static inline int is_10g_interface(phy_interface_t interface) 198 { 199 return interface == PHY_INTERFACE_MODE_XGMII; 200 } 201 202 #endif 203 204 int phy_init(void); 205 int phy_reset(struct phy_device *phydev); 206 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, 207 phy_interface_t interface); 208 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); 209 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 210 struct eth_device *dev, 211 phy_interface_t interface); 212 int phy_startup(struct phy_device *phydev); 213 int phy_config(struct phy_device *phydev); 214 int phy_shutdown(struct phy_device *phydev); 215 int phy_register(struct phy_driver *drv); 216 int genphy_config_aneg(struct phy_device *phydev); 217 int genphy_restart_aneg(struct phy_device *phydev); 218 int genphy_update_link(struct phy_device *phydev); 219 int genphy_parse_link(struct phy_device *phydev); 220 int genphy_config(struct phy_device *phydev); 221 int genphy_startup(struct phy_device *phydev); 222 int genphy_shutdown(struct phy_device *phydev); 223 int gen10g_config(struct phy_device *phydev); 224 int gen10g_startup(struct phy_device *phydev); 225 int gen10g_shutdown(struct phy_device *phydev); 226 int gen10g_discover_mmds(struct phy_device *phydev); 227 228 int phy_aquantia_init(void); 229 int phy_atheros_init(void); 230 int phy_broadcom_init(void); 231 int phy_cortina_init(void); 232 int phy_davicom_init(void); 233 int phy_et1011c_init(void); 234 int phy_lxt_init(void); 235 int phy_marvell_init(void); 236 int phy_micrel_init(void); 237 int phy_natsemi_init(void); 238 int phy_realtek_init(void); 239 int phy_smsc_init(void); 240 int phy_teranetics_init(void); 241 int phy_vitesse_init(void); 242 243 int board_phy_config(struct phy_device *phydev); 244 245 /* PHY UIDs for various PHYs that are referenced in external code */ 246 #define PHY_UID_CS4340 0x13e51002 247 #define PHY_UID_TN2020 0x00a19410 248 249 #endif 250