1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Andy Fleming <afleming@gmail.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h 8 */ 9 10 #ifndef _PHY_H 11 #define _PHY_H 12 13 #include <linux/list.h> 14 #include <linux/mii.h> 15 #include <linux/ethtool.h> 16 #include <linux/mdio.h> 17 18 #define PHY_MAX_ADDR 32 19 20 #define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ 21 SUPPORTED_10baseT_Full | \ 22 SUPPORTED_100baseT_Half | \ 23 SUPPORTED_100baseT_Full | \ 24 SUPPORTED_Autoneg | \ 25 SUPPORTED_TP | \ 26 SUPPORTED_MII) 27 28 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ 29 SUPPORTED_1000baseT_Half | \ 30 SUPPORTED_1000baseT_Full) 31 32 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ 33 SUPPORTED_10000baseT_Full) 34 35 #ifndef PHY_ANEG_TIMEOUT 36 #define PHY_ANEG_TIMEOUT 4000 37 #endif 38 39 40 typedef enum { 41 PHY_INTERFACE_MODE_MII, 42 PHY_INTERFACE_MODE_GMII, 43 PHY_INTERFACE_MODE_SGMII, 44 PHY_INTERFACE_MODE_SGMII_2500, 45 PHY_INTERFACE_MODE_QSGMII, 46 PHY_INTERFACE_MODE_TBI, 47 PHY_INTERFACE_MODE_RMII, 48 PHY_INTERFACE_MODE_RGMII, 49 PHY_INTERFACE_MODE_RGMII_ID, 50 PHY_INTERFACE_MODE_RGMII_RXID, 51 PHY_INTERFACE_MODE_RGMII_TXID, 52 PHY_INTERFACE_MODE_RTBI, 53 PHY_INTERFACE_MODE_XGMII, 54 PHY_INTERFACE_MODE_NONE, /* Must be last */ 55 56 PHY_INTERFACE_MODE_COUNT, 57 } phy_interface_t; 58 59 static const char *phy_interface_strings[] = { 60 [PHY_INTERFACE_MODE_MII] = "mii", 61 [PHY_INTERFACE_MODE_GMII] = "gmii", 62 [PHY_INTERFACE_MODE_SGMII] = "sgmii", 63 [PHY_INTERFACE_MODE_SGMII_2500] = "sgmii-2500", 64 [PHY_INTERFACE_MODE_QSGMII] = "qsgmii", 65 [PHY_INTERFACE_MODE_TBI] = "tbi", 66 [PHY_INTERFACE_MODE_RMII] = "rmii", 67 [PHY_INTERFACE_MODE_RGMII] = "rgmii", 68 [PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id", 69 [PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid", 70 [PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid", 71 [PHY_INTERFACE_MODE_RTBI] = "rtbi", 72 [PHY_INTERFACE_MODE_XGMII] = "xgmii", 73 [PHY_INTERFACE_MODE_NONE] = "", 74 }; 75 76 static inline const char *phy_string_for_interface(phy_interface_t i) 77 { 78 /* Default to unknown */ 79 if (i > PHY_INTERFACE_MODE_NONE) 80 i = PHY_INTERFACE_MODE_NONE; 81 82 return phy_interface_strings[i]; 83 } 84 85 86 struct phy_device; 87 88 #define MDIO_NAME_LEN 32 89 90 struct mii_dev { 91 struct list_head link; 92 char name[MDIO_NAME_LEN]; 93 void *priv; 94 int (*read)(struct mii_dev *bus, int addr, int devad, int reg); 95 int (*write)(struct mii_dev *bus, int addr, int devad, int reg, 96 u16 val); 97 int (*reset)(struct mii_dev *bus); 98 struct phy_device *phymap[PHY_MAX_ADDR]; 99 u32 phy_mask; 100 }; 101 102 /* struct phy_driver: a structure which defines PHY behavior 103 * 104 * uid will contain a number which represents the PHY. During 105 * startup, the driver will poll the PHY to find out what its 106 * UID--as defined by registers 2 and 3--is. The 32-bit result 107 * gotten from the PHY will be masked to 108 * discard any bits which may change based on revision numbers 109 * unimportant to functionality 110 * 111 */ 112 struct phy_driver { 113 char *name; 114 unsigned int uid; 115 unsigned int mask; 116 unsigned int mmds; 117 118 u32 features; 119 120 /* Called to do any driver startup necessities */ 121 /* Will be called during phy_connect */ 122 int (*probe)(struct phy_device *phydev); 123 124 /* Called to configure the PHY, and modify the controller 125 * based on the results. Should be called after phy_connect */ 126 int (*config)(struct phy_device *phydev); 127 128 /* Called when starting up the controller */ 129 int (*startup)(struct phy_device *phydev); 130 131 /* Called when bringing down the controller */ 132 int (*shutdown)(struct phy_device *phydev); 133 134 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); 135 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, 136 u16 val); 137 struct list_head list; 138 }; 139 140 struct phy_device { 141 /* Information about the PHY type */ 142 /* And management functions */ 143 struct mii_dev *bus; 144 struct phy_driver *drv; 145 void *priv; 146 147 #ifdef CONFIG_DM_ETH 148 struct udevice *dev; 149 #else 150 struct eth_device *dev; 151 #endif 152 153 /* forced speed & duplex (no autoneg) 154 * partner speed & duplex & pause (autoneg) 155 */ 156 int speed; 157 int duplex; 158 159 /* The most recently read link state */ 160 int link; 161 int port; 162 phy_interface_t interface; 163 164 u32 advertising; 165 u32 supported; 166 u32 mmds; 167 168 int autoneg; 169 int addr; 170 int pause; 171 int asym_pause; 172 u32 phy_id; 173 u32 flags; 174 }; 175 176 struct fixed_link { 177 int phy_id; 178 int duplex; 179 int link_speed; 180 int pause; 181 int asym_pause; 182 }; 183 184 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) 185 { 186 struct mii_dev *bus = phydev->bus; 187 188 return bus->read(bus, phydev->addr, devad, regnum); 189 } 190 191 static inline int phy_write(struct phy_device *phydev, int devad, int regnum, 192 u16 val) 193 { 194 struct mii_dev *bus = phydev->bus; 195 196 return bus->write(bus, phydev->addr, devad, regnum, val); 197 } 198 199 #ifdef CONFIG_PHYLIB_10G 200 extern struct phy_driver gen10g_driver; 201 202 /* For now, XGMII is the only 10G interface */ 203 static inline int is_10g_interface(phy_interface_t interface) 204 { 205 return interface == PHY_INTERFACE_MODE_XGMII; 206 } 207 208 #endif 209 210 int phy_init(void); 211 int phy_reset(struct phy_device *phydev); 212 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, 213 phy_interface_t interface); 214 #ifdef CONFIG_DM_ETH 215 void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); 216 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 217 struct udevice *dev, 218 phy_interface_t interface); 219 #else 220 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); 221 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 222 struct eth_device *dev, 223 phy_interface_t interface); 224 #endif 225 int phy_startup(struct phy_device *phydev); 226 int phy_config(struct phy_device *phydev); 227 int phy_shutdown(struct phy_device *phydev); 228 int phy_register(struct phy_driver *drv); 229 int genphy_config_aneg(struct phy_device *phydev); 230 int genphy_restart_aneg(struct phy_device *phydev); 231 int genphy_update_link(struct phy_device *phydev); 232 int genphy_parse_link(struct phy_device *phydev); 233 int genphy_config(struct phy_device *phydev); 234 int genphy_startup(struct phy_device *phydev); 235 int genphy_shutdown(struct phy_device *phydev); 236 int gen10g_config(struct phy_device *phydev); 237 int gen10g_startup(struct phy_device *phydev); 238 int gen10g_shutdown(struct phy_device *phydev); 239 int gen10g_discover_mmds(struct phy_device *phydev); 240 241 int phy_aquantia_init(void); 242 int phy_atheros_init(void); 243 int phy_broadcom_init(void); 244 int phy_cortina_init(void); 245 int phy_davicom_init(void); 246 int phy_et1011c_init(void); 247 int phy_lxt_init(void); 248 int phy_marvell_init(void); 249 int phy_micrel_init(void); 250 int phy_natsemi_init(void); 251 int phy_realtek_init(void); 252 int phy_smsc_init(void); 253 int phy_teranetics_init(void); 254 int phy_ti_init(void); 255 int phy_vitesse_init(void); 256 257 int board_phy_config(struct phy_device *phydev); 258 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); 259 260 /** 261 * phy_get_interface_by_name() - Look up a PHY interface name 262 * 263 * @str: PHY interface name, e.g. "mii" 264 * @return PHY_INTERFACE_MODE_... value, or -1 if not found 265 */ 266 int phy_get_interface_by_name(const char *str); 267 268 /* PHY UIDs for various PHYs that are referenced in external code */ 269 #define PHY_UID_CS4340 0x13e51002 270 #define PHY_UID_TN2020 0x00a19410 271 272 #endif 273