1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2011 Freescale Semiconductor, Inc. 4 * Andy Fleming <afleming@gmail.com> 5 * 6 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h 7 */ 8 9 #ifndef _PHY_H 10 #define _PHY_H 11 12 #include <dm.h> 13 #include <linux/list.h> 14 #include <linux/mii.h> 15 #include <linux/ethtool.h> 16 #include <linux/mdio.h> 17 #include <phy_interface.h> 18 19 #define PHY_FIXED_ID 0xa5a55a5a 20 #define PHY_NCSI_ID 0xbeefcafe 21 22 #define PHY_MAX_ADDR 32 23 24 #define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */ 25 26 #define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \ 27 SUPPORTED_TP | \ 28 SUPPORTED_MII) 29 30 #define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \ 31 SUPPORTED_10baseT_Full) 32 33 #define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \ 34 SUPPORTED_100baseT_Full) 35 36 #define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \ 37 SUPPORTED_1000baseT_Full) 38 39 #define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \ 40 PHY_100BT_FEATURES | \ 41 PHY_DEFAULT_FEATURES) 42 43 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ 44 PHY_1000BT_FEATURES) 45 46 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \ 47 SUPPORTED_10000baseT_Full) 48 49 #ifndef PHY_ANEG_TIMEOUT 50 #define PHY_ANEG_TIMEOUT 4000 51 #endif 52 53 54 struct phy_device; 55 56 #define MDIO_NAME_LEN 32 57 58 struct mii_dev { 59 struct list_head link; 60 char name[MDIO_NAME_LEN]; 61 void *priv; 62 int (*read)(struct mii_dev *bus, int addr, int devad, int reg); 63 int (*write)(struct mii_dev *bus, int addr, int devad, int reg, 64 u16 val); 65 int (*reset)(struct mii_dev *bus); 66 struct phy_device *phymap[PHY_MAX_ADDR]; 67 u32 phy_mask; 68 }; 69 70 /* struct phy_driver: a structure which defines PHY behavior 71 * 72 * uid will contain a number which represents the PHY. During 73 * startup, the driver will poll the PHY to find out what its 74 * UID--as defined by registers 2 and 3--is. The 32-bit result 75 * gotten from the PHY will be masked to 76 * discard any bits which may change based on revision numbers 77 * unimportant to functionality 78 * 79 */ 80 struct phy_driver { 81 char *name; 82 unsigned int uid; 83 unsigned int mask; 84 unsigned int mmds; 85 86 u32 features; 87 88 /* Called to do any driver startup necessities */ 89 /* Will be called during phy_connect */ 90 int (*probe)(struct phy_device *phydev); 91 92 /* Called to configure the PHY, and modify the controller 93 * based on the results. Should be called after phy_connect */ 94 int (*config)(struct phy_device *phydev); 95 96 /* Called when starting up the controller */ 97 int (*startup)(struct phy_device *phydev); 98 99 /* Called when bringing down the controller */ 100 int (*shutdown)(struct phy_device *phydev); 101 102 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg); 103 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg, 104 u16 val); 105 struct list_head list; 106 }; 107 108 struct phy_device { 109 /* Information about the PHY type */ 110 /* And management functions */ 111 struct mii_dev *bus; 112 struct phy_driver *drv; 113 void *priv; 114 115 #ifdef CONFIG_DM_ETH 116 struct udevice *dev; 117 ofnode node; 118 #else 119 struct eth_device *dev; 120 #endif 121 122 /* forced speed & duplex (no autoneg) 123 * partner speed & duplex & pause (autoneg) 124 */ 125 int speed; 126 int duplex; 127 128 /* The most recently read link state */ 129 int link; 130 int port; 131 phy_interface_t interface; 132 133 u32 advertising; 134 u32 supported; 135 u32 mmds; 136 137 int autoneg; 138 int addr; 139 int pause; 140 int asym_pause; 141 u32 phy_id; 142 bool is_c45; 143 u32 flags; 144 }; 145 146 struct fixed_link { 147 int phy_id; 148 int duplex; 149 int link_speed; 150 int pause; 151 int asym_pause; 152 }; 153 154 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) 155 { 156 struct mii_dev *bus = phydev->bus; 157 158 if (!bus || !bus->read) { 159 debug("%s: No bus configured\n", __func__); 160 return -1; 161 } 162 163 return bus->read(bus, phydev->addr, devad, regnum); 164 } 165 166 static inline int phy_write(struct phy_device *phydev, int devad, int regnum, 167 u16 val) 168 { 169 struct mii_dev *bus = phydev->bus; 170 171 if (!bus || !bus->write) { 172 debug("%s: No bus configured\n", __func__); 173 return -1; 174 } 175 176 return bus->write(bus, phydev->addr, devad, regnum, val); 177 } 178 179 #ifdef CONFIG_PHYLIB_10G 180 extern struct phy_driver gen10g_driver; 181 182 /* For now, XGMII is the only 10G interface */ 183 static inline int is_10g_interface(phy_interface_t interface) 184 { 185 return interface == PHY_INTERFACE_MODE_XGMII; 186 } 187 188 #endif 189 190 int phy_init(void); 191 int phy_reset(struct phy_device *phydev); 192 struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask, 193 phy_interface_t interface); 194 #ifdef CONFIG_DM_ETH 195 void phy_connect_dev(struct phy_device *phydev, struct udevice *dev); 196 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 197 struct udevice *dev, 198 phy_interface_t interface); 199 static inline ofnode phy_get_ofnode(struct phy_device *phydev) 200 { 201 if (ofnode_valid(phydev->node)) 202 return phydev->node; 203 else 204 return dev_ofnode(phydev->dev); 205 } 206 #else 207 void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev); 208 struct phy_device *phy_connect(struct mii_dev *bus, int addr, 209 struct eth_device *dev, 210 phy_interface_t interface); 211 static inline ofnode phy_get_ofnode(struct phy_device *phydev) 212 { 213 return ofnode_null(); 214 } 215 #endif 216 int phy_startup(struct phy_device *phydev); 217 int phy_config(struct phy_device *phydev); 218 int phy_shutdown(struct phy_device *phydev); 219 int phy_register(struct phy_driver *drv); 220 int phy_set_supported(struct phy_device *phydev, u32 max_speed); 221 int genphy_config_aneg(struct phy_device *phydev); 222 int genphy_restart_aneg(struct phy_device *phydev); 223 int genphy_update_link(struct phy_device *phydev); 224 int genphy_parse_link(struct phy_device *phydev); 225 int genphy_config(struct phy_device *phydev); 226 int genphy_startup(struct phy_device *phydev); 227 int genphy_shutdown(struct phy_device *phydev); 228 int gen10g_config(struct phy_device *phydev); 229 int gen10g_startup(struct phy_device *phydev); 230 int gen10g_shutdown(struct phy_device *phydev); 231 int gen10g_discover_mmds(struct phy_device *phydev); 232 233 int phy_b53_init(void); 234 int phy_mv88e61xx_init(void); 235 int phy_aquantia_init(void); 236 int phy_atheros_init(void); 237 int phy_broadcom_init(void); 238 int phy_cortina_init(void); 239 int phy_davicom_init(void); 240 int phy_et1011c_init(void); 241 int phy_lxt_init(void); 242 int phy_marvell_init(void); 243 int phy_micrel_ksz8xxx_init(void); 244 int phy_micrel_ksz90x1_init(void); 245 int phy_meson_gxl_init(void); 246 int phy_natsemi_init(void); 247 int phy_realtek_init(void); 248 int phy_smsc_init(void); 249 int phy_teranetics_init(void); 250 int phy_ti_init(void); 251 int phy_vitesse_init(void); 252 int phy_xilinx_init(void); 253 int phy_mscc_init(void); 254 int phy_fixed_init(void); 255 int phy_ncsi_init(void); 256 257 int board_phy_config(struct phy_device *phydev); 258 int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); 259 260 /** 261 * phy_get_interface_by_name() - Look up a PHY interface name 262 * 263 * @str: PHY interface name, e.g. "mii" 264 * @return PHY_INTERFACE_MODE_... value, or -1 if not found 265 */ 266 int phy_get_interface_by_name(const char *str); 267 268 /** 269 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 270 * is RGMII (all variants) 271 * @phydev: the phy_device struct 272 */ 273 static inline bool phy_interface_is_rgmii(struct phy_device *phydev) 274 { 275 return phydev->interface >= PHY_INTERFACE_MODE_RGMII && 276 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; 277 } 278 279 /** 280 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface 281 * is SGMII (all variants) 282 * @phydev: the phy_device struct 283 */ 284 static inline bool phy_interface_is_sgmii(struct phy_device *phydev) 285 { 286 return phydev->interface >= PHY_INTERFACE_MODE_SGMII && 287 phydev->interface <= PHY_INTERFACE_MODE_QSGMII; 288 } 289 290 bool phy_interface_is_ncsi(void); 291 292 /* PHY UIDs for various PHYs that are referenced in external code */ 293 #define PHY_UID_CS4340 0x13e51002 294 #define PHY_UID_CS4223 0x03e57003 295 #define PHY_UID_TN2020 0x00a19410 296 #define PHY_UID_IN112525_S03 0x02107440 297 298 #endif 299