1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _PCMCIA_H 9 #define _PCMCIA_H 10 11 #include <common.h> 12 #include <config.h> 13 14 /* 15 * Allow configuration to select PCMCIA slot, 16 * or try to generate a useful default 17 */ 18 #if defined(CONFIG_CMD_PCMCIA) || \ 19 (defined(CONFIG_CMD_IDE) && \ 20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) 21 22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 23 24 #if defined(CONFIG_FADS) /* The FADS series are a mess */ 25 # if defined(CONFIG_MPC86x) || defined(CONFIG_MPC821) 26 # define CONFIG_PCMCIA_SLOT_A 27 # else 28 # define CONFIG_PCMCIA_SLOT_B 29 # endif 30 #elif defined(CONFIG_TQM8xxL) || defined(CONFIG_SVM_SC8xx) 31 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */ 32 #elif defined(CONFIG_SPD823TS) /* The SPD8xx use SLOT_B */ 33 # define CONFIG_PCMCIA_SLOT_B 34 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */ 35 # define CONFIG_PCMCIA_SLOT_A 36 #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */ 37 # define CONFIG_PCMCIA_SLOT_B 38 #elif defined(CONFIG_ICU862) /* The ICU862 use SLOT_B */ 39 # define CONFIG_PCMCIA_SLOT_B 40 #elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */ 41 # define CONFIG_PCMCIA_SLOT_B 42 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */ 43 # define CONFIG_PCMCIA_SLOT_A 44 #elif defined(CONFIG_NETTA) 45 # define CONFIG_PCMCIA_SLOT_A 46 #elif defined(CONFIG_UC100) /* The UC100 use SLOT_B */ 47 # define CONFIG_PCMCIA_SLOT_B 48 #else 49 # error "PCMCIA Slot not configured" 50 #endif 51 52 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */ 53 54 /* Make sure exactly one slot is defined - we support only one for now */ 55 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) 56 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured 57 #endif 58 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B) 59 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured 60 #endif 61 62 #ifndef PCMCIA_SOCKETS_NO 63 #define PCMCIA_SOCKETS_NO 1 64 #endif 65 #ifndef PCMCIA_MEM_WIN_NO 66 #define PCMCIA_MEM_WIN_NO 4 67 #endif 68 #define PCMCIA_IO_WIN_NO 2 69 70 /* define _slot_ to be able to optimize macros */ 71 #ifdef CONFIG_PCMCIA_SLOT_A 72 # define _slot_ 0 73 # define PCMCIA_SLOT_MSG "slot A" 74 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A 75 #else 76 # define _slot_ 1 77 # define PCMCIA_SLOT_MSG "slot B" 78 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B 79 #endif 80 81 /* 82 * The TQM850L hardware has two pins swapped! Grrrrgh! 83 */ 84 #ifdef CONFIG_TQM850L 85 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE 86 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET 87 #else 88 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET 89 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE 90 #endif 91 92 /* 93 * This structure is used to address each window in the PCMCIA controller. 94 * 95 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly 96 * after pcmcia_win_t[n]... 97 */ 98 99 typedef struct { 100 ulong br; 101 ulong or; 102 } pcmcia_win_t; 103 104 /* 105 * Definitions for PCMCIA control registers to operate in IDE mode 106 * 107 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL) 108 * to be done later (depending on CPU clock) 109 */ 110 111 /* Window 0: 112 * Base: 0xFE100000 CS1 113 * Port Size: 2 Bytes 114 * Port Size: 16 Bit 115 * Common Memory Space 116 */ 117 118 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000 119 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \ 120 | PCMCIA_PPS_16 \ 121 | PCMCIA_PRS_MEM \ 122 | PCMCIA_SLOT_x \ 123 | PCMCIA_PV \ 124 ) 125 126 /* Window 1: 127 * Base: 0xFE100080 CS1 128 * Port Size: 8 Bytes 129 * Port Size: 8 Bit 130 * Common Memory Space 131 */ 132 133 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080 134 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \ 135 | PCMCIA_PPS_8 \ 136 | PCMCIA_PRS_MEM \ 137 | PCMCIA_SLOT_x \ 138 | PCMCIA_PV \ 139 ) 140 141 /* Window 2: 142 * Base: 0xFE100100 CS2 143 * Port Size: 8 Bytes 144 * Port Size: 8 Bit 145 * Common Memory Space 146 */ 147 148 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100 149 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \ 150 | PCMCIA_PPS_8 \ 151 | PCMCIA_PRS_MEM \ 152 | PCMCIA_SLOT_x \ 153 | PCMCIA_PV \ 154 ) 155 156 /* Window 3: 157 * not used 158 */ 159 #define CONFIG_SYS_PCMCIA_PBR3 0 160 #define CONFIG_SYS_PCMCIA_POR3 0 161 162 /* Window 4: 163 * Base: 0xFE100C00 CS1 164 * Port Size: 2 Bytes 165 * Port Size: 16 Bit 166 * Common Memory Space 167 */ 168 169 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00 170 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \ 171 | PCMCIA_PPS_16 \ 172 | PCMCIA_PRS_MEM \ 173 | PCMCIA_SLOT_x \ 174 | PCMCIA_PV \ 175 ) 176 177 /* Window 5: 178 * Base: 0xFE100C80 CS1 179 * Port Size: 8 Bytes 180 * Port Size: 8 Bit 181 * Common Memory Space 182 */ 183 184 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80 185 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \ 186 | PCMCIA_PPS_8 \ 187 | PCMCIA_PRS_MEM \ 188 | PCMCIA_SLOT_x \ 189 | PCMCIA_PV \ 190 ) 191 192 /* Window 6: 193 * Base: 0xFE100D00 CS2 194 * Port Size: 8 Bytes 195 * Port Size: 8 Bit 196 * Common Memory Space 197 */ 198 199 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00 200 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \ 201 | PCMCIA_PPS_8 \ 202 | PCMCIA_PRS_MEM \ 203 | PCMCIA_SLOT_x \ 204 | PCMCIA_PV \ 205 ) 206 207 /* Window 7: 208 * not used 209 */ 210 #define CONFIG_SYS_PCMCIA_PBR7 0 211 #define CONFIG_SYS_PCMCIA_POR7 0 212 213 /**********************************************************************/ 214 215 /* 216 * CIS Tupel codes 217 */ 218 #define CISTPL_NULL 0x00 219 #define CISTPL_DEVICE 0x01 220 #define CISTPL_LONGLINK_CB 0x02 221 #define CISTPL_INDIRECT 0x03 222 #define CISTPL_CONFIG_CB 0x04 223 #define CISTPL_CFTABLE_ENTRY_CB 0x05 224 #define CISTPL_LONGLINK_MFC 0x06 225 #define CISTPL_BAR 0x07 226 #define CISTPL_PWR_MGMNT 0x08 227 #define CISTPL_EXTDEVICE 0x09 228 #define CISTPL_CHECKSUM 0x10 229 #define CISTPL_LONGLINK_A 0x11 230 #define CISTPL_LONGLINK_C 0x12 231 #define CISTPL_LINKTARGET 0x13 232 #define CISTPL_NO_LINK 0x14 233 #define CISTPL_VERS_1 0x15 234 #define CISTPL_ALTSTR 0x16 235 #define CISTPL_DEVICE_A 0x17 236 #define CISTPL_JEDEC_C 0x18 237 #define CISTPL_JEDEC_A 0x19 238 #define CISTPL_CONFIG 0x1a 239 #define CISTPL_CFTABLE_ENTRY 0x1b 240 #define CISTPL_DEVICE_OC 0x1c 241 #define CISTPL_DEVICE_OA 0x1d 242 #define CISTPL_DEVICE_GEO 0x1e 243 #define CISTPL_DEVICE_GEO_A 0x1f 244 #define CISTPL_MANFID 0x20 245 #define CISTPL_FUNCID 0x21 246 #define CISTPL_FUNCE 0x22 247 #define CISTPL_SWIL 0x23 248 #define CISTPL_END 0xff 249 250 /* 251 * CIS Function ID codes 252 */ 253 #define CISTPL_FUNCID_MULTI 0x00 254 #define CISTPL_FUNCID_MEMORY 0x01 255 #define CISTPL_FUNCID_SERIAL 0x02 256 #define CISTPL_FUNCID_PARALLEL 0x03 257 #define CISTPL_FUNCID_FIXED 0x04 258 #define CISTPL_FUNCID_VIDEO 0x05 259 #define CISTPL_FUNCID_NETWORK 0x06 260 #define CISTPL_FUNCID_AIMS 0x07 261 #define CISTPL_FUNCID_SCSI 0x08 262 263 /* 264 * Fixed Disk FUNCE codes 265 */ 266 #define CISTPL_IDE_INTERFACE 0x01 267 268 #define CISTPL_FUNCE_IDE_IFACE 0x01 269 #define CISTPL_FUNCE_IDE_MASTER 0x02 270 #define CISTPL_FUNCE_IDE_SLAVE 0x03 271 272 /* First feature byte */ 273 #define CISTPL_IDE_SILICON 0x04 274 #define CISTPL_IDE_UNIQUE 0x08 275 #define CISTPL_IDE_DUAL 0x10 276 277 /* Second feature byte */ 278 #define CISTPL_IDE_HAS_SLEEP 0x01 279 #define CISTPL_IDE_HAS_STANDBY 0x02 280 #define CISTPL_IDE_HAS_IDLE 0x04 281 #define CISTPL_IDE_LOW_POWER 0x08 282 #define CISTPL_IDE_REG_INHIBIT 0x10 283 #define CISTPL_IDE_HAS_INDEX 0x20 284 #define CISTPL_IDE_IOIS16 0x40 285 286 #endif 287 288 #ifdef CONFIG_8xx 289 extern u_int *pcmcia_pgcrx[]; 290 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) 291 #endif 292 293 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) 294 extern int check_ide_device(int slot); 295 #endif 296 297 #endif /* _PCMCIA_H */ 298