1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Andreas Heppel <aheppel@sysgo.de> 5 * 6 * (C) Copyright 2002 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 */ 9 10 #ifndef _PCI_H 11 #define _PCI_H 12 13 #define PCI_CFG_SPACE_SIZE 256 14 #define PCI_CFG_SPACE_EXP_SIZE 4096 15 16 /* 17 * Under PCI, each device has 256 bytes of configuration address space, 18 * of which the first 64 bytes are standardized as follows: 19 */ 20 #define PCI_STD_HEADER_SIZEOF 64 21 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 22 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 23 #define PCI_COMMAND 0x04 /* 16 bits */ 24 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 25 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 26 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 27 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 28 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 29 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 30 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 31 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 32 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 33 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 34 35 #define PCI_STATUS 0x06 /* 16 bits */ 36 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 37 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 38 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 39 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 40 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 41 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 42 #define PCI_STATUS_DEVSEL_FAST 0x000 43 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 44 #define PCI_STATUS_DEVSEL_SLOW 0x400 45 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 46 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 47 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 48 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 49 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 50 51 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 52 revision */ 53 #define PCI_REVISION_ID 0x08 /* Revision ID */ 54 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 55 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 56 #define PCI_CLASS_CODE 0x0b /* Device class code */ 57 #define PCI_CLASS_CODE_TOO_OLD 0x00 58 #define PCI_CLASS_CODE_STORAGE 0x01 59 #define PCI_CLASS_CODE_NETWORK 0x02 60 #define PCI_CLASS_CODE_DISPLAY 0x03 61 #define PCI_CLASS_CODE_MULTIMEDIA 0x04 62 #define PCI_CLASS_CODE_MEMORY 0x05 63 #define PCI_CLASS_CODE_BRIDGE 0x06 64 #define PCI_CLASS_CODE_COMM 0x07 65 #define PCI_CLASS_CODE_PERIPHERAL 0x08 66 #define PCI_CLASS_CODE_INPUT 0x09 67 #define PCI_CLASS_CODE_DOCKING 0x0A 68 #define PCI_CLASS_CODE_PROCESSOR 0x0B 69 #define PCI_CLASS_CODE_SERIAL 0x0C 70 #define PCI_CLASS_CODE_WIRELESS 0x0D 71 #define PCI_CLASS_CODE_I2O 0x0E 72 #define PCI_CLASS_CODE_SATELLITE 0x0F 73 #define PCI_CLASS_CODE_CRYPTO 0x10 74 #define PCI_CLASS_CODE_DATA 0x11 75 /* Base Class 0x12 - 0xFE is reserved */ 76 #define PCI_CLASS_CODE_OTHER 0xFF 77 78 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 79 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 80 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 81 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 82 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 83 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 84 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 85 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 86 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 87 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 88 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 89 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 90 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 91 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 92 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 93 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 94 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 95 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 96 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 97 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 98 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 99 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 100 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 101 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 105 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 106 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 107 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 108 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 109 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 110 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 111 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 112 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 113 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 114 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 115 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 116 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 117 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 118 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 119 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A 120 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 121 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 122 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 123 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 124 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 125 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 126 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 127 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 134 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 135 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 136 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 137 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 138 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 139 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 140 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 141 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 142 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 143 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 144 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 145 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 146 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 147 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 148 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 149 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 150 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 151 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 152 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 153 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 154 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 155 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 156 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 157 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 158 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 159 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 160 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 161 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 162 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 163 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 164 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 165 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 166 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 167 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 168 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 169 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 170 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 171 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 172 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 173 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 174 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 175 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 176 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 177 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 178 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 179 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 180 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 181 182 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 183 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 184 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 185 #define PCI_HEADER_TYPE_NORMAL 0 186 #define PCI_HEADER_TYPE_BRIDGE 1 187 #define PCI_HEADER_TYPE_CARDBUS 2 188 189 #define PCI_BIST 0x0f /* 8 bits */ 190 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 191 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 192 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 193 194 /* 195 * Base addresses specify locations in memory or I/O space. 196 * Decoded size can be determined by writing a value of 197 * 0xffffffff to the register, and reading it back. Only 198 * 1 bits are decoded. 199 */ 200 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 201 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 202 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 203 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 204 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 205 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 206 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 207 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 208 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 209 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 210 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 211 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 212 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 213 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 214 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 215 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 216 /* bit 1 is reserved if address_space = 1 */ 217 218 /* Header type 0 (normal devices) */ 219 #define PCI_CARDBUS_CIS 0x28 220 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 221 #define PCI_SUBSYSTEM_ID 0x2e 222 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 223 #define PCI_ROM_ADDRESS_ENABLE 0x01 224 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 225 226 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 227 228 /* 0x35-0x3b are reserved */ 229 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 230 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 231 #define PCI_MIN_GNT 0x3e /* 8 bits */ 232 #define PCI_MAX_LAT 0x3f /* 8 bits */ 233 234 #define PCI_INTERRUPT_LINE_DISABLE 0xff 235 236 /* Header type 1 (PCI-to-PCI bridges) */ 237 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 238 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 239 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 240 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 241 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 242 #define PCI_IO_LIMIT 0x1d 243 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 244 #define PCI_IO_RANGE_TYPE_16 0x00 245 #define PCI_IO_RANGE_TYPE_32 0x01 246 #define PCI_IO_RANGE_MASK ~0x0f 247 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 248 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 249 #define PCI_MEMORY_LIMIT 0x22 250 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 251 #define PCI_MEMORY_RANGE_MASK ~0x0f 252 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 253 #define PCI_PREF_MEMORY_LIMIT 0x26 254 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 255 #define PCI_PREF_RANGE_TYPE_32 0x00 256 #define PCI_PREF_RANGE_TYPE_64 0x01 257 #define PCI_PREF_RANGE_MASK ~0x0f 258 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 259 #define PCI_PREF_LIMIT_UPPER32 0x2c 260 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 261 #define PCI_IO_LIMIT_UPPER16 0x32 262 /* 0x34 same as for htype 0 */ 263 /* 0x35-0x3b is reserved */ 264 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 265 /* 0x3c-0x3d are same as for htype 0 */ 266 #define PCI_BRIDGE_CONTROL 0x3e 267 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 268 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 269 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 270 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 271 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 272 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 273 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 274 275 /* Header type 2 (CardBus bridges) */ 276 #define PCI_CB_CAPABILITY_LIST 0x14 277 /* 0x15 reserved */ 278 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 279 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 280 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 281 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 282 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 283 #define PCI_CB_MEMORY_BASE_0 0x1c 284 #define PCI_CB_MEMORY_LIMIT_0 0x20 285 #define PCI_CB_MEMORY_BASE_1 0x24 286 #define PCI_CB_MEMORY_LIMIT_1 0x28 287 #define PCI_CB_IO_BASE_0 0x2c 288 #define PCI_CB_IO_BASE_0_HI 0x2e 289 #define PCI_CB_IO_LIMIT_0 0x30 290 #define PCI_CB_IO_LIMIT_0_HI 0x32 291 #define PCI_CB_IO_BASE_1 0x34 292 #define PCI_CB_IO_BASE_1_HI 0x36 293 #define PCI_CB_IO_LIMIT_1 0x38 294 #define PCI_CB_IO_LIMIT_1_HI 0x3a 295 #define PCI_CB_IO_RANGE_MASK ~0x03 296 /* 0x3c-0x3d are same as for htype 0 */ 297 #define PCI_CB_BRIDGE_CONTROL 0x3e 298 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 299 #define PCI_CB_BRIDGE_CTL_SERR 0x02 300 #define PCI_CB_BRIDGE_CTL_ISA 0x04 301 #define PCI_CB_BRIDGE_CTL_VGA 0x08 302 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 303 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 304 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 305 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 306 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 307 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 308 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 309 #define PCI_CB_SUBSYSTEM_ID 0x42 310 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 311 /* 0x48-0x7f reserved */ 312 313 /* Capability lists */ 314 315 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 316 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 317 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 318 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 319 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 320 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 321 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 322 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 323 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 324 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ 325 #define PCI_CAP_ID_DBG 0x0A /* Debug port */ 326 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ 327 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 328 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ 329 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ 330 #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ 331 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 332 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 333 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ 334 #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ 335 #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */ 336 #define PCI_CAP_ID_MAX PCI_CAP_ID_EA 337 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 338 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 339 #define PCI_CAP_SIZEOF 4 340 341 /* Power Management Registers */ 342 343 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 344 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 345 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 346 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 347 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 348 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 349 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 350 #define PCI_PM_CTRL 4 /* PM control and status register */ 351 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 352 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 353 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 354 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 355 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 356 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 357 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 358 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 359 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 360 #define PCI_PM_SIZEOF 8 361 362 /* AGP registers */ 363 364 #define PCI_AGP_VERSION 2 /* BCD version number */ 365 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 366 #define PCI_AGP_STATUS 4 /* Status register */ 367 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 368 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 369 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 370 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 371 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 372 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 373 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 374 #define PCI_AGP_COMMAND 8 /* Control register */ 375 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 376 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 377 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 378 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 379 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 380 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 381 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 382 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 383 #define PCI_AGP_SIZEOF 12 384 385 /* PCI-X registers */ 386 387 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 388 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 389 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 390 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 391 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 392 393 394 /* Slot Identification */ 395 396 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 397 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 398 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 399 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 400 401 /* Message Signalled Interrupts registers */ 402 403 #define PCI_MSI_FLAGS 2 /* Various flags */ 404 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 405 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 406 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 407 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 408 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 409 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 410 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 411 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 412 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 413 414 #define PCI_MAX_PCI_DEVICES 32 415 #define PCI_MAX_PCI_FUNCTIONS 8 416 417 #define PCI_FIND_CAP_TTL 0x48 418 #define CAP_START_POS 0x40 419 420 /* Extended Capabilities (PCI-X 2.0 and Express) */ 421 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 422 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 423 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 424 425 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 426 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 427 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 428 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 429 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 430 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 431 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 432 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 433 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 434 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 435 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 436 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 437 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 438 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 439 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 440 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 441 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 442 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 443 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 444 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 445 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 446 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 447 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 448 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 449 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 450 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 451 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 452 #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ 453 #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ 454 #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ 455 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM 456 457 /* Include the ID list */ 458 459 #include <pci_ids.h> 460 461 #ifndef __ASSEMBLY__ 462 463 #ifdef CONFIG_SYS_PCI_64BIT 464 typedef u64 pci_addr_t; 465 typedef u64 pci_size_t; 466 #else 467 typedef u32 pci_addr_t; 468 typedef u32 pci_size_t; 469 #endif 470 471 struct pci_region { 472 pci_addr_t bus_start; /* Start on the bus */ 473 phys_addr_t phys_start; /* Start in physical address space */ 474 pci_size_t size; /* Size */ 475 unsigned long flags; /* Resource flags */ 476 477 pci_addr_t bus_lower; 478 }; 479 480 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 481 #define PCI_REGION_IO 0x00000001 /* PCI IO space */ 482 #define PCI_REGION_TYPE 0x00000001 483 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 484 485 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 486 #define PCI_REGION_RO 0x00000200 /* Read-only memory */ 487 488 static inline void pci_set_region(struct pci_region *reg, 489 pci_addr_t bus_start, 490 phys_addr_t phys_start, 491 pci_size_t size, 492 unsigned long flags) { 493 reg->bus_start = bus_start; 494 reg->phys_start = phys_start; 495 reg->size = size; 496 reg->flags = flags; 497 } 498 499 typedef int pci_dev_t; 500 501 #define PCI_BUS(d) (((d) >> 16) & 0xff) 502 #define PCI_DEV(d) (((d) >> 11) & 0x1f) 503 #define PCI_FUNC(d) (((d) >> 8) & 0x7) 504 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) 505 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) 506 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) 507 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) 508 #define PCI_VENDEV(v, d) (((v) << 16) | (d)) 509 #define PCI_ANY_ID (~0) 510 511 struct pci_device_id { 512 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 513 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ 514 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ 515 unsigned long driver_data; /* Data private to the driver */ 516 }; 517 518 struct pci_controller; 519 520 struct pci_config_table { 521 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 522 unsigned int class; /* Class ID, or PCI_ANY_ID */ 523 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 524 unsigned int dev; /* Device number, or PCI_ANY_ID */ 525 unsigned int func; /* Function number, or PCI_ANY_ID */ 526 527 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 528 struct pci_config_table *); 529 unsigned long priv[3]; 530 }; 531 532 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 533 struct pci_config_table *); 534 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 535 struct pci_config_table *); 536 537 #define MAX_PCI_REGIONS 7 538 539 #define INDIRECT_TYPE_NO_PCIE_LINK 1 540 541 /* 542 * Structure of a PCI controller (host bridge) 543 * 544 * With driver model this is dev_get_uclass_priv(bus) 545 */ 546 struct pci_controller { 547 #ifdef CONFIG_DM_PCI 548 struct udevice *bus; 549 struct udevice *ctlr; 550 #else 551 struct pci_controller *next; 552 #endif 553 554 int first_busno; 555 int last_busno; 556 557 volatile unsigned int *cfg_addr; 558 volatile unsigned char *cfg_data; 559 560 int indirect_type; 561 562 /* 563 * TODO(sjg@chromium.org): With driver model we use struct 564 * pci_controller for both the controller and any bridge devices 565 * attached to it. But there is only one region list and it is in the 566 * top-level controller. 567 * 568 * This could be changed so that struct pci_controller is only used 569 * for PCI controllers and a separate UCLASS (or perhaps 570 * UCLASS_PCI_GENERIC) is used for bridges. 571 */ 572 struct pci_region regions[MAX_PCI_REGIONS]; 573 int region_count; 574 575 struct pci_config_table *config_table; 576 577 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 578 #ifndef CONFIG_DM_PCI 579 /* Low-level architecture-dependent routines */ 580 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); 581 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); 582 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); 583 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); 584 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); 585 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); 586 #endif 587 588 /* Used by auto config */ 589 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 590 591 #ifndef CONFIG_DM_PCI 592 int current_busno; 593 594 void *priv_data; 595 #endif 596 }; 597 598 #ifndef CONFIG_DM_PCI 599 static inline void pci_set_ops(struct pci_controller *hose, 600 int (*read_byte)(struct pci_controller*, 601 pci_dev_t, int where, u8 *), 602 int (*read_word)(struct pci_controller*, 603 pci_dev_t, int where, u16 *), 604 int (*read_dword)(struct pci_controller*, 605 pci_dev_t, int where, u32 *), 606 int (*write_byte)(struct pci_controller*, 607 pci_dev_t, int where, u8), 608 int (*write_word)(struct pci_controller*, 609 pci_dev_t, int where, u16), 610 int (*write_dword)(struct pci_controller*, 611 pci_dev_t, int where, u32)) { 612 hose->read_byte = read_byte; 613 hose->read_word = read_word; 614 hose->read_dword = read_dword; 615 hose->write_byte = write_byte; 616 hose->write_word = write_word; 617 hose->write_dword = write_dword; 618 } 619 #endif 620 621 #ifdef CONFIG_PCI_INDIRECT_BRIDGE 622 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); 623 #endif 624 625 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 626 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 627 pci_addr_t addr, unsigned long flags); 628 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 629 phys_addr_t addr, unsigned long flags); 630 631 #define pci_phys_to_bus(dev, addr, flags) \ 632 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 633 #define pci_bus_to_phys(dev, addr, flags) \ 634 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 635 636 #define pci_virt_to_bus(dev, addr, flags) \ 637 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 638 (virt_to_phys(addr)), (flags)) 639 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 640 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 641 (addr), (flags)), \ 642 (len), (map_flags)) 643 644 #define pci_phys_to_mem(dev, addr) \ 645 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 646 #define pci_mem_to_phys(dev, addr) \ 647 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 648 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 649 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 650 651 #define pci_virt_to_mem(dev, addr) \ 652 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 653 #define pci_mem_to_virt(dev, addr, len, map_flags) \ 654 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 655 #define pci_virt_to_io(dev, addr) \ 656 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 657 #define pci_io_to_virt(dev, addr, len, map_flags) \ 658 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 659 660 /* For driver model these are defined in macros in pci_compat.c */ 661 extern int pci_hose_read_config_byte(struct pci_controller *hose, 662 pci_dev_t dev, int where, u8 *val); 663 extern int pci_hose_read_config_word(struct pci_controller *hose, 664 pci_dev_t dev, int where, u16 *val); 665 extern int pci_hose_read_config_dword(struct pci_controller *hose, 666 pci_dev_t dev, int where, u32 *val); 667 extern int pci_hose_write_config_byte(struct pci_controller *hose, 668 pci_dev_t dev, int where, u8 val); 669 extern int pci_hose_write_config_word(struct pci_controller *hose, 670 pci_dev_t dev, int where, u16 val); 671 extern int pci_hose_write_config_dword(struct pci_controller *hose, 672 pci_dev_t dev, int where, u32 val); 673 #endif 674 675 #ifndef CONFIG_DM_PCI 676 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); 677 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); 678 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); 679 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); 680 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); 681 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); 682 #endif 683 684 void pciauto_region_init(struct pci_region *res); 685 void pciauto_region_align(struct pci_region *res, pci_size_t size); 686 void pciauto_config_init(struct pci_controller *hose); 687 688 /** 689 * pciauto_region_allocate() - Allocate resources from a PCI resource region 690 * 691 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is 692 * false, the result will be guaranteed to fit in 32 bits. 693 * 694 * @res: PCI region to allocate from 695 * @size: Amount of bytes to allocate 696 * @bar: Returns the PCI bus address of the allocated resource 697 * @supports_64bit: Whether to allow allocations above the 32-bit boundary 698 * @return 0 if successful, -1 on failure 699 */ 700 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 701 pci_addr_t *bar, bool supports_64bit); 702 703 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 704 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 705 pci_dev_t dev, int where, u8 *val); 706 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 707 pci_dev_t dev, int where, u16 *val); 708 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 709 pci_dev_t dev, int where, u8 val); 710 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 711 pci_dev_t dev, int where, u16 val); 712 713 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 714 extern void pci_register_hose(struct pci_controller* hose); 715 extern struct pci_controller* pci_bus_to_hose(int bus); 716 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 717 extern struct pci_controller *pci_get_hose_head(void); 718 719 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); 720 extern int pci_hose_scan(struct pci_controller *hose); 721 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 722 723 extern void pciauto_setup_device(struct pci_controller *hose, 724 pci_dev_t dev, int bars_num, 725 struct pci_region *mem, 726 struct pci_region *prefetch, 727 struct pci_region *io); 728 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 729 pci_dev_t dev, int sub_bus); 730 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 731 pci_dev_t dev, int sub_bus); 732 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 733 734 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 735 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 736 pci_dev_t pci_find_class(unsigned int find_class, int index); 737 738 extern int pci_hose_config_device(struct pci_controller *hose, 739 pci_dev_t dev, 740 unsigned long io, 741 pci_addr_t mem, 742 unsigned long command); 743 744 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 745 int cap); 746 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 747 u8 hdr_type); 748 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 749 int cap); 750 751 int pci_find_next_ext_capability(struct pci_controller *hose, 752 pci_dev_t dev, int start, int cap); 753 int pci_hose_find_ext_capability(struct pci_controller *hose, 754 pci_dev_t dev, int cap); 755 756 #ifdef CONFIG_PCI_FIXUP_DEV 757 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 758 unsigned short vendor, 759 unsigned short device, 760 unsigned short class); 761 #endif 762 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ 763 764 const char * pci_class_str(u8 class); 765 int pci_last_busno(void); 766 767 #ifdef CONFIG_MPC85xx 768 extern void pci_mpc85xx_init (struct pci_controller *hose); 769 #endif 770 771 #ifdef CONFIG_PCIE_IMX 772 extern void imx_pcie_remove(void); 773 #endif 774 775 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 776 /** 777 * pci_write_bar32() - Write the address of a BAR including control bits 778 * 779 * This writes a raw address (with control bits) to a bar. This can be used 780 * with devices which require hard-coded addresses, not part of the normal 781 * PCI enumeration process. 782 * 783 * @hose: PCI hose to use 784 * @dev: PCI device to update 785 * @barnum: BAR number (0-5) 786 * @addr: BAR address with control bits 787 */ 788 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, 789 u32 addr); 790 791 /** 792 * pci_read_bar32() - read the address of a bar 793 * 794 * @hose: PCI hose to use 795 * @dev: PCI device to inspect 796 * @barnum: BAR number (0-5) 797 * @return address of the bar, masking out any control bits 798 * */ 799 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); 800 801 /** 802 * pci_hose_find_devices() - Find devices by vendor/device ID 803 * 804 * @hose: PCI hose to search 805 * @busnum: Bus number to search 806 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 807 * @indexp: Pointer to device index to find. To find the first matching 808 * device, pass 0; to find the second, pass 1, etc. This 809 * parameter is decremented for each non-matching device so 810 * can be called repeatedly. 811 */ 812 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, 813 struct pci_device_id *ids, int *indexp); 814 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ 815 816 /* Access sizes for PCI reads and writes */ 817 enum pci_size_t { 818 PCI_SIZE_8, 819 PCI_SIZE_16, 820 PCI_SIZE_32, 821 }; 822 823 struct udevice; 824 825 #ifdef CONFIG_DM_PCI 826 /** 827 * struct pci_child_platdata - information stored about each PCI device 828 * 829 * Every device on a PCI bus has this per-child data. 830 * 831 * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a 832 * PCI bus (i.e. UCLASS_PCI) 833 * 834 * @devfn: Encoded device and function index - see PCI_DEVFN() 835 * @vendor: PCI vendor ID (see pci_ids.h) 836 * @device: PCI device ID (see pci_ids.h) 837 * @class: PCI class, 3 bytes: (base, sub, prog-if) 838 */ 839 struct pci_child_platdata { 840 int devfn; 841 unsigned short vendor; 842 unsigned short device; 843 unsigned int class; 844 }; 845 846 /* PCI bus operations */ 847 struct dm_pci_ops { 848 /** 849 * read_config() - Read a PCI configuration value 850 * 851 * PCI buses must support reading and writing configuration values 852 * so that the bus can be scanned and its devices configured. 853 * 854 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. 855 * If bridges exist it is possible to use the top-level bus to 856 * access a sub-bus. In that case @bus will be the top-level bus 857 * and PCI_BUS(bdf) will be a different (higher) value 858 * 859 * @bus: Bus to read from 860 * @bdf: Bus, device and function to read 861 * @offset: Byte offset within the device's configuration space 862 * @valuep: Place to put the returned value 863 * @size: Access size 864 * @return 0 if OK, -ve on error 865 */ 866 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 867 ulong *valuep, enum pci_size_t size); 868 /** 869 * write_config() - Write a PCI configuration value 870 * 871 * @bus: Bus to write to 872 * @bdf: Bus, device and function to write 873 * @offset: Byte offset within the device's configuration space 874 * @value: Value to write 875 * @size: Access size 876 * @return 0 if OK, -ve on error 877 */ 878 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 879 ulong value, enum pci_size_t size); 880 }; 881 882 /* Get access to a PCI bus' operations */ 883 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) 884 885 /** 886 * dm_pci_get_bdf() - Get the BDF value for a device 887 * 888 * @dev: Device to check 889 * @return bus/device/function value (see PCI_BDF()) 890 */ 891 pci_dev_t dm_pci_get_bdf(struct udevice *dev); 892 893 /** 894 * pci_bind_bus_devices() - scan a PCI bus and bind devices 895 * 896 * Scan a PCI bus looking for devices. Bind each one that is found. If 897 * devices are already bound that match the scanned devices, just update the 898 * child data so that the device can be used correctly (this happens when 899 * the device tree describes devices we expect to see on the bus). 900 * 901 * Devices that are bound in this way will use a generic PCI driver which 902 * does nothing. The device can still be accessed but will not provide any 903 * driver interface. 904 * 905 * @bus: Bus containing devices to bind 906 * @return 0 if OK, -ve on error 907 */ 908 int pci_bind_bus_devices(struct udevice *bus); 909 910 /** 911 * pci_auto_config_devices() - configure bus devices ready for use 912 * 913 * This works through all devices on a bus by scanning the driver model 914 * data structures (normally these have been set up by pci_bind_bus_devices() 915 * earlier). 916 * 917 * Space is allocated for each PCI base address register (BAR) so that the 918 * devices are mapped into memory and I/O space ready for use. 919 * 920 * @bus: Bus containing devices to bind 921 * @return 0 if OK, -ve on error 922 */ 923 int pci_auto_config_devices(struct udevice *bus); 924 925 /** 926 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address 927 * 928 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 929 * @devp: Returns the device for this address, if found 930 * @return 0 if OK, -ENODEV if not found 931 */ 932 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); 933 934 /** 935 * pci_bus_find_devfn() - Find a device on a bus 936 * 937 * @find_devfn: PCI device address (device and function only) 938 * @devp: Returns the device for this address, if found 939 * @return 0 if OK, -ENODEV if not found 940 */ 941 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 942 struct udevice **devp); 943 944 /** 945 * pci_find_first_device() - return the first available PCI device 946 * 947 * This function and pci_find_first_device() allow iteration through all 948 * available PCI devices on all buses. Assuming there are any, this will 949 * return the first one. 950 * 951 * @devp: Set to the first available device, or NULL if no more are left 952 * or we got an error 953 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 954 */ 955 int pci_find_first_device(struct udevice **devp); 956 957 /** 958 * pci_find_next_device() - return the next available PCI device 959 * 960 * Finds the next available PCI device after the one supplied, or sets @devp 961 * to NULL if there are no more. 962 * 963 * @devp: On entry, the last device returned. Set to the next available 964 * device, or NULL if no more are left or we got an error 965 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 966 */ 967 int pci_find_next_device(struct udevice **devp); 968 969 /** 970 * pci_get_ff() - Returns a mask for the given access size 971 * 972 * @size: Access size 973 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for 974 * PCI_SIZE_32 975 */ 976 int pci_get_ff(enum pci_size_t size); 977 978 /** 979 * pci_bus_find_devices () - Find devices on a bus 980 * 981 * @bus: Bus to search 982 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 983 * @indexp: Pointer to device index to find. To find the first matching 984 * device, pass 0; to find the second, pass 1, etc. This 985 * parameter is decremented for each non-matching device so 986 * can be called repeatedly. 987 * @devp: Returns matching device if found 988 * @return 0 if found, -ENODEV if not 989 */ 990 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 991 int *indexp, struct udevice **devp); 992 993 /** 994 * pci_find_device_id() - Find a device on any bus 995 * 996 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 997 * @index: Index number of device to find, 0 for the first match, 1 for 998 * the second, etc. 999 * @devp: Returns matching device if found 1000 * @return 0 if found, -ENODEV if not 1001 */ 1002 int pci_find_device_id(struct pci_device_id *ids, int index, 1003 struct udevice **devp); 1004 1005 /** 1006 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices 1007 * 1008 * This probes the given bus which causes it to be scanned for devices. The 1009 * devices will be bound but not probed. 1010 * 1011 * @hose specifies the PCI hose that will be used for the scan. This is 1012 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is 1013 * in @bdf, and is a subordinate bus reachable from @hose. 1014 * 1015 * @hose: PCI hose to scan 1016 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) 1017 * @return 0 if OK, -ve on error 1018 */ 1019 int dm_pci_hose_probe_bus(struct udevice *bus); 1020 1021 /** 1022 * pci_bus_read_config() - Read a configuration value from a device 1023 * 1024 * TODO(sjg@chromium.org): We should be able to pass just a device and have 1025 * it do the right thing. It would be good to have that function also. 1026 * 1027 * @bus: Bus to read from 1028 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1029 * @offset: Register offset to read 1030 * @valuep: Place to put the returned value 1031 * @size: Access size 1032 * @return 0 if OK, -ve on error 1033 */ 1034 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 1035 unsigned long *valuep, enum pci_size_t size); 1036 1037 /** 1038 * pci_bus_write_config() - Write a configuration value to a device 1039 * 1040 * @bus: Bus to write from 1041 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1042 * @offset: Register offset to write 1043 * @value: Value to write 1044 * @size: Access size 1045 * @return 0 if OK, -ve on error 1046 */ 1047 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 1048 unsigned long value, enum pci_size_t size); 1049 1050 /** 1051 * pci_bus_clrset_config32() - Update a configuration value for a device 1052 * 1053 * The register at @offset is updated to (oldvalue & ~clr) | set. 1054 * 1055 * @bus: Bus to access 1056 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1057 * @offset: Register offset to update 1058 * @clr: Bits to clear 1059 * @set: Bits to set 1060 * @return 0 if OK, -ve on error 1061 */ 1062 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, 1063 u32 clr, u32 set); 1064 1065 /** 1066 * Driver model PCI config access functions. Use these in preference to others 1067 * when you have a valid device 1068 */ 1069 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, 1070 enum pci_size_t size); 1071 1072 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep); 1073 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep); 1074 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep); 1075 1076 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, 1077 enum pci_size_t size); 1078 1079 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value); 1080 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value); 1081 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); 1082 1083 /** 1084 * These permit convenient read/modify/write on PCI configuration. The 1085 * register is updated to (oldvalue & ~clr) | set. 1086 */ 1087 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set); 1088 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set); 1089 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set); 1090 1091 /* 1092 * The following functions provide access to the above without needing the 1093 * size parameter. We are trying to encourage the use of the 8/16/32-style 1094 * functions, rather than byte/word/dword. But both are supported. 1095 */ 1096 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); 1097 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); 1098 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); 1099 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); 1100 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); 1101 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); 1102 1103 /** 1104 * pci_generic_mmap_write_config() - Generic helper for writing to 1105 * memory-mapped PCI configuration space. 1106 * @bus: Pointer to the PCI bus 1107 * @addr_f: Callback for calculating the config space address 1108 * @bdf: Identifies the PCI device to access 1109 * @offset: The offset into the device's configuration space 1110 * @value: The value to write 1111 * @size: Indicates the size of access to perform 1112 * 1113 * Write the value @value of size @size from offset @offset within the 1114 * configuration space of the device identified by the bus, device & function 1115 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is 1116 * responsible for calculating the CPU address of the respective configuration 1117 * space offset. 1118 * 1119 * Return: 0 on success, else -EINVAL 1120 */ 1121 int pci_generic_mmap_write_config( 1122 struct udevice *bus, 1123 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), 1124 pci_dev_t bdf, 1125 uint offset, 1126 ulong value, 1127 enum pci_size_t size); 1128 1129 /** 1130 * pci_generic_mmap_read_config() - Generic helper for reading from 1131 * memory-mapped PCI configuration space. 1132 * @bus: Pointer to the PCI bus 1133 * @addr_f: Callback for calculating the config space address 1134 * @bdf: Identifies the PCI device to access 1135 * @offset: The offset into the device's configuration space 1136 * @valuep: A pointer at which to store the read value 1137 * @size: Indicates the size of access to perform 1138 * 1139 * Read a value of size @size from offset @offset within the configuration 1140 * space of the device identified by the bus, device & function numbers in @bdf 1141 * on the PCI bus @bus. The callback function @addr_f is responsible for 1142 * calculating the CPU address of the respective configuration space offset. 1143 * 1144 * Return: 0 on success, else -EINVAL 1145 */ 1146 int pci_generic_mmap_read_config( 1147 struct udevice *bus, 1148 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), 1149 pci_dev_t bdf, 1150 uint offset, 1151 ulong *valuep, 1152 enum pci_size_t size); 1153 1154 #ifdef CONFIG_DM_PCI_COMPAT 1155 /* Compatibility with old naming */ 1156 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, 1157 u32 value) 1158 { 1159 return pci_write_config32(pcidev, offset, value); 1160 } 1161 1162 /* Compatibility with old naming */ 1163 static inline int pci_write_config_word(pci_dev_t pcidev, int offset, 1164 u16 value) 1165 { 1166 return pci_write_config16(pcidev, offset, value); 1167 } 1168 1169 /* Compatibility with old naming */ 1170 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, 1171 u8 value) 1172 { 1173 return pci_write_config8(pcidev, offset, value); 1174 } 1175 1176 /* Compatibility with old naming */ 1177 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, 1178 u32 *valuep) 1179 { 1180 return pci_read_config32(pcidev, offset, valuep); 1181 } 1182 1183 /* Compatibility with old naming */ 1184 static inline int pci_read_config_word(pci_dev_t pcidev, int offset, 1185 u16 *valuep) 1186 { 1187 return pci_read_config16(pcidev, offset, valuep); 1188 } 1189 1190 /* Compatibility with old naming */ 1191 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, 1192 u8 *valuep) 1193 { 1194 return pci_read_config8(pcidev, offset, valuep); 1195 } 1196 #endif /* CONFIG_DM_PCI_COMPAT */ 1197 1198 /** 1199 * dm_pciauto_config_device() - configure a device ready for use 1200 * 1201 * Space is allocated for each PCI base address register (BAR) so that the 1202 * devices are mapped into memory and I/O space ready for use. 1203 * 1204 * @dev: Device to configure 1205 * @return 0 if OK, -ve on error 1206 */ 1207 int dm_pciauto_config_device(struct udevice *dev); 1208 1209 /** 1210 * pci_conv_32_to_size() - convert a 32-bit read value to the given size 1211 * 1212 * Some PCI buses must always perform 32-bit reads. The data must then be 1213 * shifted and masked to reflect the required access size and offset. This 1214 * function performs this transformation. 1215 * 1216 * @value: Value to transform (32-bit value read from @offset & ~3) 1217 * @offset: Register offset that was read 1218 * @size: Required size of the result 1219 * @return the value that would have been obtained if the read had been 1220 * performed at the given offset with the correct size 1221 */ 1222 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); 1223 1224 /** 1225 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write 1226 * 1227 * Some PCI buses must always perform 32-bit writes. To emulate a smaller 1228 * write the old 32-bit data must be read, updated with the required new data 1229 * and written back as a 32-bit value. This function performs the 1230 * transformation from the old value to the new value. 1231 * 1232 * @value: Value to transform (32-bit value read from @offset & ~3) 1233 * @offset: Register offset that should be written 1234 * @size: Required size of the write 1235 * @return the value that should be written as a 32-bit access to @offset & ~3. 1236 */ 1237 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, 1238 enum pci_size_t size); 1239 1240 /** 1241 * pci_get_controller() - obtain the controller to use for a bus 1242 * 1243 * @dev: Device to check 1244 * @return pointer to the controller device for this bus 1245 */ 1246 struct udevice *pci_get_controller(struct udevice *dev); 1247 1248 /** 1249 * pci_get_regions() - obtain pointers to all the region types 1250 * 1251 * @dev: Device to check 1252 * @iop: Returns a pointer to the I/O region, or NULL if none 1253 * @memp: Returns a pointer to the memory region, or NULL if none 1254 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none 1255 * @return the number of non-NULL regions returned, normally 3 1256 */ 1257 int pci_get_regions(struct udevice *dev, struct pci_region **iop, 1258 struct pci_region **memp, struct pci_region **prefp); 1259 1260 /** 1261 * dm_pci_write_bar32() - Write the address of a BAR 1262 * 1263 * This writes a raw address to a bar 1264 * 1265 * @dev: PCI device to update 1266 * @barnum: BAR number (0-5) 1267 * @addr: BAR address 1268 */ 1269 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); 1270 1271 /** 1272 * dm_pci_read_bar32() - read a base address register from a device 1273 * 1274 * @dev: Device to check 1275 * @barnum: Bar number to read (numbered from 0) 1276 * @return: value of BAR 1277 */ 1278 u32 dm_pci_read_bar32(struct udevice *dev, int barnum); 1279 1280 /** 1281 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address 1282 * 1283 * @dev: Device containing the PCI address 1284 * @addr: PCI address to convert 1285 * @flags: Flags for the region type (PCI_REGION_...) 1286 * @return physical address corresponding to that PCI bus address 1287 */ 1288 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, 1289 unsigned long flags); 1290 1291 /** 1292 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address 1293 * 1294 * @dev: Device containing the bus address 1295 * @addr: Physical address to convert 1296 * @flags: Flags for the region type (PCI_REGION_...) 1297 * @return PCI bus address corresponding to that physical address 1298 */ 1299 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, 1300 unsigned long flags); 1301 1302 /** 1303 * dm_pci_map_bar() - get a virtual address associated with a BAR region 1304 * 1305 * Looks up a base address register and finds the physical memory address 1306 * that corresponds to it 1307 * 1308 * @dev: Device to check 1309 * @bar: Bar number to read (numbered from 0) 1310 * @flags: Flags for the region type (PCI_REGION_...) 1311 * @return: pointer to the virtual address to use 1312 */ 1313 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); 1314 1315 /** 1316 * dm_pci_find_capability() - find a capability 1317 * 1318 * Tell if a device supports a given PCI capability. Returns the 1319 * address of the requested capability structure within the device's 1320 * PCI configuration space or 0 in case the device does not support it. 1321 * 1322 * Possible values for @cap: 1323 * 1324 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1325 * %PCI_CAP_ID_PCIX PCI-X 1326 * %PCI_CAP_ID_EXP PCI Express 1327 * %PCI_CAP_ID_MSIX MSI-X 1328 * 1329 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1330 * 1331 * @dev: PCI device to query 1332 * @cap: capability code 1333 * @return: capability address or 0 if not supported 1334 */ 1335 int dm_pci_find_capability(struct udevice *dev, int cap); 1336 1337 /** 1338 * dm_pci_find_ext_capability() - find an extended capability 1339 * 1340 * Tell if a device supports a given PCI express extended capability. 1341 * Returns the address of the requested extended capability structure 1342 * within the device's PCI configuration space or 0 in case the device 1343 * does not support it. 1344 * 1345 * Possible values for @cap: 1346 * 1347 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1348 * %PCI_EXT_CAP_ID_VC Virtual Channel 1349 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1350 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1351 * 1352 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1353 * 1354 * @dev: PCI device to query 1355 * @cap: extended capability code 1356 * @return: extended capability address or 0 if not supported 1357 */ 1358 int dm_pci_find_ext_capability(struct udevice *dev, int cap); 1359 1360 #define dm_pci_virt_to_bus(dev, addr, flags) \ 1361 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) 1362 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 1363 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \ 1364 (len), (map_flags)) 1365 1366 #define dm_pci_phys_to_mem(dev, addr) \ 1367 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 1368 #define dm_pci_mem_to_phys(dev, addr) \ 1369 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 1370 #define dm_pci_phys_to_io(dev, addr) \ 1371 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 1372 #define dm_pci_io_to_phys(dev, addr) \ 1373 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 1374 1375 #define dm_pci_virt_to_mem(dev, addr) \ 1376 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 1377 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ 1378 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 1379 #define dm_pci_virt_to_io(dev, addr) \ 1380 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 1381 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \ 1382 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 1383 1384 /** 1385 * dm_pci_find_device() - find a device by vendor/device ID 1386 * 1387 * @vendor: Vendor ID 1388 * @device: Device ID 1389 * @index: 0 to find the first match, 1 for second, etc. 1390 * @devp: Returns pointer to the device, if found 1391 * @return 0 if found, -ve on error 1392 */ 1393 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, 1394 struct udevice **devp); 1395 1396 /** 1397 * dm_pci_find_class() - find a device by class 1398 * 1399 * @find_class: 3-byte (24-bit) class value to find 1400 * @index: 0 to find the first match, 1 for second, etc. 1401 * @devp: Returns pointer to the device, if found 1402 * @return 0 if found, -ve on error 1403 */ 1404 int dm_pci_find_class(uint find_class, int index, struct udevice **devp); 1405 1406 /** 1407 * struct dm_pci_emul_ops - PCI device emulator operations 1408 */ 1409 struct dm_pci_emul_ops { 1410 /** 1411 * get_devfn(): Check which device and function this emulators 1412 * 1413 * @dev: device to check 1414 * @return the device and function this emulates, or -ve on error 1415 */ 1416 int (*get_devfn)(struct udevice *dev); 1417 /** 1418 * read_config() - Read a PCI configuration value 1419 * 1420 * @dev: Emulated device to read from 1421 * @offset: Byte offset within the device's configuration space 1422 * @valuep: Place to put the returned value 1423 * @size: Access size 1424 * @return 0 if OK, -ve on error 1425 */ 1426 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep, 1427 enum pci_size_t size); 1428 /** 1429 * write_config() - Write a PCI configuration value 1430 * 1431 * @dev: Emulated device to write to 1432 * @offset: Byte offset within the device's configuration space 1433 * @value: Value to write 1434 * @size: Access size 1435 * @return 0 if OK, -ve on error 1436 */ 1437 int (*write_config)(struct udevice *dev, uint offset, ulong value, 1438 enum pci_size_t size); 1439 /** 1440 * read_io() - Read a PCI I/O value 1441 * 1442 * @dev: Emulated device to read from 1443 * @addr: I/O address to read 1444 * @valuep: Place to put the returned value 1445 * @size: Access size 1446 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1447 * other -ve value on error 1448 */ 1449 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, 1450 enum pci_size_t size); 1451 /** 1452 * write_io() - Write a PCI I/O value 1453 * 1454 * @dev: Emulated device to write from 1455 * @addr: I/O address to write 1456 * @value: Value to write 1457 * @size: Access size 1458 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1459 * other -ve value on error 1460 */ 1461 int (*write_io)(struct udevice *dev, unsigned int addr, 1462 ulong value, enum pci_size_t size); 1463 /** 1464 * map_physmem() - Map a device into sandbox memory 1465 * 1466 * @dev: Emulated device to map 1467 * @addr: Memory address, normally corresponding to a PCI BAR. 1468 * The device should have been configured to have a BAR 1469 * at this address. 1470 * @lenp: On entry, the size of the area to map, On exit it is 1471 * updated to the size actually mapped, which may be less 1472 * if the device has less space 1473 * @ptrp: Returns a pointer to the mapped address. The device's 1474 * space can be accessed as @lenp bytes starting here 1475 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1476 * other -ve value on error 1477 */ 1478 int (*map_physmem)(struct udevice *dev, phys_addr_t addr, 1479 unsigned long *lenp, void **ptrp); 1480 /** 1481 * unmap_physmem() - undo a memory mapping 1482 * 1483 * This must be called after map_physmem() to undo the mapping. 1484 * Some devices can use this to check what has been written into 1485 * their mapped memory and perform an operations they require on it. 1486 * In this way, map/unmap can be used as a sort of handshake between 1487 * the emulated device and its users. 1488 * 1489 * @dev: Emuated device to unmap 1490 * @vaddr: Mapped memory address, as passed to map_physmem() 1491 * @len: Size of area mapped, as returned by map_physmem() 1492 * @return 0 if OK, -ve on error 1493 */ 1494 int (*unmap_physmem)(struct udevice *dev, const void *vaddr, 1495 unsigned long len); 1496 }; 1497 1498 /* Get access to a PCI device emulator's operations */ 1499 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) 1500 1501 /** 1502 * sandbox_pci_get_emul() - Get the emulation device for a PCI device 1503 * 1504 * Searches for a suitable emulator for the given PCI bus device 1505 * 1506 * @bus: PCI bus to search 1507 * @find_devfn: PCI device and function address (PCI_DEVFN()) 1508 * @containerp: Returns container device if found 1509 * @emulp: Returns emulated device if found 1510 * @return 0 if found, -ENODEV if not found 1511 */ 1512 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, 1513 struct udevice **containerp, struct udevice **emulp); 1514 1515 #endif /* CONFIG_DM_PCI */ 1516 1517 /** 1518 * PCI_DEVICE - macro used to describe a specific pci device 1519 * @vend: the 16 bit PCI Vendor ID 1520 * @dev: the 16 bit PCI Device ID 1521 * 1522 * This macro is used to create a struct pci_device_id that matches a 1523 * specific device. The subvendor and subdevice fields will be set to 1524 * PCI_ANY_ID. 1525 */ 1526 #define PCI_DEVICE(vend, dev) \ 1527 .vendor = (vend), .device = (dev), \ 1528 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1529 1530 /** 1531 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 1532 * @vend: the 16 bit PCI Vendor ID 1533 * @dev: the 16 bit PCI Device ID 1534 * @subvend: the 16 bit PCI Subvendor ID 1535 * @subdev: the 16 bit PCI Subdevice ID 1536 * 1537 * This macro is used to create a struct pci_device_id that matches a 1538 * specific device with subsystem information. 1539 */ 1540 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1541 .vendor = (vend), .device = (dev), \ 1542 .subvendor = (subvend), .subdevice = (subdev) 1543 1544 /** 1545 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 1546 * @dev_class: the class, subclass, prog-if triple for this device 1547 * @dev_class_mask: the class mask for this device 1548 * 1549 * This macro is used to create a struct pci_device_id that matches a 1550 * specific PCI class. The vendor, device, subvendor, and subdevice 1551 * fields will be set to PCI_ANY_ID. 1552 */ 1553 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ 1554 .class = (dev_class), .class_mask = (dev_class_mask), \ 1555 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1556 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1557 1558 /** 1559 * PCI_VDEVICE - macro used to describe a specific pci device in short form 1560 * @vend: the vendor name 1561 * @dev: the 16 bit PCI Device ID 1562 * 1563 * This macro is used to create a struct pci_device_id that matches a 1564 * specific PCI device. The subvendor, and subdevice fields will be set 1565 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1566 * private data. 1567 */ 1568 1569 #define PCI_VDEVICE(vend, dev) \ 1570 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1571 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1572 1573 /** 1574 * struct pci_driver_entry - Matches a driver to its pci_device_id list 1575 * @driver: Driver to use 1576 * @match: List of match records for this driver, terminated by {} 1577 */ 1578 struct pci_driver_entry { 1579 struct driver *driver; 1580 const struct pci_device_id *match; 1581 }; 1582 1583 #define U_BOOT_PCI_DEVICE(__name, __match) \ 1584 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\ 1585 .driver = llsym(struct driver, __name, driver), \ 1586 .match = __match, \ 1587 } 1588 1589 #endif /* __ASSEMBLY__ */ 1590 #endif /* _PCI_H */ 1591