1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _PCI_H 12 #define _PCI_H 13 14 /* 15 * Under PCI, each device has 256 bytes of configuration address space, 16 * of which the first 64 bytes are standardized as follows: 17 */ 18 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 19 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 20 #define PCI_COMMAND 0x04 /* 16 bits */ 21 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 22 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 23 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 24 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 25 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 26 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 27 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 28 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 29 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 30 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 31 32 #define PCI_STATUS 0x06 /* 16 bits */ 33 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 34 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 35 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 36 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 37 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 38 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 39 #define PCI_STATUS_DEVSEL_FAST 0x000 40 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 41 #define PCI_STATUS_DEVSEL_SLOW 0x400 42 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 43 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 44 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 45 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 46 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 47 48 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 49 revision */ 50 #define PCI_REVISION_ID 0x08 /* Revision ID */ 51 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 52 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 53 #define PCI_CLASS_CODE 0x0b /* Device class code */ 54 #define PCI_CLASS_CODE_TOO_OLD 0x00 55 #define PCI_CLASS_CODE_STORAGE 0x01 56 #define PCI_CLASS_CODE_NETWORK 0x02 57 #define PCI_CLASS_CODE_DISPLAY 0x03 58 #define PCI_CLASS_CODE_MULTIMEDIA 0x04 59 #define PCI_CLASS_CODE_MEMORY 0x05 60 #define PCI_CLASS_CODE_BRIDGE 0x06 61 #define PCI_CLASS_CODE_COMM 0x07 62 #define PCI_CLASS_CODE_PERIPHERAL 0x08 63 #define PCI_CLASS_CODE_INPUT 0x09 64 #define PCI_CLASS_CODE_DOCKING 0x0A 65 #define PCI_CLASS_CODE_PROCESSOR 0x0B 66 #define PCI_CLASS_CODE_SERIAL 0x0C 67 #define PCI_CLASS_CODE_WIRELESS 0x0D 68 #define PCI_CLASS_CODE_I2O 0x0E 69 #define PCI_CLASS_CODE_SATELLITE 0x0F 70 #define PCI_CLASS_CODE_CRYPTO 0x10 71 #define PCI_CLASS_CODE_DATA 0x11 72 /* Base Class 0x12 - 0xFE is reserved */ 73 #define PCI_CLASS_CODE_OTHER 0xFF 74 75 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 76 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 77 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 78 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 79 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 80 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 81 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 82 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 83 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 84 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 85 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 86 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 87 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 88 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 89 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 90 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 91 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 92 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 93 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 94 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 95 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 96 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 97 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 98 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 99 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 100 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 101 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 103 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 104 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 105 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 106 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 107 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 108 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 109 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 110 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 111 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 112 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 113 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 114 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 115 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 116 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A 117 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 118 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 119 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 120 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 121 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 122 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 123 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 124 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 125 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 126 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 127 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 132 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 133 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 134 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 135 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 136 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 137 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 138 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 139 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 140 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 141 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 142 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 143 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 144 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 145 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 146 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 147 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 148 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 149 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 150 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 151 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 152 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 153 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 154 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 155 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 156 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 157 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 158 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 159 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 160 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 161 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 162 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 163 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 164 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 165 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 166 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 167 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 168 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 169 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 170 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 171 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 172 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 173 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 174 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 175 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 176 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 177 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 178 179 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 180 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 181 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 182 #define PCI_HEADER_TYPE_NORMAL 0 183 #define PCI_HEADER_TYPE_BRIDGE 1 184 #define PCI_HEADER_TYPE_CARDBUS 2 185 186 #define PCI_BIST 0x0f /* 8 bits */ 187 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 188 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 189 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 190 191 /* 192 * Base addresses specify locations in memory or I/O space. 193 * Decoded size can be determined by writing a value of 194 * 0xffffffff to the register, and reading it back. Only 195 * 1 bits are decoded. 196 */ 197 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 198 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 199 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 200 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 201 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 202 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 203 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 204 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 205 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 206 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 207 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 208 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 209 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 210 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 211 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 212 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 213 /* bit 1 is reserved if address_space = 1 */ 214 215 /* Header type 0 (normal devices) */ 216 #define PCI_CARDBUS_CIS 0x28 217 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 218 #define PCI_SUBSYSTEM_ID 0x2e 219 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 220 #define PCI_ROM_ADDRESS_ENABLE 0x01 221 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 222 223 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 224 225 /* 0x35-0x3b are reserved */ 226 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 227 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 228 #define PCI_MIN_GNT 0x3e /* 8 bits */ 229 #define PCI_MAX_LAT 0x3f /* 8 bits */ 230 231 /* Header type 1 (PCI-to-PCI bridges) */ 232 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 233 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 234 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 235 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 236 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 237 #define PCI_IO_LIMIT 0x1d 238 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 239 #define PCI_IO_RANGE_TYPE_16 0x00 240 #define PCI_IO_RANGE_TYPE_32 0x01 241 #define PCI_IO_RANGE_MASK ~0x0f 242 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 243 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 244 #define PCI_MEMORY_LIMIT 0x22 245 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 246 #define PCI_MEMORY_RANGE_MASK ~0x0f 247 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 248 #define PCI_PREF_MEMORY_LIMIT 0x26 249 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 250 #define PCI_PREF_RANGE_TYPE_32 0x00 251 #define PCI_PREF_RANGE_TYPE_64 0x01 252 #define PCI_PREF_RANGE_MASK ~0x0f 253 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 254 #define PCI_PREF_LIMIT_UPPER32 0x2c 255 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 256 #define PCI_IO_LIMIT_UPPER16 0x32 257 /* 0x34 same as for htype 0 */ 258 /* 0x35-0x3b is reserved */ 259 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 260 /* 0x3c-0x3d are same as for htype 0 */ 261 #define PCI_BRIDGE_CONTROL 0x3e 262 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 263 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 264 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 265 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 266 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 267 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 268 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 269 270 /* From 440ep */ 271 #define PCI_ERREN 0x48 /* Error Enable */ 272 #define PCI_ERRSTS 0x49 /* Error Status */ 273 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ 274 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ 275 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ 276 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ 277 #define PCI_CAPID 0x58 /* Capability Identifier */ 278 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ 279 #define PCI_PMC 0x5A /* Power Management Capabilities */ 280 #define PCI_PMCSR 0x5C /* Power Management Control Status */ 281 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ 282 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ 283 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ 284 285 /* Header type 2 (CardBus bridges) */ 286 #define PCI_CB_CAPABILITY_LIST 0x14 287 /* 0x15 reserved */ 288 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 289 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 290 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 291 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 292 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 293 #define PCI_CB_MEMORY_BASE_0 0x1c 294 #define PCI_CB_MEMORY_LIMIT_0 0x20 295 #define PCI_CB_MEMORY_BASE_1 0x24 296 #define PCI_CB_MEMORY_LIMIT_1 0x28 297 #define PCI_CB_IO_BASE_0 0x2c 298 #define PCI_CB_IO_BASE_0_HI 0x2e 299 #define PCI_CB_IO_LIMIT_0 0x30 300 #define PCI_CB_IO_LIMIT_0_HI 0x32 301 #define PCI_CB_IO_BASE_1 0x34 302 #define PCI_CB_IO_BASE_1_HI 0x36 303 #define PCI_CB_IO_LIMIT_1 0x38 304 #define PCI_CB_IO_LIMIT_1_HI 0x3a 305 #define PCI_CB_IO_RANGE_MASK ~0x03 306 /* 0x3c-0x3d are same as for htype 0 */ 307 #define PCI_CB_BRIDGE_CONTROL 0x3e 308 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 309 #define PCI_CB_BRIDGE_CTL_SERR 0x02 310 #define PCI_CB_BRIDGE_CTL_ISA 0x04 311 #define PCI_CB_BRIDGE_CTL_VGA 0x08 312 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 313 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 314 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 315 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 316 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 317 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 318 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 319 #define PCI_CB_SUBSYSTEM_ID 0x42 320 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 321 /* 0x48-0x7f reserved */ 322 323 /* Capability lists */ 324 325 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 326 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 327 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 328 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 329 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 330 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 331 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 332 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 333 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 334 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 335 #define PCI_CAP_SIZEOF 4 336 337 /* Power Management Registers */ 338 339 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 340 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 341 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 342 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 343 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 344 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 345 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 346 #define PCI_PM_CTRL 4 /* PM control and status register */ 347 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 348 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 349 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 350 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 351 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 352 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 353 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 354 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 355 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 356 #define PCI_PM_SIZEOF 8 357 358 /* AGP registers */ 359 360 #define PCI_AGP_VERSION 2 /* BCD version number */ 361 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 362 #define PCI_AGP_STATUS 4 /* Status register */ 363 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 364 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 365 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 366 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 367 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 368 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 369 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 370 #define PCI_AGP_COMMAND 8 /* Control register */ 371 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 372 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 373 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 374 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 375 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 376 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 377 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 378 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 379 #define PCI_AGP_SIZEOF 12 380 381 /* PCI-X registers */ 382 383 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 384 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 385 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 386 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 387 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 388 389 390 /* Slot Identification */ 391 392 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 393 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 394 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 395 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 396 397 /* Message Signalled Interrupts registers */ 398 399 #define PCI_MSI_FLAGS 2 /* Various flags */ 400 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 401 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 402 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 403 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 404 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 405 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 406 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 407 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 408 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 409 410 #define PCI_MAX_PCI_DEVICES 32 411 #define PCI_MAX_PCI_FUNCTIONS 8 412 413 #define PCI_FIND_CAP_TTL 0x48 414 #define CAP_START_POS 0x40 415 416 /* Include the ID list */ 417 418 #include <pci_ids.h> 419 420 #ifdef CONFIG_SYS_PCI_64BIT 421 typedef u64 pci_addr_t; 422 typedef u64 pci_size_t; 423 #else 424 typedef u32 pci_addr_t; 425 typedef u32 pci_size_t; 426 #endif 427 428 struct pci_region { 429 pci_addr_t bus_start; /* Start on the bus */ 430 phys_addr_t phys_start; /* Start in physical address space */ 431 pci_size_t size; /* Size */ 432 unsigned long flags; /* Resource flags */ 433 434 pci_addr_t bus_lower; 435 }; 436 437 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 438 #define PCI_REGION_IO 0x00000001 /* PCI IO space */ 439 #define PCI_REGION_TYPE 0x00000001 440 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 441 442 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 443 #define PCI_REGION_RO 0x00000200 /* Read-only memory */ 444 445 static inline void pci_set_region(struct pci_region *reg, 446 pci_addr_t bus_start, 447 phys_addr_t phys_start, 448 pci_size_t size, 449 unsigned long flags) { 450 reg->bus_start = bus_start; 451 reg->phys_start = phys_start; 452 reg->size = size; 453 reg->flags = flags; 454 } 455 456 typedef int pci_dev_t; 457 458 #define PCI_BUS(d) (((d) >> 16) & 0xff) 459 #define PCI_DEV(d) (((d) >> 11) & 0x1f) 460 #define PCI_FUNC(d) (((d) >> 8) & 0x7) 461 #define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8) 462 463 #define PCI_ANY_ID (~0) 464 465 struct pci_device_id { 466 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 467 }; 468 469 struct pci_controller; 470 471 struct pci_config_table { 472 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 473 unsigned int class; /* Class ID, or PCI_ANY_ID */ 474 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 475 unsigned int dev; /* Device number, or PCI_ANY_ID */ 476 unsigned int func; /* Function number, or PCI_ANY_ID */ 477 478 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 479 struct pci_config_table *); 480 unsigned long priv[3]; 481 }; 482 483 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 484 struct pci_config_table *); 485 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 486 struct pci_config_table *); 487 488 #define MAX_PCI_REGIONS 7 489 490 #define INDIRECT_TYPE_NO_PCIE_LINK 1 491 492 /* 493 * Structure of a PCI controller (host bridge) 494 */ 495 struct pci_controller { 496 struct pci_controller *next; 497 498 int first_busno; 499 int last_busno; 500 501 volatile unsigned int *cfg_addr; 502 volatile unsigned char *cfg_data; 503 504 int indirect_type; 505 506 struct pci_region regions[MAX_PCI_REGIONS]; 507 int region_count; 508 509 struct pci_config_table *config_table; 510 511 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 512 513 /* Low-level architecture-dependent routines */ 514 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); 515 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); 516 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); 517 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); 518 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); 519 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); 520 521 /* Used by auto config */ 522 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 523 524 /* Used by ppc405 autoconfig*/ 525 struct pci_region *pci_fb; 526 int current_busno; 527 528 void *priv_data; 529 }; 530 531 static inline void pci_set_ops(struct pci_controller *hose, 532 int (*read_byte)(struct pci_controller*, 533 pci_dev_t, int where, u8 *), 534 int (*read_word)(struct pci_controller*, 535 pci_dev_t, int where, u16 *), 536 int (*read_dword)(struct pci_controller*, 537 pci_dev_t, int where, u32 *), 538 int (*write_byte)(struct pci_controller*, 539 pci_dev_t, int where, u8), 540 int (*write_word)(struct pci_controller*, 541 pci_dev_t, int where, u16), 542 int (*write_dword)(struct pci_controller*, 543 pci_dev_t, int where, u32)) { 544 hose->read_byte = read_byte; 545 hose->read_word = read_word; 546 hose->read_dword = read_dword; 547 hose->write_byte = write_byte; 548 hose->write_word = write_word; 549 hose->write_dword = write_dword; 550 } 551 552 #ifdef CONFIG_PCI_INDIRECT_BRIDGE 553 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); 554 #endif 555 556 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 557 pci_addr_t addr, unsigned long flags); 558 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 559 phys_addr_t addr, unsigned long flags); 560 561 #define pci_phys_to_bus(dev, addr, flags) \ 562 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 563 #define pci_bus_to_phys(dev, addr, flags) \ 564 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 565 566 #define pci_virt_to_bus(dev, addr, flags) \ 567 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 568 (virt_to_phys(addr)), (flags)) 569 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 570 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 571 (addr), (flags)), \ 572 (len), (map_flags)) 573 574 #define pci_phys_to_mem(dev, addr) \ 575 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 576 #define pci_mem_to_phys(dev, addr) \ 577 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 578 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 579 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 580 581 #define pci_virt_to_mem(dev, addr) \ 582 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 583 #define pci_mem_to_virt(dev, addr, len, map_flags) \ 584 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 585 #define pci_virt_to_io(dev, addr) \ 586 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 587 #define pci_io_to_virt(dev, addr, len, map_flags) \ 588 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 589 590 extern int pci_hose_read_config_byte(struct pci_controller *hose, 591 pci_dev_t dev, int where, u8 *val); 592 extern int pci_hose_read_config_word(struct pci_controller *hose, 593 pci_dev_t dev, int where, u16 *val); 594 extern int pci_hose_read_config_dword(struct pci_controller *hose, 595 pci_dev_t dev, int where, u32 *val); 596 extern int pci_hose_write_config_byte(struct pci_controller *hose, 597 pci_dev_t dev, int where, u8 val); 598 extern int pci_hose_write_config_word(struct pci_controller *hose, 599 pci_dev_t dev, int where, u16 val); 600 extern int pci_hose_write_config_dword(struct pci_controller *hose, 601 pci_dev_t dev, int where, u32 val); 602 603 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); 604 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); 605 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); 606 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); 607 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); 608 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); 609 610 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 611 pci_dev_t dev, int where, u8 *val); 612 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 613 pci_dev_t dev, int where, u16 *val); 614 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 615 pci_dev_t dev, int where, u8 val); 616 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 617 pci_dev_t dev, int where, u16 val); 618 619 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 620 extern void pci_register_hose(struct pci_controller* hose); 621 extern struct pci_controller* pci_bus_to_hose(int bus); 622 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 623 624 extern int pci_hose_scan(struct pci_controller *hose); 625 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 626 627 extern void pciauto_region_init(struct pci_region* res); 628 extern void pciauto_region_align(struct pci_region *res, pci_size_t size); 629 extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar); 630 extern void pciauto_setup_device(struct pci_controller *hose, 631 pci_dev_t dev, int bars_num, 632 struct pci_region *mem, 633 struct pci_region *prefetch, 634 struct pci_region *io); 635 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 636 pci_dev_t dev, int sub_bus); 637 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 638 pci_dev_t dev, int sub_bus); 639 extern void pciauto_config_init(struct pci_controller *hose); 640 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 641 642 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 643 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 644 extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code, 645 int wanted_prog_if, int index); 646 647 extern int pci_hose_config_device(struct pci_controller *hose, 648 pci_dev_t dev, 649 unsigned long io, 650 pci_addr_t mem, 651 unsigned long command); 652 653 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 654 int cap); 655 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 656 u8 hdr_type); 657 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 658 int cap); 659 660 const char * pci_class_str(u8 class); 661 int pci_last_busno(void); 662 663 #ifdef CONFIG_MPC824X 664 extern void pci_mpc824x_init (struct pci_controller *hose); 665 #endif 666 667 #ifdef CONFIG_MPC85xx 668 extern void pci_mpc85xx_init (struct pci_controller *hose); 669 #endif 670 #endif /* _PCI_H */ 671