1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _PCI_H 12 #define _PCI_H 13 14 #define PCI_CFG_SPACE_SIZE 256 15 #define PCI_CFG_SPACE_EXP_SIZE 4096 16 17 /* 18 * Under PCI, each device has 256 bytes of configuration address space, 19 * of which the first 64 bytes are standardized as follows: 20 */ 21 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 22 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 23 #define PCI_COMMAND 0x04 /* 16 bits */ 24 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 25 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 26 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 27 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 28 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 29 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 30 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 31 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 32 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 33 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 34 35 #define PCI_STATUS 0x06 /* 16 bits */ 36 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 37 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 38 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 39 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 40 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 41 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 42 #define PCI_STATUS_DEVSEL_FAST 0x000 43 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 44 #define PCI_STATUS_DEVSEL_SLOW 0x400 45 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 46 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 47 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 48 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 49 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 50 51 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 52 revision */ 53 #define PCI_REVISION_ID 0x08 /* Revision ID */ 54 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 55 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 56 #define PCI_CLASS_CODE 0x0b /* Device class code */ 57 #define PCI_CLASS_CODE_TOO_OLD 0x00 58 #define PCI_CLASS_CODE_STORAGE 0x01 59 #define PCI_CLASS_CODE_NETWORK 0x02 60 #define PCI_CLASS_CODE_DISPLAY 0x03 61 #define PCI_CLASS_CODE_MULTIMEDIA 0x04 62 #define PCI_CLASS_CODE_MEMORY 0x05 63 #define PCI_CLASS_CODE_BRIDGE 0x06 64 #define PCI_CLASS_CODE_COMM 0x07 65 #define PCI_CLASS_CODE_PERIPHERAL 0x08 66 #define PCI_CLASS_CODE_INPUT 0x09 67 #define PCI_CLASS_CODE_DOCKING 0x0A 68 #define PCI_CLASS_CODE_PROCESSOR 0x0B 69 #define PCI_CLASS_CODE_SERIAL 0x0C 70 #define PCI_CLASS_CODE_WIRELESS 0x0D 71 #define PCI_CLASS_CODE_I2O 0x0E 72 #define PCI_CLASS_CODE_SATELLITE 0x0F 73 #define PCI_CLASS_CODE_CRYPTO 0x10 74 #define PCI_CLASS_CODE_DATA 0x11 75 /* Base Class 0x12 - 0xFE is reserved */ 76 #define PCI_CLASS_CODE_OTHER 0xFF 77 78 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 79 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 80 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 81 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 82 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 83 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 84 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 85 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 86 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 87 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 88 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 89 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 90 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 91 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 92 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 93 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 94 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 95 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 96 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 97 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 98 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 99 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 100 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 101 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 105 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 106 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 107 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 108 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 109 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 110 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 111 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 112 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 113 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 114 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 115 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 116 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 117 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 118 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 119 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A 120 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 121 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 122 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 123 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 124 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 125 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 126 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 127 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 134 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 135 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 136 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 137 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 138 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 139 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 140 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 141 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 142 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 143 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 144 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 145 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 146 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 147 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 148 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 149 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 150 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 151 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 152 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 153 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 154 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 155 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 156 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 157 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 158 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 159 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 160 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 161 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 162 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 163 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 164 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 165 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 166 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 167 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 168 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 169 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 170 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 171 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 172 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 173 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 174 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 175 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 176 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 177 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 178 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 179 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 180 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 181 182 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 183 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 184 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 185 #define PCI_HEADER_TYPE_NORMAL 0 186 #define PCI_HEADER_TYPE_BRIDGE 1 187 #define PCI_HEADER_TYPE_CARDBUS 2 188 189 #define PCI_BIST 0x0f /* 8 bits */ 190 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 191 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 192 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 193 194 /* 195 * Base addresses specify locations in memory or I/O space. 196 * Decoded size can be determined by writing a value of 197 * 0xffffffff to the register, and reading it back. Only 198 * 1 bits are decoded. 199 */ 200 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 201 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 202 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 203 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 204 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 205 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 206 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 207 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 208 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 209 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 210 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 211 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 212 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 213 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 214 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 215 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 216 /* bit 1 is reserved if address_space = 1 */ 217 218 /* Header type 0 (normal devices) */ 219 #define PCI_CARDBUS_CIS 0x28 220 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 221 #define PCI_SUBSYSTEM_ID 0x2e 222 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 223 #define PCI_ROM_ADDRESS_ENABLE 0x01 224 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 225 226 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 227 228 /* 0x35-0x3b are reserved */ 229 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 230 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 231 #define PCI_MIN_GNT 0x3e /* 8 bits */ 232 #define PCI_MAX_LAT 0x3f /* 8 bits */ 233 234 /* Header type 1 (PCI-to-PCI bridges) */ 235 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 236 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 237 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 238 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 239 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 240 #define PCI_IO_LIMIT 0x1d 241 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 242 #define PCI_IO_RANGE_TYPE_16 0x00 243 #define PCI_IO_RANGE_TYPE_32 0x01 244 #define PCI_IO_RANGE_MASK ~0x0f 245 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 246 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 247 #define PCI_MEMORY_LIMIT 0x22 248 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 249 #define PCI_MEMORY_RANGE_MASK ~0x0f 250 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 251 #define PCI_PREF_MEMORY_LIMIT 0x26 252 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 253 #define PCI_PREF_RANGE_TYPE_32 0x00 254 #define PCI_PREF_RANGE_TYPE_64 0x01 255 #define PCI_PREF_RANGE_MASK ~0x0f 256 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 257 #define PCI_PREF_LIMIT_UPPER32 0x2c 258 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 259 #define PCI_IO_LIMIT_UPPER16 0x32 260 /* 0x34 same as for htype 0 */ 261 /* 0x35-0x3b is reserved */ 262 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 263 /* 0x3c-0x3d are same as for htype 0 */ 264 #define PCI_BRIDGE_CONTROL 0x3e 265 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 266 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 267 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 268 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 269 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 270 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 271 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 272 273 /* From 440ep */ 274 #define PCI_ERREN 0x48 /* Error Enable */ 275 #define PCI_ERRSTS 0x49 /* Error Status */ 276 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ 277 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ 278 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ 279 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ 280 #define PCI_CAPID 0x58 /* Capability Identifier */ 281 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ 282 #define PCI_PMC 0x5A /* Power Management Capabilities */ 283 #define PCI_PMCSR 0x5C /* Power Management Control Status */ 284 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ 285 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ 286 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ 287 288 /* Header type 2 (CardBus bridges) */ 289 #define PCI_CB_CAPABILITY_LIST 0x14 290 /* 0x15 reserved */ 291 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 292 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 293 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 294 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 295 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 296 #define PCI_CB_MEMORY_BASE_0 0x1c 297 #define PCI_CB_MEMORY_LIMIT_0 0x20 298 #define PCI_CB_MEMORY_BASE_1 0x24 299 #define PCI_CB_MEMORY_LIMIT_1 0x28 300 #define PCI_CB_IO_BASE_0 0x2c 301 #define PCI_CB_IO_BASE_0_HI 0x2e 302 #define PCI_CB_IO_LIMIT_0 0x30 303 #define PCI_CB_IO_LIMIT_0_HI 0x32 304 #define PCI_CB_IO_BASE_1 0x34 305 #define PCI_CB_IO_BASE_1_HI 0x36 306 #define PCI_CB_IO_LIMIT_1 0x38 307 #define PCI_CB_IO_LIMIT_1_HI 0x3a 308 #define PCI_CB_IO_RANGE_MASK ~0x03 309 /* 0x3c-0x3d are same as for htype 0 */ 310 #define PCI_CB_BRIDGE_CONTROL 0x3e 311 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 312 #define PCI_CB_BRIDGE_CTL_SERR 0x02 313 #define PCI_CB_BRIDGE_CTL_ISA 0x04 314 #define PCI_CB_BRIDGE_CTL_VGA 0x08 315 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 316 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 317 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 318 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 319 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 320 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 321 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 322 #define PCI_CB_SUBSYSTEM_ID 0x42 323 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 324 /* 0x48-0x7f reserved */ 325 326 /* Capability lists */ 327 328 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 329 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 330 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 331 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 332 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 333 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 334 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 335 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 336 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 337 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 338 #define PCI_CAP_SIZEOF 4 339 340 /* Power Management Registers */ 341 342 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 343 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 344 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 345 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 346 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 347 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 348 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 349 #define PCI_PM_CTRL 4 /* PM control and status register */ 350 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 351 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 352 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 353 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 354 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 355 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 356 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 357 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 358 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 359 #define PCI_PM_SIZEOF 8 360 361 /* AGP registers */ 362 363 #define PCI_AGP_VERSION 2 /* BCD version number */ 364 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 365 #define PCI_AGP_STATUS 4 /* Status register */ 366 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 367 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 368 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 369 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 370 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 371 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 372 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 373 #define PCI_AGP_COMMAND 8 /* Control register */ 374 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 375 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 376 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 377 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 378 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 379 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 380 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 381 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 382 #define PCI_AGP_SIZEOF 12 383 384 /* PCI-X registers */ 385 386 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 387 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 388 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 389 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 390 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 391 392 393 /* Slot Identification */ 394 395 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 396 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 397 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 398 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 399 400 /* Message Signalled Interrupts registers */ 401 402 #define PCI_MSI_FLAGS 2 /* Various flags */ 403 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 404 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 405 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 406 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 407 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 408 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 409 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 410 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 411 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 412 413 #define PCI_MAX_PCI_DEVICES 32 414 #define PCI_MAX_PCI_FUNCTIONS 8 415 416 #define PCI_FIND_CAP_TTL 0x48 417 #define CAP_START_POS 0x40 418 419 /* Extended Capabilities (PCI-X 2.0 and Express) */ 420 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 421 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 422 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 423 424 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 425 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 426 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 427 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 428 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 429 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 430 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 431 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 432 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 433 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 434 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 435 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 436 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 437 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 438 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 439 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 440 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 441 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 442 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 443 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 444 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 445 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 446 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 447 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 448 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 449 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 450 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 451 452 /* Include the ID list */ 453 454 #include <pci_ids.h> 455 456 #ifndef __ASSEMBLY__ 457 458 #ifdef CONFIG_SYS_PCI_64BIT 459 typedef u64 pci_addr_t; 460 typedef u64 pci_size_t; 461 #else 462 typedef u32 pci_addr_t; 463 typedef u32 pci_size_t; 464 #endif 465 466 struct pci_region { 467 pci_addr_t bus_start; /* Start on the bus */ 468 phys_addr_t phys_start; /* Start in physical address space */ 469 pci_size_t size; /* Size */ 470 unsigned long flags; /* Resource flags */ 471 472 pci_addr_t bus_lower; 473 }; 474 475 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 476 #define PCI_REGION_IO 0x00000001 /* PCI IO space */ 477 #define PCI_REGION_TYPE 0x00000001 478 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 479 480 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 481 #define PCI_REGION_RO 0x00000200 /* Read-only memory */ 482 483 static inline void pci_set_region(struct pci_region *reg, 484 pci_addr_t bus_start, 485 phys_addr_t phys_start, 486 pci_size_t size, 487 unsigned long flags) { 488 reg->bus_start = bus_start; 489 reg->phys_start = phys_start; 490 reg->size = size; 491 reg->flags = flags; 492 } 493 494 typedef int pci_dev_t; 495 496 #define PCI_BUS(d) (((d) >> 16) & 0xff) 497 #define PCI_DEV(d) (((d) >> 11) & 0x1f) 498 #define PCI_FUNC(d) (((d) >> 8) & 0x7) 499 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) 500 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) 501 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) 502 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) 503 #define PCI_VENDEV(v, d) (((v) << 16) | (d)) 504 #define PCI_ANY_ID (~0) 505 506 struct pci_device_id { 507 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 508 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ 509 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ 510 unsigned long driver_data; /* Data private to the driver */ 511 }; 512 513 struct pci_controller; 514 515 struct pci_config_table { 516 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 517 unsigned int class; /* Class ID, or PCI_ANY_ID */ 518 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 519 unsigned int dev; /* Device number, or PCI_ANY_ID */ 520 unsigned int func; /* Function number, or PCI_ANY_ID */ 521 522 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 523 struct pci_config_table *); 524 unsigned long priv[3]; 525 }; 526 527 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 528 struct pci_config_table *); 529 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 530 struct pci_config_table *); 531 532 #define MAX_PCI_REGIONS 7 533 534 #define INDIRECT_TYPE_NO_PCIE_LINK 1 535 536 /* 537 * Structure of a PCI controller (host bridge) 538 */ 539 struct pci_controller { 540 #ifdef CONFIG_DM_PCI 541 struct udevice *bus; 542 struct udevice *ctlr; 543 #else 544 struct pci_controller *next; 545 #endif 546 547 int first_busno; 548 int last_busno; 549 550 volatile unsigned int *cfg_addr; 551 volatile unsigned char *cfg_data; 552 553 int indirect_type; 554 555 /* 556 * TODO(sjg@chromium.org): With driver model we use struct 557 * pci_controller for both the controller and any bridge devices 558 * attached to it. But there is only one region list and it is in the 559 * top-level controller. 560 * 561 * This could be changed so that struct pci_controller is only used 562 * for PCI controllers and a separate UCLASS (or perhaps 563 * UCLASS_PCI_GENERIC) is used for bridges. 564 */ 565 struct pci_region regions[MAX_PCI_REGIONS]; 566 int region_count; 567 568 struct pci_config_table *config_table; 569 570 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 571 #ifndef CONFIG_DM_PCI 572 /* Low-level architecture-dependent routines */ 573 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); 574 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); 575 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); 576 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); 577 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); 578 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); 579 #endif 580 581 /* Used by auto config */ 582 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 583 584 /* Used by ppc405 autoconfig*/ 585 struct pci_region *pci_fb; 586 #ifndef CONFIG_DM_PCI 587 int current_busno; 588 589 void *priv_data; 590 #endif 591 }; 592 593 #ifndef CONFIG_DM_PCI 594 static inline void pci_set_ops(struct pci_controller *hose, 595 int (*read_byte)(struct pci_controller*, 596 pci_dev_t, int where, u8 *), 597 int (*read_word)(struct pci_controller*, 598 pci_dev_t, int where, u16 *), 599 int (*read_dword)(struct pci_controller*, 600 pci_dev_t, int where, u32 *), 601 int (*write_byte)(struct pci_controller*, 602 pci_dev_t, int where, u8), 603 int (*write_word)(struct pci_controller*, 604 pci_dev_t, int where, u16), 605 int (*write_dword)(struct pci_controller*, 606 pci_dev_t, int where, u32)) { 607 hose->read_byte = read_byte; 608 hose->read_word = read_word; 609 hose->read_dword = read_dword; 610 hose->write_byte = write_byte; 611 hose->write_word = write_word; 612 hose->write_dword = write_dword; 613 } 614 #endif 615 616 #ifdef CONFIG_PCI_INDIRECT_BRIDGE 617 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); 618 #endif 619 620 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 621 pci_addr_t addr, unsigned long flags); 622 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 623 phys_addr_t addr, unsigned long flags); 624 625 #define pci_phys_to_bus(dev, addr, flags) \ 626 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 627 #define pci_bus_to_phys(dev, addr, flags) \ 628 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 629 630 #define pci_virt_to_bus(dev, addr, flags) \ 631 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 632 (virt_to_phys(addr)), (flags)) 633 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 634 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 635 (addr), (flags)), \ 636 (len), (map_flags)) 637 638 #define pci_phys_to_mem(dev, addr) \ 639 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 640 #define pci_mem_to_phys(dev, addr) \ 641 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 642 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 643 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 644 645 #define pci_virt_to_mem(dev, addr) \ 646 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 647 #define pci_mem_to_virt(dev, addr, len, map_flags) \ 648 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 649 #define pci_virt_to_io(dev, addr) \ 650 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 651 #define pci_io_to_virt(dev, addr, len, map_flags) \ 652 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 653 654 extern int pci_hose_read_config_byte(struct pci_controller *hose, 655 pci_dev_t dev, int where, u8 *val); 656 extern int pci_hose_read_config_word(struct pci_controller *hose, 657 pci_dev_t dev, int where, u16 *val); 658 extern int pci_hose_read_config_dword(struct pci_controller *hose, 659 pci_dev_t dev, int where, u32 *val); 660 extern int pci_hose_write_config_byte(struct pci_controller *hose, 661 pci_dev_t dev, int where, u8 val); 662 extern int pci_hose_write_config_word(struct pci_controller *hose, 663 pci_dev_t dev, int where, u16 val); 664 extern int pci_hose_write_config_dword(struct pci_controller *hose, 665 pci_dev_t dev, int where, u32 val); 666 667 #ifndef CONFIG_DM_PCI 668 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); 669 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); 670 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); 671 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); 672 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); 673 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); 674 #endif 675 676 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 677 pci_dev_t dev, int where, u8 *val); 678 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 679 pci_dev_t dev, int where, u16 *val); 680 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 681 pci_dev_t dev, int where, u8 val); 682 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 683 pci_dev_t dev, int where, u16 val); 684 685 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 686 extern void pci_register_hose(struct pci_controller* hose); 687 extern struct pci_controller* pci_bus_to_hose(int bus); 688 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 689 690 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); 691 extern int pci_hose_scan(struct pci_controller *hose); 692 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 693 694 extern void pciauto_region_init(struct pci_region* res); 695 extern void pciauto_region_align(struct pci_region *res, pci_size_t size); 696 extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar); 697 extern void pciauto_setup_device(struct pci_controller *hose, 698 pci_dev_t dev, int bars_num, 699 struct pci_region *mem, 700 struct pci_region *prefetch, 701 struct pci_region *io); 702 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 703 pci_dev_t dev, int sub_bus); 704 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 705 pci_dev_t dev, int sub_bus); 706 extern void pciauto_config_init(struct pci_controller *hose); 707 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 708 709 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 710 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 711 pci_dev_t pci_find_class(unsigned int find_class, int index); 712 713 extern int pci_hose_config_device(struct pci_controller *hose, 714 pci_dev_t dev, 715 unsigned long io, 716 pci_addr_t mem, 717 unsigned long command); 718 719 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 720 int cap); 721 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 722 u8 hdr_type); 723 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 724 int cap); 725 726 int pci_find_next_ext_capability(struct pci_controller *hose, 727 pci_dev_t dev, int start, int cap); 728 int pci_hose_find_ext_capability(struct pci_controller *hose, 729 pci_dev_t dev, int cap); 730 731 #ifdef CONFIG_PCI_FIXUP_DEV 732 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 733 unsigned short vendor, 734 unsigned short device, 735 unsigned short class); 736 #endif 737 738 const char * pci_class_str(u8 class); 739 int pci_last_busno(void); 740 741 #ifdef CONFIG_MPC85xx 742 extern void pci_mpc85xx_init (struct pci_controller *hose); 743 #endif 744 745 /** 746 * pci_write_bar32() - Write the address of a BAR including control bits 747 * 748 * This writes a raw address (with control bits) to a bar 749 * 750 * @hose: PCI hose to use 751 * @dev: PCI device to update 752 * @barnum: BAR number (0-5) 753 * @addr: BAR address with control bits 754 */ 755 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, 756 u32 addr_and_ctrl); 757 758 /** 759 * pci_read_bar32() - read the address of a bar 760 * 761 * @hose: PCI hose to use 762 * @dev: PCI device to inspect 763 * @barnum: BAR number (0-5) 764 * @return address of the bar, masking out any control bits 765 * */ 766 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); 767 768 /** 769 * pci_hose_find_devices() - Find devices by vendor/device ID 770 * 771 * @hose: PCI hose to search 772 * @busnum: Bus number to search 773 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 774 * @indexp: Pointer to device index to find. To find the first matching 775 * device, pass 0; to find the second, pass 1, etc. This 776 * parameter is decremented for each non-matching device so 777 * can be called repeatedly. 778 */ 779 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, 780 struct pci_device_id *ids, int *indexp); 781 782 /* Access sizes for PCI reads and writes */ 783 enum pci_size_t { 784 PCI_SIZE_8, 785 PCI_SIZE_16, 786 PCI_SIZE_32, 787 }; 788 789 struct udevice; 790 791 #ifdef CONFIG_DM_PCI 792 /** 793 * struct pci_child_platdata - information stored about each PCI device 794 * 795 * Every device on a PCI bus has this per-child data. 796 * 797 * It can be accessed using dev_get_parentdata(dev) if dev->parent is a 798 * PCI bus (i.e. UCLASS_PCI) 799 * 800 * @devfn: Encoded device and function index - see PCI_DEVFN() 801 * @vendor: PCI vendor ID (see pci_ids.h) 802 * @device: PCI device ID (see pci_ids.h) 803 * @class: PCI class, 3 bytes: (base, sub, prog-if) 804 */ 805 struct pci_child_platdata { 806 int devfn; 807 unsigned short vendor; 808 unsigned short device; 809 unsigned int class; 810 }; 811 812 /* PCI bus operations */ 813 struct dm_pci_ops { 814 /** 815 * read_config() - Read a PCI configuration value 816 * 817 * PCI buses must support reading and writing configuration values 818 * so that the bus can be scanned and its devices configured. 819 * 820 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. 821 * If bridges exist it is possible to use the top-level bus to 822 * access a sub-bus. In that case @bus will be the top-level bus 823 * and PCI_BUS(bdf) will be a different (higher) value 824 * 825 * @bus: Bus to read from 826 * @bdf: Bus, device and function to read 827 * @offset: Byte offset within the device's configuration space 828 * @valuep: Place to put the returned value 829 * @size: Access size 830 * @return 0 if OK, -ve on error 831 */ 832 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 833 ulong *valuep, enum pci_size_t size); 834 /** 835 * write_config() - Write a PCI configuration value 836 * 837 * @bus: Bus to write to 838 * @bdf: Bus, device and function to write 839 * @offset: Byte offset within the device's configuration space 840 * @value: Value to write 841 * @size: Access size 842 * @return 0 if OK, -ve on error 843 */ 844 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 845 ulong value, enum pci_size_t size); 846 }; 847 848 /* Get access to a PCI bus' operations */ 849 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) 850 851 /** 852 * pci_get_bdf() - Get the BDF value for a device 853 * 854 * @dev: Device to check 855 * @return bus/device/function value (see PCI_BDF()) 856 */ 857 pci_dev_t pci_get_bdf(struct udevice *dev); 858 859 /** 860 * pci_bind_bus_devices() - scan a PCI bus and bind devices 861 * 862 * Scan a PCI bus looking for devices. Bind each one that is found. If 863 * devices are already bound that match the scanned devices, just update the 864 * child data so that the device can be used correctly (this happens when 865 * the device tree describes devices we expect to see on the bus). 866 * 867 * Devices that are bound in this way will use a generic PCI driver which 868 * does nothing. The device can still be accessed but will not provide any 869 * driver interface. 870 * 871 * @bus: Bus containing devices to bind 872 * @return 0 if OK, -ve on error 873 */ 874 int pci_bind_bus_devices(struct udevice *bus); 875 876 /** 877 * pci_auto_config_devices() - configure bus devices ready for use 878 * 879 * This works through all devices on a bus by scanning the driver model 880 * data structures (normally these have been set up by pci_bind_bus_devices() 881 * earlier). 882 * 883 * Space is allocated for each PCI base address register (BAR) so that the 884 * devices are mapped into memory and I/O space ready for use. 885 * 886 * @bus: Bus containing devices to bind 887 * @return 0 if OK, -ve on error 888 */ 889 int pci_auto_config_devices(struct udevice *bus); 890 891 /** 892 * pci_bus_find_bdf() - Find a device given its PCI bus address 893 * 894 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 895 * @devp: Returns the device for this address, if found 896 * @return 0 if OK, -ENODEV if not found 897 */ 898 int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); 899 900 /** 901 * pci_bus_find_devfn() - Find a device on a bus 902 * 903 * @find_devfn: PCI device address (device and function only) 904 * @devp: Returns the device for this address, if found 905 * @return 0 if OK, -ENODEV if not found 906 */ 907 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 908 struct udevice **devp); 909 910 /** 911 * pci_get_ff() - Returns a mask for the given access size 912 * 913 * @size: Access size 914 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for 915 * PCI_SIZE_32 916 */ 917 int pci_get_ff(enum pci_size_t size); 918 919 /** 920 * pci_bus_find_devices () - Find devices on a bus 921 * 922 * @bus: Bus to search 923 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 924 * @indexp: Pointer to device index to find. To find the first matching 925 * device, pass 0; to find the second, pass 1, etc. This 926 * parameter is decremented for each non-matching device so 927 * can be called repeatedly. 928 * @devp: Returns matching device if found 929 * @return 0 if found, -ENODEV if not 930 */ 931 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 932 int *indexp, struct udevice **devp); 933 934 /** 935 * pci_find_device_id() - Find a device on any bus 936 * 937 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 938 * @index: Index number of device to find, 0 for the first match, 1 for 939 * the second, etc. 940 * @devp: Returns matching device if found 941 * @return 0 if found, -ENODEV if not 942 */ 943 int pci_find_device_id(struct pci_device_id *ids, int index, 944 struct udevice **devp); 945 946 /** 947 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices 948 * 949 * This probes the given bus which causes it to be scanned for devices. The 950 * devices will be bound but not probed. 951 * 952 * @hose specifies the PCI hose that will be used for the scan. This is 953 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is 954 * in @bdf, and is a subordinate bus reachable from @hose. 955 * 956 * @hose: PCI hose to scan 957 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) 958 * @return 0 if OK, -ve on error 959 */ 960 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf); 961 962 /** 963 * pci_bus_read_config() - Read a configuration value from a device 964 * 965 * TODO(sjg@chromium.org): We should be able to pass just a device and have 966 * it do the right thing. It would be good to have that function also. 967 * 968 * @bus: Bus to read from 969 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 970 * @valuep: Place to put the returned value 971 * @size: Access size 972 * @return 0 if OK, -ve on error 973 */ 974 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 975 unsigned long *valuep, enum pci_size_t size); 976 977 /** 978 * pci_bus_write_config() - Write a configuration value to a device 979 * 980 * @bus: Bus to write from 981 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 982 * @value: Value to write 983 * @size: Access size 984 * @return 0 if OK, -ve on error 985 */ 986 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 987 unsigned long value, enum pci_size_t size); 988 989 /* 990 * The following functions provide access to the above without needing the 991 * size parameter. We are trying to encourage the use of the 8/16/32-style 992 * functions, rather than byte/word/dword. But both are supported. 993 */ 994 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); 995 996 /* Compatibility with old naming */ 997 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, 998 u32 value) 999 { 1000 return pci_write_config32(pcidev, offset, value); 1001 } 1002 1003 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); 1004 1005 /* Compatibility with old naming */ 1006 static inline int pci_write_config_word(pci_dev_t pcidev, int offset, 1007 u16 value) 1008 { 1009 return pci_write_config16(pcidev, offset, value); 1010 } 1011 1012 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); 1013 1014 /* Compatibility with old naming */ 1015 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, 1016 u8 value) 1017 { 1018 return pci_write_config8(pcidev, offset, value); 1019 } 1020 1021 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); 1022 1023 /* Compatibility with old naming */ 1024 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, 1025 u32 *valuep) 1026 { 1027 return pci_read_config32(pcidev, offset, valuep); 1028 } 1029 1030 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); 1031 1032 /* Compatibility with old naming */ 1033 static inline int pci_read_config_word(pci_dev_t pcidev, int offset, 1034 u16 *valuep) 1035 { 1036 return pci_read_config16(pcidev, offset, valuep); 1037 } 1038 1039 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); 1040 1041 /* Compatibility with old naming */ 1042 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, 1043 u8 *valuep) 1044 { 1045 return pci_read_config8(pcidev, offset, valuep); 1046 } 1047 1048 /** 1049 * struct dm_pci_emul_ops - PCI device emulator operations 1050 */ 1051 struct dm_pci_emul_ops { 1052 /** 1053 * get_devfn(): Check which device and function this emulators 1054 * 1055 * @dev: device to check 1056 * @return the device and function this emulates, or -ve on error 1057 */ 1058 int (*get_devfn)(struct udevice *dev); 1059 /** 1060 * read_config() - Read a PCI configuration value 1061 * 1062 * @dev: Emulated device to read from 1063 * @offset: Byte offset within the device's configuration space 1064 * @valuep: Place to put the returned value 1065 * @size: Access size 1066 * @return 0 if OK, -ve on error 1067 */ 1068 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep, 1069 enum pci_size_t size); 1070 /** 1071 * write_config() - Write a PCI configuration value 1072 * 1073 * @dev: Emulated device to write to 1074 * @offset: Byte offset within the device's configuration space 1075 * @value: Value to write 1076 * @size: Access size 1077 * @return 0 if OK, -ve on error 1078 */ 1079 int (*write_config)(struct udevice *dev, uint offset, ulong value, 1080 enum pci_size_t size); 1081 /** 1082 * read_io() - Read a PCI I/O value 1083 * 1084 * @dev: Emulated device to read from 1085 * @addr: I/O address to read 1086 * @valuep: Place to put the returned value 1087 * @size: Access size 1088 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1089 * other -ve value on error 1090 */ 1091 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, 1092 enum pci_size_t size); 1093 /** 1094 * write_io() - Write a PCI I/O value 1095 * 1096 * @dev: Emulated device to write from 1097 * @addr: I/O address to write 1098 * @value: Value to write 1099 * @size: Access size 1100 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1101 * other -ve value on error 1102 */ 1103 int (*write_io)(struct udevice *dev, unsigned int addr, 1104 ulong value, enum pci_size_t size); 1105 /** 1106 * map_physmem() - Map a device into sandbox memory 1107 * 1108 * @dev: Emulated device to map 1109 * @addr: Memory address, normally corresponding to a PCI BAR. 1110 * The device should have been configured to have a BAR 1111 * at this address. 1112 * @lenp: On entry, the size of the area to map, On exit it is 1113 * updated to the size actually mapped, which may be less 1114 * if the device has less space 1115 * @ptrp: Returns a pointer to the mapped address. The device's 1116 * space can be accessed as @lenp bytes starting here 1117 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1118 * other -ve value on error 1119 */ 1120 int (*map_physmem)(struct udevice *dev, phys_addr_t addr, 1121 unsigned long *lenp, void **ptrp); 1122 /** 1123 * unmap_physmem() - undo a memory mapping 1124 * 1125 * This must be called after map_physmem() to undo the mapping. 1126 * Some devices can use this to check what has been written into 1127 * their mapped memory and perform an operations they require on it. 1128 * In this way, map/unmap can be used as a sort of handshake between 1129 * the emulated device and its users. 1130 * 1131 * @dev: Emuated device to unmap 1132 * @vaddr: Mapped memory address, as passed to map_physmem() 1133 * @len: Size of area mapped, as returned by map_physmem() 1134 * @return 0 if OK, -ve on error 1135 */ 1136 int (*unmap_physmem)(struct udevice *dev, const void *vaddr, 1137 unsigned long len); 1138 }; 1139 1140 /* Get access to a PCI device emulator's operations */ 1141 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) 1142 1143 /** 1144 * sandbox_pci_get_emul() - Get the emulation device for a PCI device 1145 * 1146 * Searches for a suitable emulator for the given PCI bus device 1147 * 1148 * @bus: PCI bus to search 1149 * @find_devfn: PCI device and function address (PCI_DEVFN()) 1150 * @emulp: Returns emulated device if found 1151 * @return 0 if found, -ENODEV if not found 1152 */ 1153 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, 1154 struct udevice **emulp); 1155 1156 #endif /* CONFIG_DM_PCI */ 1157 1158 /** 1159 * PCI_DEVICE - macro used to describe a specific pci device 1160 * @vend: the 16 bit PCI Vendor ID 1161 * @dev: the 16 bit PCI Device ID 1162 * 1163 * This macro is used to create a struct pci_device_id that matches a 1164 * specific device. The subvendor and subdevice fields will be set to 1165 * PCI_ANY_ID. 1166 */ 1167 #define PCI_DEVICE(vend, dev) \ 1168 .vendor = (vend), .device = (dev), \ 1169 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1170 1171 /** 1172 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 1173 * @vend: the 16 bit PCI Vendor ID 1174 * @dev: the 16 bit PCI Device ID 1175 * @subvend: the 16 bit PCI Subvendor ID 1176 * @subdev: the 16 bit PCI Subdevice ID 1177 * 1178 * This macro is used to create a struct pci_device_id that matches a 1179 * specific device with subsystem information. 1180 */ 1181 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1182 .vendor = (vend), .device = (dev), \ 1183 .subvendor = (subvend), .subdevice = (subdev) 1184 1185 /** 1186 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 1187 * @dev_class: the class, subclass, prog-if triple for this device 1188 * @dev_class_mask: the class mask for this device 1189 * 1190 * This macro is used to create a struct pci_device_id that matches a 1191 * specific PCI class. The vendor, device, subvendor, and subdevice 1192 * fields will be set to PCI_ANY_ID. 1193 */ 1194 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ 1195 .class = (dev_class), .class_mask = (dev_class_mask), \ 1196 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1197 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1198 1199 /** 1200 * PCI_VDEVICE - macro used to describe a specific pci device in short form 1201 * @vend: the vendor name 1202 * @dev: the 16 bit PCI Device ID 1203 * 1204 * This macro is used to create a struct pci_device_id that matches a 1205 * specific PCI device. The subvendor, and subdevice fields will be set 1206 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1207 * private data. 1208 */ 1209 1210 #define PCI_VDEVICE(vend, dev) \ 1211 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1212 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1213 1214 /** 1215 * struct pci_driver_entry - Matches a driver to its pci_device_id list 1216 * @driver: Driver to use 1217 * @match: List of match records for this driver, terminated by {} 1218 */ 1219 struct pci_driver_entry { 1220 struct driver *driver; 1221 const struct pci_device_id *match; 1222 }; 1223 1224 #define U_BOOT_PCI_DEVICE(__name, __match) \ 1225 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\ 1226 .driver = llsym(struct driver, __name, driver), \ 1227 .match = __match, \ 1228 } 1229 1230 #endif /* __ASSEMBLY__ */ 1231 #endif /* _PCI_H */ 1232