xref: /openbmc/u-boot/include/pci.h (revision 70c56c138f3776b68f24acb09a9bc3ba67855d0a)
1  /*
2   * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3   * Andreas Heppel <aheppel@sysgo.de>
4   *
5   * (C) Copyright 2002
6   * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7   *
8   * SPDX-License-Identifier:	GPL-2.0+
9   */
10  
11  #ifndef _PCI_H
12  #define _PCI_H
13  
14  #define PCI_CFG_SPACE_SIZE	256
15  #define PCI_CFG_SPACE_EXP_SIZE	4096
16  
17  /*
18   * Under PCI, each device has 256 bytes of configuration address space,
19   * of which the first 64 bytes are standardized as follows:
20   */
21  #define PCI_VENDOR_ID		0x00	/* 16 bits */
22  #define PCI_DEVICE_ID		0x02	/* 16 bits */
23  #define PCI_COMMAND		0x04	/* 16 bits */
24  #define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
25  #define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
26  #define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
27  #define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
28  #define  PCI_COMMAND_INVALIDATE 0x10	/* Use memory write and invalidate */
29  #define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
30  #define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
31  #define  PCI_COMMAND_WAIT	0x80	/* Enable address/data stepping */
32  #define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
33  #define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
34  
35  #define PCI_STATUS		0x06	/* 16 bits */
36  #define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
37  #define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
38  #define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
39  #define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
40  #define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
41  #define  PCI_STATUS_DEVSEL_MASK 0x600	/* DEVSEL timing */
42  #define  PCI_STATUS_DEVSEL_FAST 0x000
43  #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
44  #define  PCI_STATUS_DEVSEL_SLOW 0x400
45  #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
46  #define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
47  #define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
48  #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
49  #define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
50  
51  #define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
52  					   revision */
53  #define PCI_REVISION_ID		0x08	/* Revision ID */
54  #define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
55  #define PCI_CLASS_DEVICE	0x0a	/* Device class */
56  #define PCI_CLASS_CODE		0x0b	/* Device class code */
57  #define  PCI_CLASS_CODE_TOO_OLD	0x00
58  #define  PCI_CLASS_CODE_STORAGE 0x01
59  #define  PCI_CLASS_CODE_NETWORK 0x02
60  #define  PCI_CLASS_CODE_DISPLAY	0x03
61  #define  PCI_CLASS_CODE_MULTIMEDIA 0x04
62  #define  PCI_CLASS_CODE_MEMORY	0x05
63  #define  PCI_CLASS_CODE_BRIDGE	0x06
64  #define  PCI_CLASS_CODE_COMM	0x07
65  #define  PCI_CLASS_CODE_PERIPHERAL 0x08
66  #define  PCI_CLASS_CODE_INPUT	0x09
67  #define  PCI_CLASS_CODE_DOCKING	0x0A
68  #define  PCI_CLASS_CODE_PROCESSOR 0x0B
69  #define  PCI_CLASS_CODE_SERIAL	0x0C
70  #define  PCI_CLASS_CODE_WIRELESS 0x0D
71  #define  PCI_CLASS_CODE_I2O	0x0E
72  #define  PCI_CLASS_CODE_SATELLITE 0x0F
73  #define  PCI_CLASS_CODE_CRYPTO	0x10
74  #define  PCI_CLASS_CODE_DATA	0x11
75  /* Base Class 0x12 - 0xFE is reserved */
76  #define  PCI_CLASS_CODE_OTHER	0xFF
77  
78  #define PCI_CLASS_SUB_CODE	0x0a	/* Device sub-class code */
79  #define  PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA	0x00
80  #define  PCI_CLASS_SUB_CODE_TOO_OLD_VGA		0x01
81  #define  PCI_CLASS_SUB_CODE_STORAGE_SCSI	0x00
82  #define  PCI_CLASS_SUB_CODE_STORAGE_IDE		0x01
83  #define  PCI_CLASS_SUB_CODE_STORAGE_FLOPPY	0x02
84  #define  PCI_CLASS_SUB_CODE_STORAGE_IPIBUS	0x03
85  #define  PCI_CLASS_SUB_CODE_STORAGE_RAID	0x04
86  #define  PCI_CLASS_SUB_CODE_STORAGE_ATA		0x05
87  #define  PCI_CLASS_SUB_CODE_STORAGE_SATA	0x06
88  #define  PCI_CLASS_SUB_CODE_STORAGE_SAS		0x07
89  #define  PCI_CLASS_SUB_CODE_STORAGE_OTHER	0x80
90  #define  PCI_CLASS_SUB_CODE_NETWORK_ETHERNET	0x00
91  #define  PCI_CLASS_SUB_CODE_NETWORK_TOKENRING	0x01
92  #define  PCI_CLASS_SUB_CODE_NETWORK_FDDI	0x02
93  #define  PCI_CLASS_SUB_CODE_NETWORK_ATM		0x03
94  #define  PCI_CLASS_SUB_CODE_NETWORK_ISDN	0x04
95  #define  PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP	0x05
96  #define  PCI_CLASS_SUB_CODE_NETWORK_PICMG	0x06
97  #define  PCI_CLASS_SUB_CODE_NETWORK_OTHER	0x80
98  #define  PCI_CLASS_SUB_CODE_DISPLAY_VGA		0x00
99  #define  PCI_CLASS_SUB_CODE_DISPLAY_XGA		0x01
100  #define  PCI_CLASS_SUB_CODE_DISPLAY_3D		0x02
101  #define  PCI_CLASS_SUB_CODE_DISPLAY_OTHER	0x80
102  #define  PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO	0x00
103  #define  PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO	0x01
104  #define  PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE	0x02
105  #define  PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER	0x80
106  #define  PCI_CLASS_SUB_CODE_MEMORY_RAM		0x00
107  #define  PCI_CLASS_SUB_CODE_MEMORY_FLASH	0x01
108  #define  PCI_CLASS_SUB_CODE_MEMORY_OTHER	0x80
109  #define  PCI_CLASS_SUB_CODE_BRIDGE_HOST		0x00
110  #define  PCI_CLASS_SUB_CODE_BRIDGE_ISA		0x01
111  #define  PCI_CLASS_SUB_CODE_BRIDGE_EISA		0x02
112  #define  PCI_CLASS_SUB_CODE_BRIDGE_MCA		0x03
113  #define  PCI_CLASS_SUB_CODE_BRIDGE_PCI		0x04
114  #define  PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA	0x05
115  #define  PCI_CLASS_SUB_CODE_BRIDGE_NUBUS	0x06
116  #define  PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS	0x07
117  #define  PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY	0x08
118  #define  PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI	0x09
119  #define  PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND	0x0A
120  #define  PCI_CLASS_SUB_CODE_BRIDGE_OTHER	0x80
121  #define  PCI_CLASS_SUB_CODE_COMM_SERIAL		0x00
122  #define  PCI_CLASS_SUB_CODE_COMM_PARALLEL	0x01
123  #define  PCI_CLASS_SUB_CODE_COMM_MULTIPORT	0x02
124  #define  PCI_CLASS_SUB_CODE_COMM_MODEM		0x03
125  #define  PCI_CLASS_SUB_CODE_COMM_GPIB		0x04
126  #define  PCI_CLASS_SUB_CODE_COMM_SMARTCARD	0x05
127  #define  PCI_CLASS_SUB_CODE_COMM_OTHER		0x80
128  #define  PCI_CLASS_SUB_CODE_PERIPHERAL_PIC	0x00
129  #define  PCI_CLASS_SUB_CODE_PERIPHERAL_DMA	0x01
130  #define  PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER	0x02
131  #define  PCI_CLASS_SUB_CODE_PERIPHERAL_RTC	0x03
132  #define  PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG	0x04
133  #define  PCI_CLASS_SUB_CODE_PERIPHERAL_SD	0x05
134  #define  PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER	0x80
135  #define  PCI_CLASS_SUB_CODE_INPUT_KEYBOARD	0x00
136  #define  PCI_CLASS_SUB_CODE_INPUT_DIGITIZER	0x01
137  #define  PCI_CLASS_SUB_CODE_INPUT_MOUSE		0x02
138  #define  PCI_CLASS_SUB_CODE_INPUT_SCANNER	0x03
139  #define  PCI_CLASS_SUB_CODE_INPUT_GAMEPORT	0x04
140  #define  PCI_CLASS_SUB_CODE_INPUT_OTHER		0x80
141  #define  PCI_CLASS_SUB_CODE_DOCKING_GENERIC	0x00
142  #define  PCI_CLASS_SUB_CODE_DOCKING_OTHER	0x80
143  #define  PCI_CLASS_SUB_CODE_PROCESSOR_386	0x00
144  #define  PCI_CLASS_SUB_CODE_PROCESSOR_486	0x01
145  #define  PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM	0x02
146  #define  PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA	0x10
147  #define  PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC	0x20
148  #define  PCI_CLASS_SUB_CODE_PROCESSOR_MIPS	0x30
149  #define  PCI_CLASS_SUB_CODE_PROCESSOR_COPROC	0x40
150  #define  PCI_CLASS_SUB_CODE_SERIAL_1394		0x00
151  #define  PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS	0x01
152  #define  PCI_CLASS_SUB_CODE_SERIAL_SSA		0x02
153  #define  PCI_CLASS_SUB_CODE_SERIAL_USB		0x03
154  #define  PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN	0x04
155  #define  PCI_CLASS_SUB_CODE_SERIAL_SMBUS	0x05
156  #define  PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND	0x06
157  #define  PCI_CLASS_SUB_CODE_SERIAL_IPMI		0x07
158  #define  PCI_CLASS_SUB_CODE_SERIAL_SERCOS	0x08
159  #define  PCI_CLASS_SUB_CODE_SERIAL_CANBUS	0x09
160  #define  PCI_CLASS_SUB_CODE_WIRELESS_IRDA	0x00
161  #define  PCI_CLASS_SUB_CODE_WIRELESS_IR		0x01
162  #define  PCI_CLASS_SUB_CODE_WIRELESS_RF		0x10
163  #define  PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH	0x11
164  #define  PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND	0x12
165  #define  PCI_CLASS_SUB_CODE_WIRELESS_80211A	0x20
166  #define  PCI_CLASS_SUB_CODE_WIRELESS_80211B	0x21
167  #define  PCI_CLASS_SUB_CODE_WIRELESS_OTHER	0x80
168  #define  PCI_CLASS_SUB_CODE_I2O_V1_0		0x00
169  #define  PCI_CLASS_SUB_CODE_SATELLITE_TV	0x01
170  #define  PCI_CLASS_SUB_CODE_SATELLITE_AUDIO	0x02
171  #define  PCI_CLASS_SUB_CODE_SATELLITE_VOICE	0x03
172  #define  PCI_CLASS_SUB_CODE_SATELLITE_DATA	0x04
173  #define  PCI_CLASS_SUB_CODE_CRYPTO_NETWORK	0x00
174  #define  PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
175  #define  PCI_CLASS_SUB_CODE_CRYPTO_OTHER	0x80
176  #define  PCI_CLASS_SUB_CODE_DATA_DPIO		0x00
177  #define  PCI_CLASS_SUB_CODE_DATA_PERFCNTR	0x01
178  #define  PCI_CLASS_SUB_CODE_DATA_COMMSYNC	0x10
179  #define  PCI_CLASS_SUB_CODE_DATA_MGMT		0x20
180  #define  PCI_CLASS_SUB_CODE_DATA_OTHER		0x80
181  
182  #define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
183  #define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
184  #define PCI_HEADER_TYPE		0x0e	/* 8 bits */
185  #define  PCI_HEADER_TYPE_NORMAL 0
186  #define  PCI_HEADER_TYPE_BRIDGE 1
187  #define  PCI_HEADER_TYPE_CARDBUS 2
188  
189  #define PCI_BIST		0x0f	/* 8 bits */
190  #define PCI_BIST_CODE_MASK	0x0f	/* Return result */
191  #define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
192  #define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
193  
194  /*
195   * Base addresses specify locations in memory or I/O space.
196   * Decoded size can be determined by writing a value of
197   * 0xffffffff to the register, and reading it back.  Only
198   * 1 bits are decoded.
199   */
200  #define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
201  #define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
202  #define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
203  #define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
204  #define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
205  #define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
206  #define  PCI_BASE_ADDRESS_SPACE 0x01	/* 0 = memory, 1 = I/O */
207  #define  PCI_BASE_ADDRESS_SPACE_IO 0x01
208  #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
209  #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
210  #define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
211  #define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
212  #define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
213  #define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
214  #define  PCI_BASE_ADDRESS_MEM_MASK	(~0x0fULL)
215  #define  PCI_BASE_ADDRESS_IO_MASK	(~0x03ULL)
216  /* bit 1 is reserved if address_space = 1 */
217  
218  /* Header type 0 (normal devices) */
219  #define PCI_CARDBUS_CIS		0x28
220  #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
221  #define PCI_SUBSYSTEM_ID	0x2e
222  #define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
223  #define  PCI_ROM_ADDRESS_ENABLE 0x01
224  #define PCI_ROM_ADDRESS_MASK	(~0x7ffULL)
225  
226  #define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
227  
228  /* 0x35-0x3b are reserved */
229  #define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
230  #define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
231  #define PCI_MIN_GNT		0x3e	/* 8 bits */
232  #define PCI_MAX_LAT		0x3f	/* 8 bits */
233  
234  #define PCI_INTERRUPT_LINE_DISABLE	0xff
235  
236  /* Header type 1 (PCI-to-PCI bridges) */
237  #define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
238  #define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
239  #define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
240  #define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
241  #define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
242  #define PCI_IO_LIMIT		0x1d
243  #define  PCI_IO_RANGE_TYPE_MASK 0x0f	/* I/O bridging type */
244  #define  PCI_IO_RANGE_TYPE_16	0x00
245  #define  PCI_IO_RANGE_TYPE_32	0x01
246  #define  PCI_IO_RANGE_MASK	~0x0f
247  #define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
248  #define PCI_MEMORY_BASE		0x20	/* Memory range behind */
249  #define PCI_MEMORY_LIMIT	0x22
250  #define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
251  #define  PCI_MEMORY_RANGE_MASK	~0x0f
252  #define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
253  #define PCI_PREF_MEMORY_LIMIT	0x26
254  #define  PCI_PREF_RANGE_TYPE_MASK 0x0f
255  #define  PCI_PREF_RANGE_TYPE_32 0x00
256  #define  PCI_PREF_RANGE_TYPE_64 0x01
257  #define  PCI_PREF_RANGE_MASK	~0x0f
258  #define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
259  #define PCI_PREF_LIMIT_UPPER32	0x2c
260  #define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
261  #define PCI_IO_LIMIT_UPPER16	0x32
262  /* 0x34 same as for htype 0 */
263  /* 0x35-0x3b is reserved */
264  #define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
265  /* 0x3c-0x3d are same as for htype 0 */
266  #define PCI_BRIDGE_CONTROL	0x3e
267  #define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
268  #define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
269  #define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
270  #define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
271  #define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
272  #define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
273  #define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
274  
275  /* From 440ep */
276  #define PCI_ERREN       0x48     /* Error Enable */
277  #define PCI_ERRSTS      0x49     /* Error Status */
278  #define PCI_BRDGOPT1    0x4A     /* PCI Bridge Options 1 */
279  #define PCI_PLBSESR0    0x4C     /* PCI PLB Slave Error Syndrome 0 */
280  #define PCI_PLBSESR1    0x50     /* PCI PLB Slave Error Syndrome 1 */
281  #define PCI_PLBSEAR     0x54     /* PCI PLB Slave Error Address */
282  #define PCI_CAPID       0x58     /* Capability Identifier */
283  #define PCI_NEXTITEMPTR 0x59     /* Next Item Pointer */
284  #define PCI_PMC         0x5A     /* Power Management Capabilities */
285  #define PCI_PMCSR       0x5C     /* Power Management Control Status */
286  #define PCI_PMCSRBSE    0x5E     /* PMCSR PCI to PCI Bridge Support Extensions */
287  #define PCI_BRDGOPT2    0x60     /* PCI Bridge Options 2 */
288  #define PCI_PMSCRR      0x64     /* Power Management State Change Request Re. */
289  
290  /* Header type 2 (CardBus bridges) */
291  #define PCI_CB_CAPABILITY_LIST	0x14
292  /* 0x15 reserved */
293  #define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
294  #define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
295  #define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
296  #define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
297  #define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
298  #define PCI_CB_MEMORY_BASE_0	0x1c
299  #define PCI_CB_MEMORY_LIMIT_0	0x20
300  #define PCI_CB_MEMORY_BASE_1	0x24
301  #define PCI_CB_MEMORY_LIMIT_1	0x28
302  #define PCI_CB_IO_BASE_0	0x2c
303  #define PCI_CB_IO_BASE_0_HI	0x2e
304  #define PCI_CB_IO_LIMIT_0	0x30
305  #define PCI_CB_IO_LIMIT_0_HI	0x32
306  #define PCI_CB_IO_BASE_1	0x34
307  #define PCI_CB_IO_BASE_1_HI	0x36
308  #define PCI_CB_IO_LIMIT_1	0x38
309  #define PCI_CB_IO_LIMIT_1_HI	0x3a
310  #define  PCI_CB_IO_RANGE_MASK	~0x03
311  /* 0x3c-0x3d are same as for htype 0 */
312  #define PCI_CB_BRIDGE_CONTROL	0x3e
313  #define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
314  #define  PCI_CB_BRIDGE_CTL_SERR		0x02
315  #define  PCI_CB_BRIDGE_CTL_ISA		0x04
316  #define  PCI_CB_BRIDGE_CTL_VGA		0x08
317  #define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
318  #define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
319  #define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
320  #define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
321  #define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
322  #define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
323  #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
324  #define PCI_CB_SUBSYSTEM_ID	0x42
325  #define PCI_CB_LEGACY_MODE_BASE 0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
326  /* 0x48-0x7f reserved */
327  
328  /* Capability lists */
329  
330  #define PCI_CAP_LIST_ID		0	/* Capability ID */
331  #define  PCI_CAP_ID_PM		0x01	/* Power Management */
332  #define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
333  #define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
334  #define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
335  #define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
336  #define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
337  #define  PCI_CAP_ID_EXP 	0x10	/* PCI Express */
338  #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
339  #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
340  #define PCI_CAP_SIZEOF		4
341  
342  /* Power Management Registers */
343  
344  #define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
345  #define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
346  #define  PCI_PM_CAP_AUX_POWER	0x0010	/* Auxilliary power support */
347  #define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
348  #define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
349  #define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
350  #define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
351  #define PCI_PM_CTRL		4	/* PM control and status register */
352  #define  PCI_PM_CTRL_STATE_MASK 0x0003	/* Current power state (D0 to D3) */
353  #define  PCI_PM_CTRL_PME_ENABLE 0x0100	/* PME pin enable */
354  #define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
355  #define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
356  #define  PCI_PM_CTRL_PME_STATUS 0x8000	/* PME pin status */
357  #define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
358  #define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
359  #define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
360  #define PCI_PM_DATA_REGISTER	7	/* (??) */
361  #define PCI_PM_SIZEOF		8
362  
363  /* AGP registers */
364  
365  #define PCI_AGP_VERSION		2	/* BCD version number */
366  #define PCI_AGP_RFU		3	/* Rest of capability flags */
367  #define PCI_AGP_STATUS		4	/* Status register */
368  #define  PCI_AGP_STATUS_RQ_MASK 0xff000000	/* Maximum number of requests - 1 */
369  #define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
370  #define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
371  #define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
372  #define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
373  #define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
374  #define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
375  #define PCI_AGP_COMMAND		8	/* Control register */
376  #define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
377  #define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
378  #define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
379  #define  PCI_AGP_COMMAND_64BIT	0x0020	/* Allow processing of 64-bit addresses */
380  #define  PCI_AGP_COMMAND_FW	0x0010	/* Force FW transfers */
381  #define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
382  #define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 4x rate */
383  #define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 4x rate */
384  #define PCI_AGP_SIZEOF		12
385  
386  /* PCI-X registers */
387  
388  #define  PCI_X_CMD_DPERR_E      0x0001  /* Data Parity Error Recovery Enable */
389  #define  PCI_X_CMD_ERO          0x0002  /* Enable Relaxed Ordering */
390  #define  PCI_X_CMD_MAX_READ     0x0000  /* Max Memory Read Byte Count */
391  #define  PCI_X_CMD_MAX_SPLIT    0x0030  /* Max Outstanding Split Transactions */
392  #define  PCI_X_CMD_VERSION(x)   (((x) >> 12) & 3) /* Version */
393  
394  
395  /* Slot Identification */
396  
397  #define PCI_SID_ESR		2	/* Expansion Slot Register */
398  #define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
399  #define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
400  #define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
401  
402  /* Message Signalled Interrupts registers */
403  
404  #define PCI_MSI_FLAGS		2	/* Various flags */
405  #define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
406  #define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
407  #define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
408  #define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
409  #define PCI_MSI_RFU		3	/* Rest of capability flags */
410  #define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
411  #define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
412  #define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
413  #define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
414  
415  #define PCI_MAX_PCI_DEVICES	32
416  #define PCI_MAX_PCI_FUNCTIONS	8
417  
418  #define PCI_FIND_CAP_TTL 0x48
419  #define CAP_START_POS 0x40
420  
421  /* Extended Capabilities (PCI-X 2.0 and Express) */
422  #define PCI_EXT_CAP_ID(header)		(header & 0x0000ffff)
423  #define PCI_EXT_CAP_VER(header)		((header >> 16) & 0xf)
424  #define PCI_EXT_CAP_NEXT(header)	((header >> 20) & 0xffc)
425  
426  #define PCI_EXT_CAP_ID_ERR	0x01	/* Advanced Error Reporting */
427  #define PCI_EXT_CAP_ID_VC	0x02	/* Virtual Channel Capability */
428  #define PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
429  #define PCI_EXT_CAP_ID_PWR	0x04	/* Power Budgeting */
430  #define PCI_EXT_CAP_ID_RCLD	0x05	/* Root Complex Link Declaration */
431  #define PCI_EXT_CAP_ID_RCILC	0x06	/* Root Complex Internal Link Control */
432  #define PCI_EXT_CAP_ID_RCEC	0x07	/* Root Complex Event Collector */
433  #define PCI_EXT_CAP_ID_MFVC	0x08	/* Multi-Function VC Capability */
434  #define PCI_EXT_CAP_ID_VC9	0x09	/* same as _VC */
435  #define PCI_EXT_CAP_ID_RCRB	0x0A	/* Root Complex RB? */
436  #define PCI_EXT_CAP_ID_VNDR	0x0B	/* Vendor-Specific */
437  #define PCI_EXT_CAP_ID_CAC	0x0C	/* Config Access - obsolete */
438  #define PCI_EXT_CAP_ID_ACS	0x0D	/* Access Control Services */
439  #define PCI_EXT_CAP_ID_ARI	0x0E	/* Alternate Routing ID */
440  #define PCI_EXT_CAP_ID_ATS	0x0F	/* Address Translation Services */
441  #define PCI_EXT_CAP_ID_SRIOV	0x10	/* Single Root I/O Virtualization */
442  #define PCI_EXT_CAP_ID_MRIOV	0x11	/* Multi Root I/O Virtualization */
443  #define PCI_EXT_CAP_ID_MCAST	0x12	/* Multicast */
444  #define PCI_EXT_CAP_ID_PRI	0x13	/* Page Request Interface */
445  #define PCI_EXT_CAP_ID_AMD_XXX	0x14	/* Reserved for AMD */
446  #define PCI_EXT_CAP_ID_REBAR	0x15	/* Resizable BAR */
447  #define PCI_EXT_CAP_ID_DPA	0x16	/* Dynamic Power Allocation */
448  #define PCI_EXT_CAP_ID_TPH	0x17	/* TPH Requester */
449  #define PCI_EXT_CAP_ID_LTR	0x18	/* Latency Tolerance Reporting */
450  #define PCI_EXT_CAP_ID_SECPCI	0x19	/* Secondary PCIe Capability */
451  #define PCI_EXT_CAP_ID_PMUX	0x1A	/* Protocol Multiplexing */
452  #define PCI_EXT_CAP_ID_PASID	0x1B	/* Process Address Space ID */
453  
454  /* Include the ID list */
455  
456  #include <pci_ids.h>
457  
458  #ifndef __ASSEMBLY__
459  
460  #ifdef CONFIG_SYS_PCI_64BIT
461  typedef u64 pci_addr_t;
462  typedef u64 pci_size_t;
463  #else
464  typedef u32 pci_addr_t;
465  typedef u32 pci_size_t;
466  #endif
467  
468  struct pci_region {
469  	pci_addr_t bus_start;	/* Start on the bus */
470  	phys_addr_t phys_start;	/* Start in physical address space */
471  	pci_size_t size;	/* Size */
472  	unsigned long flags;	/* Resource flags */
473  
474  	pci_addr_t bus_lower;
475  };
476  
477  #define PCI_REGION_MEM		0x00000000	/* PCI memory space */
478  #define PCI_REGION_IO		0x00000001	/* PCI IO space */
479  #define PCI_REGION_TYPE		0x00000001
480  #define PCI_REGION_PREFETCH	0x00000008	/* prefetchable PCI memory */
481  
482  #define PCI_REGION_SYS_MEMORY	0x00000100	/* System memory */
483  #define PCI_REGION_RO		0x00000200	/* Read-only memory */
484  
485  static inline void pci_set_region(struct pci_region *reg,
486  				      pci_addr_t bus_start,
487  				      phys_addr_t phys_start,
488  				      pci_size_t size,
489  				      unsigned long flags) {
490  	reg->bus_start	= bus_start;
491  	reg->phys_start = phys_start;
492  	reg->size	= size;
493  	reg->flags	= flags;
494  }
495  
496  typedef int pci_dev_t;
497  
498  #define PCI_BUS(d)		(((d) >> 16) & 0xff)
499  #define PCI_DEV(d)		(((d) >> 11) & 0x1f)
500  #define PCI_FUNC(d)		(((d) >> 8) & 0x7)
501  #define PCI_DEVFN(d, f)		((d) << 11 | (f) << 8)
502  #define PCI_MASK_BUS(bdf)	((bdf) & 0xffff)
503  #define PCI_ADD_BUS(bus, devfn)	(((bus) << 16) | (devfn))
504  #define PCI_BDF(b, d, f)	((b) << 16 | PCI_DEVFN(d, f))
505  #define PCI_VENDEV(v, d)	(((v) << 16) | (d))
506  #define PCI_ANY_ID		(~0)
507  
508  struct pci_device_id {
509  	unsigned int vendor, device;	/* Vendor and device ID or PCI_ANY_ID */
510  	unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
511  	unsigned int class, class_mask;	/* (class,subclass,prog-if) triplet */
512  	unsigned long driver_data;	/* Data private to the driver */
513  };
514  
515  struct pci_controller;
516  
517  struct pci_config_table {
518  	unsigned int vendor, device;		/* Vendor and device ID or PCI_ANY_ID */
519  	unsigned int class;			/* Class ID, or  PCI_ANY_ID */
520  	unsigned int bus;			/* Bus number, or PCI_ANY_ID */
521  	unsigned int dev;			/* Device number, or PCI_ANY_ID */
522  	unsigned int func;			/* Function number, or PCI_ANY_ID */
523  
524  	void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
525  			      struct pci_config_table *);
526  	unsigned long priv[3];
527  };
528  
529  extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
530  				   struct pci_config_table *);
531  extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
532  				      struct pci_config_table *);
533  
534  #define MAX_PCI_REGIONS		7
535  
536  #define INDIRECT_TYPE_NO_PCIE_LINK	1
537  
538  /*
539   * Structure of a PCI controller (host bridge)
540   *
541   * With driver model this is dev_get_uclass_priv(bus)
542   */
543  struct pci_controller {
544  #ifdef CONFIG_DM_PCI
545  	struct udevice *bus;
546  	struct udevice *ctlr;
547  #else
548  	struct pci_controller *next;
549  #endif
550  
551  	int first_busno;
552  	int last_busno;
553  
554  	volatile unsigned int *cfg_addr;
555  	volatile unsigned char *cfg_data;
556  
557  	int indirect_type;
558  
559  	/*
560  	 * TODO(sjg@chromium.org): With driver model we use struct
561  	 * pci_controller for both the controller and any bridge devices
562  	 * attached to it. But there is only one region list and it is in the
563  	 * top-level controller.
564  	 *
565  	 * This could be changed so that struct pci_controller is only used
566  	 * for PCI controllers and a separate UCLASS (or perhaps
567  	 * UCLASS_PCI_GENERIC) is used for bridges.
568  	 */
569  	struct pci_region regions[MAX_PCI_REGIONS];
570  	int region_count;
571  
572  	struct pci_config_table *config_table;
573  
574  	void (*fixup_irq)(struct pci_controller *, pci_dev_t);
575  #ifndef CONFIG_DM_PCI
576  	/* Low-level architecture-dependent routines */
577  	int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
578  	int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
579  	int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
580  	int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
581  	int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
582  	int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
583  #endif
584  
585  	/* Used by auto config */
586  	struct pci_region *pci_mem, *pci_io, *pci_prefetch;
587  
588  	/* Used by ppc405 autoconfig*/
589  	struct pci_region *pci_fb;
590  #ifndef CONFIG_DM_PCI
591  	int current_busno;
592  
593  	void *priv_data;
594  #endif
595  };
596  
597  #ifndef CONFIG_DM_PCI
598  static inline void pci_set_ops(struct pci_controller *hose,
599  				   int (*read_byte)(struct pci_controller*,
600  						    pci_dev_t, int where, u8 *),
601  				   int (*read_word)(struct pci_controller*,
602  						    pci_dev_t, int where, u16 *),
603  				   int (*read_dword)(struct pci_controller*,
604  						     pci_dev_t, int where, u32 *),
605  				   int (*write_byte)(struct pci_controller*,
606  						     pci_dev_t, int where, u8),
607  				   int (*write_word)(struct pci_controller*,
608  						     pci_dev_t, int where, u16),
609  				   int (*write_dword)(struct pci_controller*,
610  						      pci_dev_t, int where, u32)) {
611  	hose->read_byte   = read_byte;
612  	hose->read_word   = read_word;
613  	hose->read_dword  = read_dword;
614  	hose->write_byte  = write_byte;
615  	hose->write_word  = write_word;
616  	hose->write_dword = write_dword;
617  }
618  #endif
619  
620  #ifdef CONFIG_PCI_INDIRECT_BRIDGE
621  extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
622  #endif
623  
624  #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
625  extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
626  					pci_addr_t addr, unsigned long flags);
627  extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
628  					phys_addr_t addr, unsigned long flags);
629  
630  #define pci_phys_to_bus(dev, addr, flags) \
631  	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
632  #define pci_bus_to_phys(dev, addr, flags) \
633  	pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
634  
635  #define pci_virt_to_bus(dev, addr, flags) \
636  	pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
637  			     (virt_to_phys(addr)), (flags))
638  #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
639  	map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
640  					 (addr), (flags)), \
641  		    (len), (map_flags))
642  
643  #define pci_phys_to_mem(dev, addr) \
644  	pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
645  #define pci_mem_to_phys(dev, addr) \
646  	pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
647  #define pci_phys_to_io(dev, addr)  pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
648  #define pci_io_to_phys(dev, addr)  pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
649  
650  #define pci_virt_to_mem(dev, addr) \
651  	pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
652  #define pci_mem_to_virt(dev, addr, len, map_flags) \
653  	pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
654  #define pci_virt_to_io(dev, addr) \
655  	pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
656  #define pci_io_to_virt(dev, addr, len, map_flags) \
657  	pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
658  
659  /* For driver model these are defined in macros in pci_compat.c */
660  extern int pci_hose_read_config_byte(struct pci_controller *hose,
661  				     pci_dev_t dev, int where, u8 *val);
662  extern int pci_hose_read_config_word(struct pci_controller *hose,
663  				     pci_dev_t dev, int where, u16 *val);
664  extern int pci_hose_read_config_dword(struct pci_controller *hose,
665  				      pci_dev_t dev, int where, u32 *val);
666  extern int pci_hose_write_config_byte(struct pci_controller *hose,
667  				      pci_dev_t dev, int where, u8 val);
668  extern int pci_hose_write_config_word(struct pci_controller *hose,
669  				      pci_dev_t dev, int where, u16 val);
670  extern int pci_hose_write_config_dword(struct pci_controller *hose,
671  				       pci_dev_t dev, int where, u32 val);
672  #endif
673  
674  #ifndef CONFIG_DM_PCI
675  extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
676  extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
677  extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
678  extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
679  extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
680  extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
681  #endif
682  
683  void pciauto_region_init(struct pci_region *res);
684  void pciauto_region_align(struct pci_region *res, pci_size_t size);
685  void pciauto_config_init(struct pci_controller *hose);
686  int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
687  			    pci_addr_t *bar);
688  
689  #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
690  extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
691  					       pci_dev_t dev, int where, u8 *val);
692  extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
693  					       pci_dev_t dev, int where, u16 *val);
694  extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
695  						pci_dev_t dev, int where, u8 val);
696  extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
697  						pci_dev_t dev, int where, u16 val);
698  
699  extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
700  extern void pci_register_hose(struct pci_controller* hose);
701  extern struct pci_controller* pci_bus_to_hose(int bus);
702  extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
703  extern struct pci_controller *pci_get_hose_head(void);
704  
705  extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
706  extern int pci_hose_scan(struct pci_controller *hose);
707  extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
708  
709  extern void pciauto_setup_device(struct pci_controller *hose,
710  				 pci_dev_t dev, int bars_num,
711  				 struct pci_region *mem,
712  				 struct pci_region *prefetch,
713  				 struct pci_region *io);
714  extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
715  				 pci_dev_t dev, int sub_bus);
716  extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
717  				 pci_dev_t dev, int sub_bus);
718  extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
719  
720  extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
721  extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
722  pci_dev_t pci_find_class(unsigned int find_class, int index);
723  
724  extern int pci_hose_config_device(struct pci_controller *hose,
725  				  pci_dev_t dev,
726  				  unsigned long io,
727  				  pci_addr_t mem,
728  				  unsigned long command);
729  
730  extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
731  				    int cap);
732  extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
733  				   u8 hdr_type);
734  extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
735  			int cap);
736  
737  int pci_find_next_ext_capability(struct pci_controller *hose,
738  				 pci_dev_t dev, int start, int cap);
739  int pci_hose_find_ext_capability(struct pci_controller *hose,
740  				 pci_dev_t dev, int cap);
741  
742  #ifdef CONFIG_PCI_FIXUP_DEV
743  extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
744  				unsigned short vendor,
745  				unsigned short device,
746  				unsigned short class);
747  #endif
748  #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
749  
750  const char * pci_class_str(u8 class);
751  int pci_last_busno(void);
752  
753  #ifdef CONFIG_MPC85xx
754  extern void pci_mpc85xx_init (struct pci_controller *hose);
755  #endif
756  
757  #ifdef CONFIG_PCIE_IMX
758  extern void imx_pcie_remove(void);
759  #endif
760  
761  #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
762  /**
763   * pci_write_bar32() - Write the address of a BAR including control bits
764   *
765   * This writes a raw address (with control bits) to a bar. This can be used
766   * with devices which require hard-coded addresses, not part of the normal
767   * PCI enumeration process.
768   *
769   * @hose:	PCI hose to use
770   * @dev:	PCI device to update
771   * @barnum:	BAR number (0-5)
772   * @addr:	BAR address with control bits
773   */
774  void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
775  		     u32 addr);
776  
777  /**
778   * pci_read_bar32() - read the address of a bar
779   *
780   * @hose:	PCI hose to use
781   * @dev:	PCI device to inspect
782   * @barnum:	BAR number (0-5)
783   * @return address of the bar, masking out any control bits
784   * */
785  u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
786  
787  /**
788   * pci_hose_find_devices() - Find devices by vendor/device ID
789   *
790   * @hose:	PCI hose to search
791   * @busnum:	Bus number to search
792   * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
793   * @indexp:	Pointer to device index to find. To find the first matching
794   *		device, pass 0; to find the second, pass 1, etc. This
795   *		parameter is decremented for each non-matching device so
796   *		can be called repeatedly.
797   */
798  pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
799  				struct pci_device_id *ids, int *indexp);
800  #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
801  
802  /* Access sizes for PCI reads and writes */
803  enum pci_size_t {
804  	PCI_SIZE_8,
805  	PCI_SIZE_16,
806  	PCI_SIZE_32,
807  };
808  
809  struct udevice;
810  
811  #ifdef CONFIG_DM_PCI
812  /**
813   * struct pci_child_platdata - information stored about each PCI device
814   *
815   * Every device on a PCI bus has this per-child data.
816   *
817   * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a
818   * PCI bus (i.e. UCLASS_PCI)
819   *
820   * @devfn:	Encoded device and function index - see PCI_DEVFN()
821   * @vendor:	PCI vendor ID (see pci_ids.h)
822   * @device:	PCI device ID (see pci_ids.h)
823   * @class:	PCI class, 3 bytes: (base, sub, prog-if)
824   */
825  struct pci_child_platdata {
826  	int devfn;
827  	unsigned short vendor;
828  	unsigned short device;
829  	unsigned int class;
830  };
831  
832  /* PCI bus operations */
833  struct dm_pci_ops {
834  	/**
835  	 * read_config() - Read a PCI configuration value
836  	 *
837  	 * PCI buses must support reading and writing configuration values
838  	 * so that the bus can be scanned and its devices configured.
839  	 *
840  	 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
841  	 * If bridges exist it is possible to use the top-level bus to
842  	 * access a sub-bus. In that case @bus will be the top-level bus
843  	 * and PCI_BUS(bdf) will be a different (higher) value
844  	 *
845  	 * @bus:	Bus to read from
846  	 * @bdf:	Bus, device and function to read
847  	 * @offset:	Byte offset within the device's configuration space
848  	 * @valuep:	Place to put the returned value
849  	 * @size:	Access size
850  	 * @return 0 if OK, -ve on error
851  	 */
852  	int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
853  			   ulong *valuep, enum pci_size_t size);
854  	/**
855  	 * write_config() - Write a PCI configuration value
856  	 *
857  	 * @bus:	Bus to write to
858  	 * @bdf:	Bus, device and function to write
859  	 * @offset:	Byte offset within the device's configuration space
860  	 * @value:	Value to write
861  	 * @size:	Access size
862  	 * @return 0 if OK, -ve on error
863  	 */
864  	int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
865  			    ulong value, enum pci_size_t size);
866  };
867  
868  /* Get access to a PCI bus' operations */
869  #define pci_get_ops(dev)	((struct dm_pci_ops *)(dev)->driver->ops)
870  
871  /**
872   * dm_pci_get_bdf() - Get the BDF value for a device
873   *
874   * @dev:	Device to check
875   * @return bus/device/function value (see PCI_BDF())
876   */
877  pci_dev_t dm_pci_get_bdf(struct udevice *dev);
878  
879  /**
880   * pci_bind_bus_devices() - scan a PCI bus and bind devices
881   *
882   * Scan a PCI bus looking for devices. Bind each one that is found. If
883   * devices are already bound that match the scanned devices, just update the
884   * child data so that the device can be used correctly (this happens when
885   * the device tree describes devices we expect to see on the bus).
886   *
887   * Devices that are bound in this way will use a generic PCI driver which
888   * does nothing. The device can still be accessed but will not provide any
889   * driver interface.
890   *
891   * @bus:	Bus containing devices to bind
892   * @return 0 if OK, -ve on error
893   */
894  int pci_bind_bus_devices(struct udevice *bus);
895  
896  /**
897   * pci_auto_config_devices() - configure bus devices ready for use
898   *
899   * This works through all devices on a bus by scanning the driver model
900   * data structures (normally these have been set up by pci_bind_bus_devices()
901   * earlier).
902   *
903   * Space is allocated for each PCI base address register (BAR) so that the
904   * devices are mapped into memory and I/O space ready for use.
905   *
906   * @bus:	Bus containing devices to bind
907   * @return 0 if OK, -ve on error
908   */
909  int pci_auto_config_devices(struct udevice *bus);
910  
911  /**
912   * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
913   *
914   * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
915   * @devp:	Returns the device for this address, if found
916   * @return 0 if OK, -ENODEV if not found
917   */
918  int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
919  
920  /**
921   * pci_bus_find_devfn() - Find a device on a bus
922   *
923   * @find_devfn:		PCI device address (device and function only)
924   * @devp:	Returns the device for this address, if found
925   * @return 0 if OK, -ENODEV if not found
926   */
927  int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
928  		       struct udevice **devp);
929  
930  /**
931   * pci_find_first_device() - return the first available PCI device
932   *
933   * This function and pci_find_first_device() allow iteration through all
934   * available PCI devices on all buses. Assuming there are any, this will
935   * return the first one.
936   *
937   * @devp:	Set to the first available device, or NULL if no more are left
938   *		or we got an error
939   * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
940   */
941  int pci_find_first_device(struct udevice **devp);
942  
943  /**
944   * pci_find_next_device() - return the next available PCI device
945   *
946   * Finds the next available PCI device after the one supplied, or sets @devp
947   * to NULL if there are no more.
948   *
949   * @devp:	On entry, the last device returned. Set to the next available
950   *		device, or NULL if no more are left or we got an error
951   * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
952   */
953  int pci_find_next_device(struct udevice **devp);
954  
955  /**
956   * pci_get_ff() - Returns a mask for the given access size
957   *
958   * @size:	Access size
959   * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
960   * PCI_SIZE_32
961   */
962  int pci_get_ff(enum pci_size_t size);
963  
964  /**
965   * pci_bus_find_devices () - Find devices on a bus
966   *
967   * @bus:	Bus to search
968   * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
969   * @indexp:	Pointer to device index to find. To find the first matching
970   *		device, pass 0; to find the second, pass 1, etc. This
971   *		parameter is decremented for each non-matching device so
972   *		can be called repeatedly.
973   * @devp:	Returns matching device if found
974   * @return 0 if found, -ENODEV if not
975   */
976  int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
977  			 int *indexp, struct udevice **devp);
978  
979  /**
980   * pci_find_device_id() - Find a device on any bus
981   *
982   * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
983   * @index:	Index number of device to find, 0 for the first match, 1 for
984   *		the second, etc.
985   * @devp:	Returns matching device if found
986   * @return 0 if found, -ENODEV if not
987   */
988  int pci_find_device_id(struct pci_device_id *ids, int index,
989  		       struct udevice **devp);
990  
991  /**
992   * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
993   *
994   * This probes the given bus which causes it to be scanned for devices. The
995   * devices will be bound but not probed.
996   *
997   * @hose specifies the PCI hose that will be used for the scan. This is
998   * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
999   * in @bdf, and is a subordinate bus reachable from @hose.
1000   *
1001   * @hose:	PCI hose to scan
1002   * @bdf:	PCI bus address to scan (PCI_BUS(bdf) is the bus number)
1003   * @return 0 if OK, -ve on error
1004   */
1005  int dm_pci_hose_probe_bus(struct udevice *bus);
1006  
1007  /**
1008   * pci_bus_read_config() - Read a configuration value from a device
1009   *
1010   * TODO(sjg@chromium.org): We should be able to pass just a device and have
1011   * it do the right thing. It would be good to have that function also.
1012   *
1013   * @bus:	Bus to read from
1014   * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
1015   * @offset:	Register offset to read
1016   * @valuep:	Place to put the returned value
1017   * @size:	Access size
1018   * @return 0 if OK, -ve on error
1019   */
1020  int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
1021  			unsigned long *valuep, enum pci_size_t size);
1022  
1023  /**
1024   * pci_bus_write_config() - Write a configuration value to a device
1025   *
1026   * @bus:	Bus to write from
1027   * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
1028   * @offset:	Register offset to write
1029   * @value:	Value to write
1030   * @size:	Access size
1031   * @return 0 if OK, -ve on error
1032   */
1033  int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1034  			 unsigned long value, enum pci_size_t size);
1035  
1036  /**
1037   * pci_bus_clrset_config32() - Update a configuration value for a device
1038   *
1039   * The register at @offset is updated to (oldvalue & ~clr) | set.
1040   *
1041   * @bus:	Bus to access
1042   * @bdf:	PCI device address: bus, device and function -see PCI_BDF()
1043   * @offset:	Register offset to update
1044   * @clr:	Bits to clear
1045   * @set:	Bits to set
1046   * @return 0 if OK, -ve on error
1047   */
1048  int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1049  			    u32 clr, u32 set);
1050  
1051  /**
1052   * Driver model PCI config access functions. Use these in preference to others
1053   * when you have a valid device
1054   */
1055  int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
1056  		       enum pci_size_t size);
1057  
1058  int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
1059  int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
1060  int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
1061  
1062  int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1063  			enum pci_size_t size);
1064  
1065  int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1066  int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1067  int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1068  
1069  /**
1070   * These permit convenient read/modify/write on PCI configuration. The
1071   * register is updated to (oldvalue & ~clr) | set.
1072   */
1073  int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1074  int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1075  int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
1076  
1077  /*
1078   * The following functions provide access to the above without needing the
1079   * size parameter. We are trying to encourage the use of the 8/16/32-style
1080   * functions, rather than byte/word/dword. But both are supported.
1081   */
1082  int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
1083  int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1084  int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1085  int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1086  int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1087  int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
1088  
1089  /**
1090   * pci_generic_mmap_write_config() - Generic helper for writing to
1091   * memory-mapped PCI configuration space.
1092   * @bus: Pointer to the PCI bus
1093   * @addr_f: Callback for calculating the config space address
1094   * @bdf: Identifies the PCI device to access
1095   * @offset: The offset into the device's configuration space
1096   * @value: The value to write
1097   * @size: Indicates the size of access to perform
1098   *
1099   * Write the value @value of size @size from offset @offset within the
1100   * configuration space of the device identified by the bus, device & function
1101   * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
1102   * responsible for calculating the CPU address of the respective configuration
1103   * space offset.
1104   *
1105   * Return: 0 on success, else -EINVAL
1106   */
1107  int pci_generic_mmap_write_config(
1108  	struct udevice *bus,
1109  	int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1110  	pci_dev_t bdf,
1111  	uint offset,
1112  	ulong value,
1113  	enum pci_size_t size);
1114  
1115  /**
1116   * pci_generic_mmap_read_config() - Generic helper for reading from
1117   * memory-mapped PCI configuration space.
1118   * @bus: Pointer to the PCI bus
1119   * @addr_f: Callback for calculating the config space address
1120   * @bdf: Identifies the PCI device to access
1121   * @offset: The offset into the device's configuration space
1122   * @valuep: A pointer at which to store the read value
1123   * @size: Indicates the size of access to perform
1124   *
1125   * Read a value of size @size from offset @offset within the configuration
1126   * space of the device identified by the bus, device & function numbers in @bdf
1127   * on the PCI bus @bus. The callback function @addr_f is responsible for
1128   * calculating the CPU address of the respective configuration space offset.
1129   *
1130   * Return: 0 on success, else -EINVAL
1131   */
1132  int pci_generic_mmap_read_config(
1133  	struct udevice *bus,
1134  	int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1135  	pci_dev_t bdf,
1136  	uint offset,
1137  	ulong *valuep,
1138  	enum pci_size_t size);
1139  
1140  #ifdef CONFIG_DM_PCI_COMPAT
1141  /* Compatibility with old naming */
1142  static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1143  					 u32 value)
1144  {
1145  	return pci_write_config32(pcidev, offset, value);
1146  }
1147  
1148  /* Compatibility with old naming */
1149  static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1150  					u16 value)
1151  {
1152  	return pci_write_config16(pcidev, offset, value);
1153  }
1154  
1155  /* Compatibility with old naming */
1156  static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1157  					u8 value)
1158  {
1159  	return pci_write_config8(pcidev, offset, value);
1160  }
1161  
1162  /* Compatibility with old naming */
1163  static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1164  					u32 *valuep)
1165  {
1166  	return pci_read_config32(pcidev, offset, valuep);
1167  }
1168  
1169  /* Compatibility with old naming */
1170  static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1171  				       u16 *valuep)
1172  {
1173  	return pci_read_config16(pcidev, offset, valuep);
1174  }
1175  
1176  /* Compatibility with old naming */
1177  static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1178  				       u8 *valuep)
1179  {
1180  	return pci_read_config8(pcidev, offset, valuep);
1181  }
1182  #endif /* CONFIG_DM_PCI_COMPAT */
1183  
1184  /**
1185   * dm_pciauto_config_device() - configure a device ready for use
1186   *
1187   * Space is allocated for each PCI base address register (BAR) so that the
1188   * devices are mapped into memory and I/O space ready for use.
1189   *
1190   * @dev:	Device to configure
1191   * @return 0 if OK, -ve on error
1192   */
1193  int dm_pciauto_config_device(struct udevice *dev);
1194  
1195  /**
1196   * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1197   *
1198   * Some PCI buses must always perform 32-bit reads. The data must then be
1199   * shifted and masked to reflect the required access size and offset. This
1200   * function performs this transformation.
1201   *
1202   * @value:	Value to transform (32-bit value read from @offset & ~3)
1203   * @offset:	Register offset that was read
1204   * @size:	Required size of the result
1205   * @return the value that would have been obtained if the read had been
1206   * performed at the given offset with the correct size
1207   */
1208  ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1209  
1210  /**
1211   * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1212   *
1213   * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1214   * write the old 32-bit data must be read, updated with the required new data
1215   * and written back as a 32-bit value. This function performs the
1216   * transformation from the old value to the new value.
1217   *
1218   * @value:	Value to transform (32-bit value read from @offset & ~3)
1219   * @offset:	Register offset that should be written
1220   * @size:	Required size of the write
1221   * @return the value that should be written as a 32-bit access to @offset & ~3.
1222   */
1223  ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1224  			  enum pci_size_t size);
1225  
1226  /**
1227   * pci_get_controller() - obtain the controller to use for a bus
1228   *
1229   * @dev:	Device to check
1230   * @return pointer to the controller device for this bus
1231   */
1232  struct udevice *pci_get_controller(struct udevice *dev);
1233  
1234  /**
1235   * pci_get_regions() - obtain pointers to all the region types
1236   *
1237   * @dev:	Device to check
1238   * @iop:	Returns a pointer to the I/O region, or NULL if none
1239   * @memp:	Returns a pointer to the memory region, or NULL if none
1240   * @prefp:	Returns a pointer to the pre-fetch region, or NULL if none
1241   * @return the number of non-NULL regions returned, normally 3
1242   */
1243  int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1244  		    struct pci_region **memp, struct pci_region **prefp);
1245  
1246  /**
1247   * dm_pci_write_bar32() - Write the address of a BAR
1248   *
1249   * This writes a raw address to a bar
1250   *
1251   * @dev:	PCI device to update
1252   * @barnum:	BAR number (0-5)
1253   * @addr:	BAR address
1254   */
1255  void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1256  
1257  /**
1258   * dm_pci_read_bar32() - read a base address register from a device
1259   *
1260   * @dev:	Device to check
1261   * @barnum:	Bar number to read (numbered from 0)
1262   * @return: value of BAR
1263   */
1264  u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
1265  
1266  /**
1267   * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
1268   *
1269   * @dev:	Device containing the PCI address
1270   * @addr:	PCI address to convert
1271   * @flags:	Flags for the region type (PCI_REGION_...)
1272   * @return physical address corresponding to that PCI bus address
1273   */
1274  phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1275  			       unsigned long flags);
1276  
1277  /**
1278   * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1279   *
1280   * @dev:	Device containing the bus address
1281   * @addr:	Physical address to convert
1282   * @flags:	Flags for the region type (PCI_REGION_...)
1283   * @return PCI bus address corresponding to that physical address
1284   */
1285  pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1286  			      unsigned long flags);
1287  
1288  /**
1289   * dm_pci_map_bar() - get a virtual address associated with a BAR region
1290   *
1291   * Looks up a base address register and finds the physical memory address
1292   * that corresponds to it
1293   *
1294   * @dev:	Device to check
1295   * @bar:	Bar number to read (numbered from 0)
1296   * @flags:	Flags for the region type (PCI_REGION_...)
1297   * @return: pointer to the virtual address to use
1298   */
1299  void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
1300  
1301  #define dm_pci_virt_to_bus(dev, addr, flags) \
1302  	dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1303  #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1304  	map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1305  		    (len), (map_flags))
1306  
1307  #define dm_pci_phys_to_mem(dev, addr) \
1308  	dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1309  #define dm_pci_mem_to_phys(dev, addr) \
1310  	dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1311  #define dm_pci_phys_to_io(dev, addr) \
1312  	dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1313  #define dm_pci_io_to_phys(dev, addr) \
1314  	dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1315  
1316  #define dm_pci_virt_to_mem(dev, addr) \
1317  	dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1318  #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1319  	dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1320  #define dm_pci_virt_to_io(dev, addr) \
1321  	dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
1322  #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
1323  	dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
1324  
1325  /**
1326   * dm_pci_find_device() - find a device by vendor/device ID
1327   *
1328   * @vendor:	Vendor ID
1329   * @device:	Device ID
1330   * @index:	0 to find the first match, 1 for second, etc.
1331   * @devp:	Returns pointer to the device, if found
1332   * @return 0 if found, -ve on error
1333   */
1334  int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1335  		       struct udevice **devp);
1336  
1337  /**
1338   * dm_pci_find_class() - find a device by class
1339   *
1340   * @find_class: 3-byte (24-bit) class value to find
1341   * @index:	0 to find the first match, 1 for second, etc.
1342   * @devp:	Returns pointer to the device, if found
1343   * @return 0 if found, -ve on error
1344   */
1345  int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1346  
1347  /**
1348   * struct dm_pci_emul_ops - PCI device emulator operations
1349   */
1350  struct dm_pci_emul_ops {
1351  	/**
1352  	 * get_devfn(): Check which device and function this emulators
1353  	 *
1354  	 * @dev:	device to check
1355  	 * @return the device and function this emulates, or -ve on error
1356  	 */
1357  	int (*get_devfn)(struct udevice *dev);
1358  	/**
1359  	 * read_config() - Read a PCI configuration value
1360  	 *
1361  	 * @dev:	Emulated device to read from
1362  	 * @offset:	Byte offset within the device's configuration space
1363  	 * @valuep:	Place to put the returned value
1364  	 * @size:	Access size
1365  	 * @return 0 if OK, -ve on error
1366  	 */
1367  	int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
1368  			   enum pci_size_t size);
1369  	/**
1370  	 * write_config() - Write a PCI configuration value
1371  	 *
1372  	 * @dev:	Emulated device to write to
1373  	 * @offset:	Byte offset within the device's configuration space
1374  	 * @value:	Value to write
1375  	 * @size:	Access size
1376  	 * @return 0 if OK, -ve on error
1377  	 */
1378  	int (*write_config)(struct udevice *dev, uint offset, ulong value,
1379  			    enum pci_size_t size);
1380  	/**
1381  	 * read_io() - Read a PCI I/O value
1382  	 *
1383  	 * @dev:	Emulated device to read from
1384  	 * @addr:	I/O address to read
1385  	 * @valuep:	Place to put the returned value
1386  	 * @size:	Access size
1387  	 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1388  	 *		other -ve value on error
1389  	 */
1390  	int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1391  		       enum pci_size_t size);
1392  	/**
1393  	 * write_io() - Write a PCI I/O value
1394  	 *
1395  	 * @dev:	Emulated device to write from
1396  	 * @addr:	I/O address to write
1397  	 * @value:	Value to write
1398  	 * @size:	Access size
1399  	 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1400  	 *		other -ve value on error
1401  	 */
1402  	int (*write_io)(struct udevice *dev, unsigned int addr,
1403  			ulong value, enum pci_size_t size);
1404  	/**
1405  	 * map_physmem() - Map a device into sandbox memory
1406  	 *
1407  	 * @dev:	Emulated device to map
1408  	 * @addr:	Memory address, normally corresponding to a PCI BAR.
1409  	 *		The device should have been configured to have a BAR
1410  	 *		at this address.
1411  	 * @lenp:	On entry, the size of the area to map, On exit it is
1412  	 *		updated to the size actually mapped, which may be less
1413  	 *		if the device has less space
1414  	 * @ptrp:	Returns a pointer to the mapped address. The device's
1415  	 *		space can be accessed as @lenp bytes starting here
1416  	 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1417  	 *		other -ve value on error
1418  	 */
1419  	int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1420  			   unsigned long *lenp, void **ptrp);
1421  	/**
1422  	 * unmap_physmem() - undo a memory mapping
1423  	 *
1424  	 * This must be called after map_physmem() to undo the mapping.
1425  	 * Some devices can use this to check what has been written into
1426  	 * their mapped memory and perform an operations they require on it.
1427  	 * In this way, map/unmap can be used as a sort of handshake between
1428  	 * the emulated device and its users.
1429  	 *
1430  	 * @dev:	Emuated device to unmap
1431  	 * @vaddr:	Mapped memory address, as passed to map_physmem()
1432  	 * @len:	Size of area mapped, as returned by map_physmem()
1433  	 * @return 0 if OK, -ve on error
1434  	 */
1435  	int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1436  			     unsigned long len);
1437  };
1438  
1439  /* Get access to a PCI device emulator's operations */
1440  #define pci_get_emul_ops(dev)	((struct dm_pci_emul_ops *)(dev)->driver->ops)
1441  
1442  /**
1443   * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1444   *
1445   * Searches for a suitable emulator for the given PCI bus device
1446   *
1447   * @bus:	PCI bus to search
1448   * @find_devfn:	PCI device and function address (PCI_DEVFN())
1449   * @emulp:	Returns emulated device if found
1450   * @return 0 if found, -ENODEV if not found
1451   */
1452  int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
1453  			 struct udevice **emulp);
1454  
1455  #endif /* CONFIG_DM_PCI */
1456  
1457  /**
1458   * PCI_DEVICE - macro used to describe a specific pci device
1459   * @vend: the 16 bit PCI Vendor ID
1460   * @dev: the 16 bit PCI Device ID
1461   *
1462   * This macro is used to create a struct pci_device_id that matches a
1463   * specific device.  The subvendor and subdevice fields will be set to
1464   * PCI_ANY_ID.
1465   */
1466  #define PCI_DEVICE(vend, dev) \
1467  	.vendor = (vend), .device = (dev), \
1468  	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1469  
1470  /**
1471   * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1472   * @vend: the 16 bit PCI Vendor ID
1473   * @dev: the 16 bit PCI Device ID
1474   * @subvend: the 16 bit PCI Subvendor ID
1475   * @subdev: the 16 bit PCI Subdevice ID
1476   *
1477   * This macro is used to create a struct pci_device_id that matches a
1478   * specific device with subsystem information.
1479   */
1480  #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1481  	.vendor = (vend), .device = (dev), \
1482  	.subvendor = (subvend), .subdevice = (subdev)
1483  
1484  /**
1485   * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1486   * @dev_class: the class, subclass, prog-if triple for this device
1487   * @dev_class_mask: the class mask for this device
1488   *
1489   * This macro is used to create a struct pci_device_id that matches a
1490   * specific PCI class.  The vendor, device, subvendor, and subdevice
1491   * fields will be set to PCI_ANY_ID.
1492   */
1493  #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1494  	.class = (dev_class), .class_mask = (dev_class_mask), \
1495  	.vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1496  	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1497  
1498  /**
1499   * PCI_VDEVICE - macro used to describe a specific pci device in short form
1500   * @vend: the vendor name
1501   * @dev: the 16 bit PCI Device ID
1502   *
1503   * This macro is used to create a struct pci_device_id that matches a
1504   * specific PCI device.  The subvendor, and subdevice fields will be set
1505   * to PCI_ANY_ID. The macro allows the next field to follow as the device
1506   * private data.
1507   */
1508  
1509  #define PCI_VDEVICE(vend, dev) \
1510  	.vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1511  	.subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1512  
1513  /**
1514   * struct pci_driver_entry - Matches a driver to its pci_device_id list
1515   * @driver: Driver to use
1516   * @match: List of match records for this driver, terminated by {}
1517   */
1518  struct pci_driver_entry {
1519  	struct driver *driver;
1520  	const struct pci_device_id *match;
1521  };
1522  
1523  #define U_BOOT_PCI_DEVICE(__name, __match)				\
1524  	ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1525  		.driver = llsym(struct driver, __name, driver), \
1526  		.match = __match, \
1527  		}
1528  
1529  #endif /* __ASSEMBLY__ */
1530  #endif /* _PCI_H */
1531