1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 4 * Andreas Heppel <aheppel@sysgo.de> 5 * 6 * (C) Copyright 2002 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 */ 9 10 #ifndef _PCI_H 11 #define _PCI_H 12 13 #define PCI_CFG_SPACE_SIZE 256 14 #define PCI_CFG_SPACE_EXP_SIZE 4096 15 16 /* 17 * Under PCI, each device has 256 bytes of configuration address space, 18 * of which the first 64 bytes are standardized as follows: 19 */ 20 #define PCI_STD_HEADER_SIZEOF 64 21 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 22 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 23 #define PCI_COMMAND 0x04 /* 16 bits */ 24 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 25 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 26 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 27 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 28 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 29 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 30 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 31 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 32 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 33 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 34 35 #define PCI_STATUS 0x06 /* 16 bits */ 36 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 37 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 38 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 39 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 40 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 41 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 42 #define PCI_STATUS_DEVSEL_FAST 0x000 43 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 44 #define PCI_STATUS_DEVSEL_SLOW 0x400 45 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 46 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 47 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 48 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 49 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 50 51 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 52 revision */ 53 #define PCI_REVISION_ID 0x08 /* Revision ID */ 54 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 55 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 56 #define PCI_CLASS_CODE 0x0b /* Device class code */ 57 #define PCI_CLASS_CODE_TOO_OLD 0x00 58 #define PCI_CLASS_CODE_STORAGE 0x01 59 #define PCI_CLASS_CODE_NETWORK 0x02 60 #define PCI_CLASS_CODE_DISPLAY 0x03 61 #define PCI_CLASS_CODE_MULTIMEDIA 0x04 62 #define PCI_CLASS_CODE_MEMORY 0x05 63 #define PCI_CLASS_CODE_BRIDGE 0x06 64 #define PCI_CLASS_CODE_COMM 0x07 65 #define PCI_CLASS_CODE_PERIPHERAL 0x08 66 #define PCI_CLASS_CODE_INPUT 0x09 67 #define PCI_CLASS_CODE_DOCKING 0x0A 68 #define PCI_CLASS_CODE_PROCESSOR 0x0B 69 #define PCI_CLASS_CODE_SERIAL 0x0C 70 #define PCI_CLASS_CODE_WIRELESS 0x0D 71 #define PCI_CLASS_CODE_I2O 0x0E 72 #define PCI_CLASS_CODE_SATELLITE 0x0F 73 #define PCI_CLASS_CODE_CRYPTO 0x10 74 #define PCI_CLASS_CODE_DATA 0x11 75 /* Base Class 0x12 - 0xFE is reserved */ 76 #define PCI_CLASS_CODE_OTHER 0xFF 77 78 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 79 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 80 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 81 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 82 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 83 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 84 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 85 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 86 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 87 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 88 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 89 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 90 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 91 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 92 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 93 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 94 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 95 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 96 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 97 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 98 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 99 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 100 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 101 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 105 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 106 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 107 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 108 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 109 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 110 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 111 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 112 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 113 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 114 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 115 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 116 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 117 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 118 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 119 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A 120 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 121 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 122 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 123 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 124 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 125 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 126 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 127 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 134 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 135 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 136 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 137 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 138 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 139 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 140 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 141 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 142 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 143 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 144 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 145 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 146 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 147 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 148 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 149 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 150 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 151 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 152 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 153 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 154 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 155 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 156 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 157 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 158 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 159 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 160 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 161 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 162 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 163 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 164 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 165 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 166 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 167 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 168 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 169 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 170 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 171 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 172 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 173 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 174 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 175 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 176 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 177 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 178 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 179 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 180 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 181 182 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 183 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 184 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 185 #define PCI_HEADER_TYPE_NORMAL 0 186 #define PCI_HEADER_TYPE_BRIDGE 1 187 #define PCI_HEADER_TYPE_CARDBUS 2 188 189 #define PCI_BIST 0x0f /* 8 bits */ 190 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 191 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 192 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 193 194 /* 195 * Base addresses specify locations in memory or I/O space. 196 * Decoded size can be determined by writing a value of 197 * 0xffffffff to the register, and reading it back. Only 198 * 1 bits are decoded. 199 */ 200 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 201 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 202 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 203 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 204 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 205 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 206 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 207 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 208 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 209 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 210 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 211 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 212 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 213 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 214 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 215 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 216 /* bit 1 is reserved if address_space = 1 */ 217 218 /* Header type 0 (normal devices) */ 219 #define PCI_CARDBUS_CIS 0x28 220 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 221 #define PCI_SUBSYSTEM_ID 0x2e 222 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 223 #define PCI_ROM_ADDRESS_ENABLE 0x01 224 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 225 226 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 227 228 /* 0x35-0x3b are reserved */ 229 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 230 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 231 #define PCI_MIN_GNT 0x3e /* 8 bits */ 232 #define PCI_MAX_LAT 0x3f /* 8 bits */ 233 234 #define PCI_INTERRUPT_LINE_DISABLE 0xff 235 236 /* Header type 1 (PCI-to-PCI bridges) */ 237 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 238 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 239 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 240 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 241 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 242 #define PCI_IO_LIMIT 0x1d 243 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 244 #define PCI_IO_RANGE_TYPE_16 0x00 245 #define PCI_IO_RANGE_TYPE_32 0x01 246 #define PCI_IO_RANGE_MASK ~0x0f 247 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 248 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 249 #define PCI_MEMORY_LIMIT 0x22 250 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 251 #define PCI_MEMORY_RANGE_MASK ~0x0f 252 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 253 #define PCI_PREF_MEMORY_LIMIT 0x26 254 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 255 #define PCI_PREF_RANGE_TYPE_32 0x00 256 #define PCI_PREF_RANGE_TYPE_64 0x01 257 #define PCI_PREF_RANGE_MASK ~0x0f 258 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 259 #define PCI_PREF_LIMIT_UPPER32 0x2c 260 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 261 #define PCI_IO_LIMIT_UPPER16 0x32 262 /* 0x34 same as for htype 0 */ 263 /* 0x35-0x3b is reserved */ 264 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 265 /* 0x3c-0x3d are same as for htype 0 */ 266 #define PCI_BRIDGE_CONTROL 0x3e 267 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 268 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 269 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 270 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 271 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 272 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 273 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 274 275 /* Header type 2 (CardBus bridges) */ 276 #define PCI_CB_CAPABILITY_LIST 0x14 277 /* 0x15 reserved */ 278 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 279 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 280 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 281 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 282 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 283 #define PCI_CB_MEMORY_BASE_0 0x1c 284 #define PCI_CB_MEMORY_LIMIT_0 0x20 285 #define PCI_CB_MEMORY_BASE_1 0x24 286 #define PCI_CB_MEMORY_LIMIT_1 0x28 287 #define PCI_CB_IO_BASE_0 0x2c 288 #define PCI_CB_IO_BASE_0_HI 0x2e 289 #define PCI_CB_IO_LIMIT_0 0x30 290 #define PCI_CB_IO_LIMIT_0_HI 0x32 291 #define PCI_CB_IO_BASE_1 0x34 292 #define PCI_CB_IO_BASE_1_HI 0x36 293 #define PCI_CB_IO_LIMIT_1 0x38 294 #define PCI_CB_IO_LIMIT_1_HI 0x3a 295 #define PCI_CB_IO_RANGE_MASK ~0x03 296 /* 0x3c-0x3d are same as for htype 0 */ 297 #define PCI_CB_BRIDGE_CONTROL 0x3e 298 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 299 #define PCI_CB_BRIDGE_CTL_SERR 0x02 300 #define PCI_CB_BRIDGE_CTL_ISA 0x04 301 #define PCI_CB_BRIDGE_CTL_VGA 0x08 302 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 303 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 304 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 305 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 306 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 307 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 308 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 309 #define PCI_CB_SUBSYSTEM_ID 0x42 310 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 311 /* 0x48-0x7f reserved */ 312 313 /* Capability lists */ 314 315 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 316 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 317 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 318 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 319 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 320 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 321 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 322 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ 323 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ 324 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */ 325 #define PCI_CAP_ID_DBG 0x0A /* Debug port */ 326 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ 327 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */ 328 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ 329 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */ 330 #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */ 331 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 332 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ 333 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */ 334 #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */ 335 #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */ 336 #define PCI_CAP_ID_MAX PCI_CAP_ID_EA 337 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 338 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 339 #define PCI_CAP_SIZEOF 4 340 341 /* Power Management Registers */ 342 343 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 344 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 345 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 346 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 347 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 348 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 349 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 350 #define PCI_PM_CTRL 4 /* PM control and status register */ 351 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 352 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 353 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 354 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 355 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 356 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 357 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 358 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 359 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 360 #define PCI_PM_SIZEOF 8 361 362 /* AGP registers */ 363 364 #define PCI_AGP_VERSION 2 /* BCD version number */ 365 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 366 #define PCI_AGP_STATUS 4 /* Status register */ 367 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 368 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 369 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 370 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 371 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 372 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 373 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 374 #define PCI_AGP_COMMAND 8 /* Control register */ 375 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 376 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 377 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 378 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 379 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 380 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 381 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 382 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 383 #define PCI_AGP_SIZEOF 12 384 385 /* PCI-X registers */ 386 387 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 388 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 389 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 390 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 391 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 392 393 394 /* Slot Identification */ 395 396 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 397 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 398 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 399 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 400 401 /* Message Signalled Interrupts registers */ 402 403 #define PCI_MSI_FLAGS 2 /* Various flags */ 404 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 405 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 406 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 407 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 408 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 409 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 410 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 411 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 412 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 413 414 #define PCI_MAX_PCI_DEVICES 32 415 #define PCI_MAX_PCI_FUNCTIONS 8 416 417 #define PCI_FIND_CAP_TTL 0x48 418 #define CAP_START_POS 0x40 419 420 /* Extended Capabilities (PCI-X 2.0 and Express) */ 421 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 422 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 423 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 424 425 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 426 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 427 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 428 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 429 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 430 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 431 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 432 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 433 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 434 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 435 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 436 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 437 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 438 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 439 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 440 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 441 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 442 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 443 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 444 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 445 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 446 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 447 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 448 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 449 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 450 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 451 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 452 #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ 453 #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ 454 #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ 455 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM 456 457 /* Include the ID list */ 458 459 #include <pci_ids.h> 460 461 #ifndef __ASSEMBLY__ 462 463 #ifdef CONFIG_SYS_PCI_64BIT 464 typedef u64 pci_addr_t; 465 typedef u64 pci_size_t; 466 #else 467 typedef u32 pci_addr_t; 468 typedef u32 pci_size_t; 469 #endif 470 471 struct pci_region { 472 pci_addr_t bus_start; /* Start on the bus */ 473 phys_addr_t phys_start; /* Start in physical address space */ 474 pci_size_t size; /* Size */ 475 unsigned long flags; /* Resource flags */ 476 477 pci_addr_t bus_lower; 478 }; 479 480 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 481 #define PCI_REGION_IO 0x00000001 /* PCI IO space */ 482 #define PCI_REGION_TYPE 0x00000001 483 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 484 485 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 486 #define PCI_REGION_RO 0x00000200 /* Read-only memory */ 487 488 static inline void pci_set_region(struct pci_region *reg, 489 pci_addr_t bus_start, 490 phys_addr_t phys_start, 491 pci_size_t size, 492 unsigned long flags) { 493 reg->bus_start = bus_start; 494 reg->phys_start = phys_start; 495 reg->size = size; 496 reg->flags = flags; 497 } 498 499 typedef int pci_dev_t; 500 501 #define PCI_BUS(d) (((d) >> 16) & 0xff) 502 503 /* 504 * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot 505 * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0. 506 * Please see the Linux header include/uapi/linux/pci.h for more details. 507 * This is relevant for the following macros: 508 * PCI_DEV, PCI_FUNC, PCI_DEVFN 509 * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with 510 * the remark from above (input d in bits 15-8 instead of 7-0. 511 */ 512 #define PCI_DEV(d) (((d) >> 11) & 0x1f) 513 #define PCI_FUNC(d) (((d) >> 8) & 0x7) 514 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) 515 516 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) 517 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) 518 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) 519 #define PCI_VENDEV(v, d) (((v) << 16) | (d)) 520 #define PCI_ANY_ID (~0) 521 522 struct pci_device_id { 523 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 524 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ 525 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ 526 unsigned long driver_data; /* Data private to the driver */ 527 }; 528 529 struct pci_controller; 530 531 struct pci_config_table { 532 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 533 unsigned int class; /* Class ID, or PCI_ANY_ID */ 534 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 535 unsigned int dev; /* Device number, or PCI_ANY_ID */ 536 unsigned int func; /* Function number, or PCI_ANY_ID */ 537 538 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 539 struct pci_config_table *); 540 unsigned long priv[3]; 541 }; 542 543 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 544 struct pci_config_table *); 545 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 546 struct pci_config_table *); 547 548 #define MAX_PCI_REGIONS 7 549 550 #define INDIRECT_TYPE_NO_PCIE_LINK 1 551 552 /* 553 * Structure of a PCI controller (host bridge) 554 * 555 * With driver model this is dev_get_uclass_priv(bus) 556 */ 557 struct pci_controller { 558 #ifdef CONFIG_DM_PCI 559 struct udevice *bus; 560 struct udevice *ctlr; 561 #else 562 struct pci_controller *next; 563 #endif 564 565 int first_busno; 566 int last_busno; 567 568 volatile unsigned int *cfg_addr; 569 volatile unsigned char *cfg_data; 570 571 int indirect_type; 572 573 /* 574 * TODO(sjg@chromium.org): With driver model we use struct 575 * pci_controller for both the controller and any bridge devices 576 * attached to it. But there is only one region list and it is in the 577 * top-level controller. 578 * 579 * This could be changed so that struct pci_controller is only used 580 * for PCI controllers and a separate UCLASS (or perhaps 581 * UCLASS_PCI_GENERIC) is used for bridges. 582 */ 583 struct pci_region regions[MAX_PCI_REGIONS]; 584 int region_count; 585 586 struct pci_config_table *config_table; 587 588 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 589 #ifndef CONFIG_DM_PCI 590 /* Low-level architecture-dependent routines */ 591 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); 592 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); 593 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); 594 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); 595 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); 596 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); 597 #endif 598 599 /* Used by auto config */ 600 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 601 602 #ifndef CONFIG_DM_PCI 603 int current_busno; 604 605 void *priv_data; 606 #endif 607 }; 608 609 #ifndef CONFIG_DM_PCI 610 static inline void pci_set_ops(struct pci_controller *hose, 611 int (*read_byte)(struct pci_controller*, 612 pci_dev_t, int where, u8 *), 613 int (*read_word)(struct pci_controller*, 614 pci_dev_t, int where, u16 *), 615 int (*read_dword)(struct pci_controller*, 616 pci_dev_t, int where, u32 *), 617 int (*write_byte)(struct pci_controller*, 618 pci_dev_t, int where, u8), 619 int (*write_word)(struct pci_controller*, 620 pci_dev_t, int where, u16), 621 int (*write_dword)(struct pci_controller*, 622 pci_dev_t, int where, u32)) { 623 hose->read_byte = read_byte; 624 hose->read_word = read_word; 625 hose->read_dword = read_dword; 626 hose->write_byte = write_byte; 627 hose->write_word = write_word; 628 hose->write_dword = write_dword; 629 } 630 #endif 631 632 #ifdef CONFIG_PCI_INDIRECT_BRIDGE 633 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); 634 #endif 635 636 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 637 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 638 pci_addr_t addr, unsigned long flags); 639 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 640 phys_addr_t addr, unsigned long flags); 641 642 #define pci_phys_to_bus(dev, addr, flags) \ 643 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 644 #define pci_bus_to_phys(dev, addr, flags) \ 645 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 646 647 #define pci_virt_to_bus(dev, addr, flags) \ 648 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 649 (virt_to_phys(addr)), (flags)) 650 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 651 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 652 (addr), (flags)), \ 653 (len), (map_flags)) 654 655 #define pci_phys_to_mem(dev, addr) \ 656 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 657 #define pci_mem_to_phys(dev, addr) \ 658 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 659 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 660 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 661 662 #define pci_virt_to_mem(dev, addr) \ 663 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 664 #define pci_mem_to_virt(dev, addr, len, map_flags) \ 665 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 666 #define pci_virt_to_io(dev, addr) \ 667 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 668 #define pci_io_to_virt(dev, addr, len, map_flags) \ 669 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 670 671 /* For driver model these are defined in macros in pci_compat.c */ 672 extern int pci_hose_read_config_byte(struct pci_controller *hose, 673 pci_dev_t dev, int where, u8 *val); 674 extern int pci_hose_read_config_word(struct pci_controller *hose, 675 pci_dev_t dev, int where, u16 *val); 676 extern int pci_hose_read_config_dword(struct pci_controller *hose, 677 pci_dev_t dev, int where, u32 *val); 678 extern int pci_hose_write_config_byte(struct pci_controller *hose, 679 pci_dev_t dev, int where, u8 val); 680 extern int pci_hose_write_config_word(struct pci_controller *hose, 681 pci_dev_t dev, int where, u16 val); 682 extern int pci_hose_write_config_dword(struct pci_controller *hose, 683 pci_dev_t dev, int where, u32 val); 684 #endif 685 686 #ifndef CONFIG_DM_PCI 687 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); 688 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); 689 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); 690 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); 691 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); 692 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); 693 #endif 694 695 void pciauto_region_init(struct pci_region *res); 696 void pciauto_region_align(struct pci_region *res, pci_size_t size); 697 void pciauto_config_init(struct pci_controller *hose); 698 699 /** 700 * pciauto_region_allocate() - Allocate resources from a PCI resource region 701 * 702 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is 703 * false, the result will be guaranteed to fit in 32 bits. 704 * 705 * @res: PCI region to allocate from 706 * @size: Amount of bytes to allocate 707 * @bar: Returns the PCI bus address of the allocated resource 708 * @supports_64bit: Whether to allow allocations above the 32-bit boundary 709 * @return 0 if successful, -1 on failure 710 */ 711 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 712 pci_addr_t *bar, bool supports_64bit); 713 714 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 715 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 716 pci_dev_t dev, int where, u8 *val); 717 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 718 pci_dev_t dev, int where, u16 *val); 719 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 720 pci_dev_t dev, int where, u8 val); 721 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 722 pci_dev_t dev, int where, u16 val); 723 724 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 725 extern void pci_register_hose(struct pci_controller* hose); 726 extern struct pci_controller* pci_bus_to_hose(int bus); 727 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 728 extern struct pci_controller *pci_get_hose_head(void); 729 730 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); 731 extern int pci_hose_scan(struct pci_controller *hose); 732 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 733 734 extern void pciauto_setup_device(struct pci_controller *hose, 735 pci_dev_t dev, int bars_num, 736 struct pci_region *mem, 737 struct pci_region *prefetch, 738 struct pci_region *io); 739 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 740 pci_dev_t dev, int sub_bus); 741 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 742 pci_dev_t dev, int sub_bus); 743 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 744 745 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 746 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 747 pci_dev_t pci_find_class(unsigned int find_class, int index); 748 749 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 750 int cap); 751 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 752 u8 hdr_type); 753 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 754 int cap); 755 756 int pci_find_next_ext_capability(struct pci_controller *hose, 757 pci_dev_t dev, int start, int cap); 758 int pci_hose_find_ext_capability(struct pci_controller *hose, 759 pci_dev_t dev, int cap); 760 761 #ifdef CONFIG_PCI_FIXUP_DEV 762 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 763 unsigned short vendor, 764 unsigned short device, 765 unsigned short class); 766 #endif 767 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ 768 769 const char * pci_class_str(u8 class); 770 int pci_last_busno(void); 771 772 #ifdef CONFIG_MPC85xx 773 extern void pci_mpc85xx_init (struct pci_controller *hose); 774 #endif 775 776 #ifdef CONFIG_PCIE_IMX 777 extern void imx_pcie_remove(void); 778 #endif 779 780 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 781 /** 782 * pci_write_bar32() - Write the address of a BAR including control bits 783 * 784 * This writes a raw address (with control bits) to a bar. This can be used 785 * with devices which require hard-coded addresses, not part of the normal 786 * PCI enumeration process. 787 * 788 * @hose: PCI hose to use 789 * @dev: PCI device to update 790 * @barnum: BAR number (0-5) 791 * @addr: BAR address with control bits 792 */ 793 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, 794 u32 addr); 795 796 /** 797 * pci_read_bar32() - read the address of a bar 798 * 799 * @hose: PCI hose to use 800 * @dev: PCI device to inspect 801 * @barnum: BAR number (0-5) 802 * @return address of the bar, masking out any control bits 803 * */ 804 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); 805 806 /** 807 * pci_hose_find_devices() - Find devices by vendor/device ID 808 * 809 * @hose: PCI hose to search 810 * @busnum: Bus number to search 811 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 812 * @indexp: Pointer to device index to find. To find the first matching 813 * device, pass 0; to find the second, pass 1, etc. This 814 * parameter is decremented for each non-matching device so 815 * can be called repeatedly. 816 */ 817 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, 818 struct pci_device_id *ids, int *indexp); 819 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ 820 821 /* Access sizes for PCI reads and writes */ 822 enum pci_size_t { 823 PCI_SIZE_8, 824 PCI_SIZE_16, 825 PCI_SIZE_32, 826 }; 827 828 struct udevice; 829 830 #ifdef CONFIG_DM_PCI 831 /** 832 * struct pci_child_platdata - information stored about each PCI device 833 * 834 * Every device on a PCI bus has this per-child data. 835 * 836 * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a 837 * PCI bus (i.e. UCLASS_PCI) 838 * 839 * @devfn: Encoded device and function index - see PCI_DEVFN() 840 * @vendor: PCI vendor ID (see pci_ids.h) 841 * @device: PCI device ID (see pci_ids.h) 842 * @class: PCI class, 3 bytes: (base, sub, prog-if) 843 */ 844 struct pci_child_platdata { 845 int devfn; 846 unsigned short vendor; 847 unsigned short device; 848 unsigned int class; 849 }; 850 851 /* PCI bus operations */ 852 struct dm_pci_ops { 853 /** 854 * read_config() - Read a PCI configuration value 855 * 856 * PCI buses must support reading and writing configuration values 857 * so that the bus can be scanned and its devices configured. 858 * 859 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. 860 * If bridges exist it is possible to use the top-level bus to 861 * access a sub-bus. In that case @bus will be the top-level bus 862 * and PCI_BUS(bdf) will be a different (higher) value 863 * 864 * @bus: Bus to read from 865 * @bdf: Bus, device and function to read 866 * @offset: Byte offset within the device's configuration space 867 * @valuep: Place to put the returned value 868 * @size: Access size 869 * @return 0 if OK, -ve on error 870 */ 871 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 872 ulong *valuep, enum pci_size_t size); 873 /** 874 * write_config() - Write a PCI configuration value 875 * 876 * @bus: Bus to write to 877 * @bdf: Bus, device and function to write 878 * @offset: Byte offset within the device's configuration space 879 * @value: Value to write 880 * @size: Access size 881 * @return 0 if OK, -ve on error 882 */ 883 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 884 ulong value, enum pci_size_t size); 885 }; 886 887 /* Get access to a PCI bus' operations */ 888 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) 889 890 /** 891 * dm_pci_get_bdf() - Get the BDF value for a device 892 * 893 * @dev: Device to check 894 * @return bus/device/function value (see PCI_BDF()) 895 */ 896 pci_dev_t dm_pci_get_bdf(struct udevice *dev); 897 898 /** 899 * pci_bind_bus_devices() - scan a PCI bus and bind devices 900 * 901 * Scan a PCI bus looking for devices. Bind each one that is found. If 902 * devices are already bound that match the scanned devices, just update the 903 * child data so that the device can be used correctly (this happens when 904 * the device tree describes devices we expect to see on the bus). 905 * 906 * Devices that are bound in this way will use a generic PCI driver which 907 * does nothing. The device can still be accessed but will not provide any 908 * driver interface. 909 * 910 * @bus: Bus containing devices to bind 911 * @return 0 if OK, -ve on error 912 */ 913 int pci_bind_bus_devices(struct udevice *bus); 914 915 /** 916 * pci_auto_config_devices() - configure bus devices ready for use 917 * 918 * This works through all devices on a bus by scanning the driver model 919 * data structures (normally these have been set up by pci_bind_bus_devices() 920 * earlier). 921 * 922 * Space is allocated for each PCI base address register (BAR) so that the 923 * devices are mapped into memory and I/O space ready for use. 924 * 925 * @bus: Bus containing devices to bind 926 * @return 0 if OK, -ve on error 927 */ 928 int pci_auto_config_devices(struct udevice *bus); 929 930 /** 931 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address 932 * 933 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 934 * @devp: Returns the device for this address, if found 935 * @return 0 if OK, -ENODEV if not found 936 */ 937 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); 938 939 /** 940 * pci_bus_find_devfn() - Find a device on a bus 941 * 942 * @find_devfn: PCI device address (device and function only) 943 * @devp: Returns the device for this address, if found 944 * @return 0 if OK, -ENODEV if not found 945 */ 946 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 947 struct udevice **devp); 948 949 /** 950 * pci_find_first_device() - return the first available PCI device 951 * 952 * This function and pci_find_first_device() allow iteration through all 953 * available PCI devices on all buses. Assuming there are any, this will 954 * return the first one. 955 * 956 * @devp: Set to the first available device, or NULL if no more are left 957 * or we got an error 958 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 959 */ 960 int pci_find_first_device(struct udevice **devp); 961 962 /** 963 * pci_find_next_device() - return the next available PCI device 964 * 965 * Finds the next available PCI device after the one supplied, or sets @devp 966 * to NULL if there are no more. 967 * 968 * @devp: On entry, the last device returned. Set to the next available 969 * device, or NULL if no more are left or we got an error 970 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 971 */ 972 int pci_find_next_device(struct udevice **devp); 973 974 /** 975 * pci_get_ff() - Returns a mask for the given access size 976 * 977 * @size: Access size 978 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for 979 * PCI_SIZE_32 980 */ 981 int pci_get_ff(enum pci_size_t size); 982 983 /** 984 * pci_bus_find_devices () - Find devices on a bus 985 * 986 * @bus: Bus to search 987 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 988 * @indexp: Pointer to device index to find. To find the first matching 989 * device, pass 0; to find the second, pass 1, etc. This 990 * parameter is decremented for each non-matching device so 991 * can be called repeatedly. 992 * @devp: Returns matching device if found 993 * @return 0 if found, -ENODEV if not 994 */ 995 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 996 int *indexp, struct udevice **devp); 997 998 /** 999 * pci_find_device_id() - Find a device on any bus 1000 * 1001 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 1002 * @index: Index number of device to find, 0 for the first match, 1 for 1003 * the second, etc. 1004 * @devp: Returns matching device if found 1005 * @return 0 if found, -ENODEV if not 1006 */ 1007 int pci_find_device_id(struct pci_device_id *ids, int index, 1008 struct udevice **devp); 1009 1010 /** 1011 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices 1012 * 1013 * This probes the given bus which causes it to be scanned for devices. The 1014 * devices will be bound but not probed. 1015 * 1016 * @hose specifies the PCI hose that will be used for the scan. This is 1017 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is 1018 * in @bdf, and is a subordinate bus reachable from @hose. 1019 * 1020 * @hose: PCI hose to scan 1021 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) 1022 * @return 0 if OK, -ve on error 1023 */ 1024 int dm_pci_hose_probe_bus(struct udevice *bus); 1025 1026 /** 1027 * pci_bus_read_config() - Read a configuration value from a device 1028 * 1029 * TODO(sjg@chromium.org): We should be able to pass just a device and have 1030 * it do the right thing. It would be good to have that function also. 1031 * 1032 * @bus: Bus to read from 1033 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1034 * @offset: Register offset to read 1035 * @valuep: Place to put the returned value 1036 * @size: Access size 1037 * @return 0 if OK, -ve on error 1038 */ 1039 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 1040 unsigned long *valuep, enum pci_size_t size); 1041 1042 /** 1043 * pci_bus_write_config() - Write a configuration value to a device 1044 * 1045 * @bus: Bus to write from 1046 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1047 * @offset: Register offset to write 1048 * @value: Value to write 1049 * @size: Access size 1050 * @return 0 if OK, -ve on error 1051 */ 1052 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 1053 unsigned long value, enum pci_size_t size); 1054 1055 /** 1056 * pci_bus_clrset_config32() - Update a configuration value for a device 1057 * 1058 * The register at @offset is updated to (oldvalue & ~clr) | set. 1059 * 1060 * @bus: Bus to access 1061 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1062 * @offset: Register offset to update 1063 * @clr: Bits to clear 1064 * @set: Bits to set 1065 * @return 0 if OK, -ve on error 1066 */ 1067 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, 1068 u32 clr, u32 set); 1069 1070 /** 1071 * Driver model PCI config access functions. Use these in preference to others 1072 * when you have a valid device 1073 */ 1074 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, 1075 enum pci_size_t size); 1076 1077 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep); 1078 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep); 1079 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep); 1080 1081 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, 1082 enum pci_size_t size); 1083 1084 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value); 1085 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value); 1086 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); 1087 1088 /** 1089 * These permit convenient read/modify/write on PCI configuration. The 1090 * register is updated to (oldvalue & ~clr) | set. 1091 */ 1092 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set); 1093 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set); 1094 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set); 1095 1096 /* 1097 * The following functions provide access to the above without needing the 1098 * size parameter. We are trying to encourage the use of the 8/16/32-style 1099 * functions, rather than byte/word/dword. But both are supported. 1100 */ 1101 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); 1102 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); 1103 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); 1104 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); 1105 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); 1106 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); 1107 1108 /** 1109 * pci_generic_mmap_write_config() - Generic helper for writing to 1110 * memory-mapped PCI configuration space. 1111 * @bus: Pointer to the PCI bus 1112 * @addr_f: Callback for calculating the config space address 1113 * @bdf: Identifies the PCI device to access 1114 * @offset: The offset into the device's configuration space 1115 * @value: The value to write 1116 * @size: Indicates the size of access to perform 1117 * 1118 * Write the value @value of size @size from offset @offset within the 1119 * configuration space of the device identified by the bus, device & function 1120 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is 1121 * responsible for calculating the CPU address of the respective configuration 1122 * space offset. 1123 * 1124 * Return: 0 on success, else -EINVAL 1125 */ 1126 int pci_generic_mmap_write_config( 1127 struct udevice *bus, 1128 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), 1129 pci_dev_t bdf, 1130 uint offset, 1131 ulong value, 1132 enum pci_size_t size); 1133 1134 /** 1135 * pci_generic_mmap_read_config() - Generic helper for reading from 1136 * memory-mapped PCI configuration space. 1137 * @bus: Pointer to the PCI bus 1138 * @addr_f: Callback for calculating the config space address 1139 * @bdf: Identifies the PCI device to access 1140 * @offset: The offset into the device's configuration space 1141 * @valuep: A pointer at which to store the read value 1142 * @size: Indicates the size of access to perform 1143 * 1144 * Read a value of size @size from offset @offset within the configuration 1145 * space of the device identified by the bus, device & function numbers in @bdf 1146 * on the PCI bus @bus. The callback function @addr_f is responsible for 1147 * calculating the CPU address of the respective configuration space offset. 1148 * 1149 * Return: 0 on success, else -EINVAL 1150 */ 1151 int pci_generic_mmap_read_config( 1152 struct udevice *bus, 1153 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), 1154 pci_dev_t bdf, 1155 uint offset, 1156 ulong *valuep, 1157 enum pci_size_t size); 1158 1159 #ifdef CONFIG_DM_PCI_COMPAT 1160 /* Compatibility with old naming */ 1161 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, 1162 u32 value) 1163 { 1164 return pci_write_config32(pcidev, offset, value); 1165 } 1166 1167 /* Compatibility with old naming */ 1168 static inline int pci_write_config_word(pci_dev_t pcidev, int offset, 1169 u16 value) 1170 { 1171 return pci_write_config16(pcidev, offset, value); 1172 } 1173 1174 /* Compatibility with old naming */ 1175 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, 1176 u8 value) 1177 { 1178 return pci_write_config8(pcidev, offset, value); 1179 } 1180 1181 /* Compatibility with old naming */ 1182 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, 1183 u32 *valuep) 1184 { 1185 return pci_read_config32(pcidev, offset, valuep); 1186 } 1187 1188 /* Compatibility with old naming */ 1189 static inline int pci_read_config_word(pci_dev_t pcidev, int offset, 1190 u16 *valuep) 1191 { 1192 return pci_read_config16(pcidev, offset, valuep); 1193 } 1194 1195 /* Compatibility with old naming */ 1196 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, 1197 u8 *valuep) 1198 { 1199 return pci_read_config8(pcidev, offset, valuep); 1200 } 1201 #endif /* CONFIG_DM_PCI_COMPAT */ 1202 1203 /** 1204 * dm_pciauto_config_device() - configure a device ready for use 1205 * 1206 * Space is allocated for each PCI base address register (BAR) so that the 1207 * devices are mapped into memory and I/O space ready for use. 1208 * 1209 * @dev: Device to configure 1210 * @return 0 if OK, -ve on error 1211 */ 1212 int dm_pciauto_config_device(struct udevice *dev); 1213 1214 /** 1215 * pci_conv_32_to_size() - convert a 32-bit read value to the given size 1216 * 1217 * Some PCI buses must always perform 32-bit reads. The data must then be 1218 * shifted and masked to reflect the required access size and offset. This 1219 * function performs this transformation. 1220 * 1221 * @value: Value to transform (32-bit value read from @offset & ~3) 1222 * @offset: Register offset that was read 1223 * @size: Required size of the result 1224 * @return the value that would have been obtained if the read had been 1225 * performed at the given offset with the correct size 1226 */ 1227 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); 1228 1229 /** 1230 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write 1231 * 1232 * Some PCI buses must always perform 32-bit writes. To emulate a smaller 1233 * write the old 32-bit data must be read, updated with the required new data 1234 * and written back as a 32-bit value. This function performs the 1235 * transformation from the old value to the new value. 1236 * 1237 * @value: Value to transform (32-bit value read from @offset & ~3) 1238 * @offset: Register offset that should be written 1239 * @size: Required size of the write 1240 * @return the value that should be written as a 32-bit access to @offset & ~3. 1241 */ 1242 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, 1243 enum pci_size_t size); 1244 1245 /** 1246 * pci_get_controller() - obtain the controller to use for a bus 1247 * 1248 * @dev: Device to check 1249 * @return pointer to the controller device for this bus 1250 */ 1251 struct udevice *pci_get_controller(struct udevice *dev); 1252 1253 /** 1254 * pci_get_regions() - obtain pointers to all the region types 1255 * 1256 * @dev: Device to check 1257 * @iop: Returns a pointer to the I/O region, or NULL if none 1258 * @memp: Returns a pointer to the memory region, or NULL if none 1259 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none 1260 * @return the number of non-NULL regions returned, normally 3 1261 */ 1262 int pci_get_regions(struct udevice *dev, struct pci_region **iop, 1263 struct pci_region **memp, struct pci_region **prefp); 1264 1265 /** 1266 * dm_pci_write_bar32() - Write the address of a BAR 1267 * 1268 * This writes a raw address to a bar 1269 * 1270 * @dev: PCI device to update 1271 * @barnum: BAR number (0-5) 1272 * @addr: BAR address 1273 */ 1274 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); 1275 1276 /** 1277 * dm_pci_read_bar32() - read a base address register from a device 1278 * 1279 * @dev: Device to check 1280 * @barnum: Bar number to read (numbered from 0) 1281 * @return: value of BAR 1282 */ 1283 u32 dm_pci_read_bar32(struct udevice *dev, int barnum); 1284 1285 /** 1286 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address 1287 * 1288 * @dev: Device containing the PCI address 1289 * @addr: PCI address to convert 1290 * @flags: Flags for the region type (PCI_REGION_...) 1291 * @return physical address corresponding to that PCI bus address 1292 */ 1293 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, 1294 unsigned long flags); 1295 1296 /** 1297 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address 1298 * 1299 * @dev: Device containing the bus address 1300 * @addr: Physical address to convert 1301 * @flags: Flags for the region type (PCI_REGION_...) 1302 * @return PCI bus address corresponding to that physical address 1303 */ 1304 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, 1305 unsigned long flags); 1306 1307 /** 1308 * dm_pci_map_bar() - get a virtual address associated with a BAR region 1309 * 1310 * Looks up a base address register and finds the physical memory address 1311 * that corresponds to it 1312 * 1313 * @dev: Device to check 1314 * @bar: Bar number to read (numbered from 0) 1315 * @flags: Flags for the region type (PCI_REGION_...) 1316 * @return: pointer to the virtual address to use 1317 */ 1318 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); 1319 1320 /** 1321 * dm_pci_find_next_capability() - find a capability starting from an offset 1322 * 1323 * Tell if a device supports a given PCI capability. Returns the 1324 * address of the requested capability structure within the device's 1325 * PCI configuration space or 0 in case the device does not support it. 1326 * 1327 * Possible values for @cap: 1328 * 1329 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1330 * %PCI_CAP_ID_PCIX PCI-X 1331 * %PCI_CAP_ID_EXP PCI Express 1332 * %PCI_CAP_ID_MSIX MSI-X 1333 * 1334 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1335 * 1336 * @dev: PCI device to query 1337 * @start: offset to start from 1338 * @cap: capability code 1339 * @return: capability address or 0 if not supported 1340 */ 1341 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap); 1342 1343 /** 1344 * dm_pci_find_capability() - find a capability 1345 * 1346 * Tell if a device supports a given PCI capability. Returns the 1347 * address of the requested capability structure within the device's 1348 * PCI configuration space or 0 in case the device does not support it. 1349 * 1350 * Possible values for @cap: 1351 * 1352 * %PCI_CAP_ID_MSI Message Signalled Interrupts 1353 * %PCI_CAP_ID_PCIX PCI-X 1354 * %PCI_CAP_ID_EXP PCI Express 1355 * %PCI_CAP_ID_MSIX MSI-X 1356 * 1357 * See PCI_CAP_ID_xxx for the complete capability ID codes. 1358 * 1359 * @dev: PCI device to query 1360 * @cap: capability code 1361 * @return: capability address or 0 if not supported 1362 */ 1363 int dm_pci_find_capability(struct udevice *dev, int cap); 1364 1365 /** 1366 * dm_pci_find_next_ext_capability() - find an extended capability 1367 * starting from an offset 1368 * 1369 * Tell if a device supports a given PCI express extended capability. 1370 * Returns the address of the requested extended capability structure 1371 * within the device's PCI configuration space or 0 in case the device 1372 * does not support it. 1373 * 1374 * Possible values for @cap: 1375 * 1376 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1377 * %PCI_EXT_CAP_ID_VC Virtual Channel 1378 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1379 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1380 * 1381 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1382 * 1383 * @dev: PCI device to query 1384 * @start: offset to start from 1385 * @cap: extended capability code 1386 * @return: extended capability address or 0 if not supported 1387 */ 1388 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap); 1389 1390 /** 1391 * dm_pci_find_ext_capability() - find an extended capability 1392 * 1393 * Tell if a device supports a given PCI express extended capability. 1394 * Returns the address of the requested extended capability structure 1395 * within the device's PCI configuration space or 0 in case the device 1396 * does not support it. 1397 * 1398 * Possible values for @cap: 1399 * 1400 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting 1401 * %PCI_EXT_CAP_ID_VC Virtual Channel 1402 * %PCI_EXT_CAP_ID_DSN Device Serial Number 1403 * %PCI_EXT_CAP_ID_PWR Power Budgeting 1404 * 1405 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes. 1406 * 1407 * @dev: PCI device to query 1408 * @cap: extended capability code 1409 * @return: extended capability address or 0 if not supported 1410 */ 1411 int dm_pci_find_ext_capability(struct udevice *dev, int cap); 1412 1413 #define dm_pci_virt_to_bus(dev, addr, flags) \ 1414 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) 1415 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 1416 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \ 1417 (len), (map_flags)) 1418 1419 #define dm_pci_phys_to_mem(dev, addr) \ 1420 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 1421 #define dm_pci_mem_to_phys(dev, addr) \ 1422 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 1423 #define dm_pci_phys_to_io(dev, addr) \ 1424 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 1425 #define dm_pci_io_to_phys(dev, addr) \ 1426 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 1427 1428 #define dm_pci_virt_to_mem(dev, addr) \ 1429 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 1430 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ 1431 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 1432 #define dm_pci_virt_to_io(dev, addr) \ 1433 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 1434 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \ 1435 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 1436 1437 /** 1438 * dm_pci_find_device() - find a device by vendor/device ID 1439 * 1440 * @vendor: Vendor ID 1441 * @device: Device ID 1442 * @index: 0 to find the first match, 1 for second, etc. 1443 * @devp: Returns pointer to the device, if found 1444 * @return 0 if found, -ve on error 1445 */ 1446 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, 1447 struct udevice **devp); 1448 1449 /** 1450 * dm_pci_find_class() - find a device by class 1451 * 1452 * @find_class: 3-byte (24-bit) class value to find 1453 * @index: 0 to find the first match, 1 for second, etc. 1454 * @devp: Returns pointer to the device, if found 1455 * @return 0 if found, -ve on error 1456 */ 1457 int dm_pci_find_class(uint find_class, int index, struct udevice **devp); 1458 1459 /** 1460 * struct dm_pci_emul_ops - PCI device emulator operations 1461 */ 1462 struct dm_pci_emul_ops { 1463 /** 1464 * get_devfn(): Check which device and function this emulators 1465 * 1466 * @dev: device to check 1467 * @return the device and function this emulates, or -ve on error 1468 */ 1469 int (*get_devfn)(struct udevice *dev); 1470 /** 1471 * read_config() - Read a PCI configuration value 1472 * 1473 * @dev: Emulated device to read from 1474 * @offset: Byte offset within the device's configuration space 1475 * @valuep: Place to put the returned value 1476 * @size: Access size 1477 * @return 0 if OK, -ve on error 1478 */ 1479 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep, 1480 enum pci_size_t size); 1481 /** 1482 * write_config() - Write a PCI configuration value 1483 * 1484 * @dev: Emulated device to write to 1485 * @offset: Byte offset within the device's configuration space 1486 * @value: Value to write 1487 * @size: Access size 1488 * @return 0 if OK, -ve on error 1489 */ 1490 int (*write_config)(struct udevice *dev, uint offset, ulong value, 1491 enum pci_size_t size); 1492 /** 1493 * read_io() - Read a PCI I/O value 1494 * 1495 * @dev: Emulated device to read from 1496 * @addr: I/O address to read 1497 * @valuep: Place to put the returned value 1498 * @size: Access size 1499 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1500 * other -ve value on error 1501 */ 1502 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, 1503 enum pci_size_t size); 1504 /** 1505 * write_io() - Write a PCI I/O value 1506 * 1507 * @dev: Emulated device to write from 1508 * @addr: I/O address to write 1509 * @value: Value to write 1510 * @size: Access size 1511 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1512 * other -ve value on error 1513 */ 1514 int (*write_io)(struct udevice *dev, unsigned int addr, 1515 ulong value, enum pci_size_t size); 1516 /** 1517 * map_physmem() - Map a device into sandbox memory 1518 * 1519 * @dev: Emulated device to map 1520 * @addr: Memory address, normally corresponding to a PCI BAR. 1521 * The device should have been configured to have a BAR 1522 * at this address. 1523 * @lenp: On entry, the size of the area to map, On exit it is 1524 * updated to the size actually mapped, which may be less 1525 * if the device has less space 1526 * @ptrp: Returns a pointer to the mapped address. The device's 1527 * space can be accessed as @lenp bytes starting here 1528 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1529 * other -ve value on error 1530 */ 1531 int (*map_physmem)(struct udevice *dev, phys_addr_t addr, 1532 unsigned long *lenp, void **ptrp); 1533 /** 1534 * unmap_physmem() - undo a memory mapping 1535 * 1536 * This must be called after map_physmem() to undo the mapping. 1537 * Some devices can use this to check what has been written into 1538 * their mapped memory and perform an operations they require on it. 1539 * In this way, map/unmap can be used as a sort of handshake between 1540 * the emulated device and its users. 1541 * 1542 * @dev: Emuated device to unmap 1543 * @vaddr: Mapped memory address, as passed to map_physmem() 1544 * @len: Size of area mapped, as returned by map_physmem() 1545 * @return 0 if OK, -ve on error 1546 */ 1547 int (*unmap_physmem)(struct udevice *dev, const void *vaddr, 1548 unsigned long len); 1549 }; 1550 1551 /* Get access to a PCI device emulator's operations */ 1552 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) 1553 1554 /** 1555 * sandbox_pci_get_emul() - Get the emulation device for a PCI device 1556 * 1557 * Searches for a suitable emulator for the given PCI bus device 1558 * 1559 * @bus: PCI bus to search 1560 * @find_devfn: PCI device and function address (PCI_DEVFN()) 1561 * @containerp: Returns container device if found 1562 * @emulp: Returns emulated device if found 1563 * @return 0 if found, -ENODEV if not found 1564 */ 1565 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, 1566 struct udevice **containerp, struct udevice **emulp); 1567 1568 /** 1569 * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device 1570 * 1571 * Get devfn from fdt_pci_addr of the specifified device 1572 * 1573 * @dev: PCI device 1574 * @return devfn in bits 15...8 if found, -ENODEV if not found 1575 */ 1576 int pci_get_devfn(struct udevice *dev); 1577 1578 #endif /* CONFIG_DM_PCI */ 1579 1580 /** 1581 * PCI_DEVICE - macro used to describe a specific pci device 1582 * @vend: the 16 bit PCI Vendor ID 1583 * @dev: the 16 bit PCI Device ID 1584 * 1585 * This macro is used to create a struct pci_device_id that matches a 1586 * specific device. The subvendor and subdevice fields will be set to 1587 * PCI_ANY_ID. 1588 */ 1589 #define PCI_DEVICE(vend, dev) \ 1590 .vendor = (vend), .device = (dev), \ 1591 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1592 1593 /** 1594 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 1595 * @vend: the 16 bit PCI Vendor ID 1596 * @dev: the 16 bit PCI Device ID 1597 * @subvend: the 16 bit PCI Subvendor ID 1598 * @subdev: the 16 bit PCI Subdevice ID 1599 * 1600 * This macro is used to create a struct pci_device_id that matches a 1601 * specific device with subsystem information. 1602 */ 1603 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1604 .vendor = (vend), .device = (dev), \ 1605 .subvendor = (subvend), .subdevice = (subdev) 1606 1607 /** 1608 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 1609 * @dev_class: the class, subclass, prog-if triple for this device 1610 * @dev_class_mask: the class mask for this device 1611 * 1612 * This macro is used to create a struct pci_device_id that matches a 1613 * specific PCI class. The vendor, device, subvendor, and subdevice 1614 * fields will be set to PCI_ANY_ID. 1615 */ 1616 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ 1617 .class = (dev_class), .class_mask = (dev_class_mask), \ 1618 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1619 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1620 1621 /** 1622 * PCI_VDEVICE - macro used to describe a specific pci device in short form 1623 * @vend: the vendor name 1624 * @dev: the 16 bit PCI Device ID 1625 * 1626 * This macro is used to create a struct pci_device_id that matches a 1627 * specific PCI device. The subvendor, and subdevice fields will be set 1628 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1629 * private data. 1630 */ 1631 1632 #define PCI_VDEVICE(vend, dev) \ 1633 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1634 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1635 1636 /** 1637 * struct pci_driver_entry - Matches a driver to its pci_device_id list 1638 * @driver: Driver to use 1639 * @match: List of match records for this driver, terminated by {} 1640 */ 1641 struct pci_driver_entry { 1642 struct driver *driver; 1643 const struct pci_device_id *match; 1644 }; 1645 1646 #define U_BOOT_PCI_DEVICE(__name, __match) \ 1647 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\ 1648 .driver = llsym(struct driver, __name, driver), \ 1649 .match = __match, \ 1650 } 1651 1652 #endif /* __ASSEMBLY__ */ 1653 #endif /* _PCI_H */ 1654