1 /* 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 3 * Andreas Heppel <aheppel@sysgo.de> 4 * 5 * (C) Copyright 2002 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _PCI_H 12 #define _PCI_H 13 14 #define PCI_CFG_SPACE_SIZE 256 15 #define PCI_CFG_SPACE_EXP_SIZE 4096 16 17 /* 18 * Under PCI, each device has 256 bytes of configuration address space, 19 * of which the first 64 bytes are standardized as follows: 20 */ 21 #define PCI_VENDOR_ID 0x00 /* 16 bits */ 22 #define PCI_DEVICE_ID 0x02 /* 16 bits */ 23 #define PCI_COMMAND 0x04 /* 16 bits */ 24 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ 25 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ 26 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ 27 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ 28 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */ 29 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ 30 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ 31 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ 32 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */ 33 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 34 35 #define PCI_STATUS 0x06 /* 16 bits */ 36 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ 37 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ 38 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ 39 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 40 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */ 41 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ 42 #define PCI_STATUS_DEVSEL_FAST 0x000 43 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 44 #define PCI_STATUS_DEVSEL_SLOW 0x400 45 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ 46 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */ 47 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */ 48 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */ 49 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */ 50 51 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 52 revision */ 53 #define PCI_REVISION_ID 0x08 /* Revision ID */ 54 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ 55 #define PCI_CLASS_DEVICE 0x0a /* Device class */ 56 #define PCI_CLASS_CODE 0x0b /* Device class code */ 57 #define PCI_CLASS_CODE_TOO_OLD 0x00 58 #define PCI_CLASS_CODE_STORAGE 0x01 59 #define PCI_CLASS_CODE_NETWORK 0x02 60 #define PCI_CLASS_CODE_DISPLAY 0x03 61 #define PCI_CLASS_CODE_MULTIMEDIA 0x04 62 #define PCI_CLASS_CODE_MEMORY 0x05 63 #define PCI_CLASS_CODE_BRIDGE 0x06 64 #define PCI_CLASS_CODE_COMM 0x07 65 #define PCI_CLASS_CODE_PERIPHERAL 0x08 66 #define PCI_CLASS_CODE_INPUT 0x09 67 #define PCI_CLASS_CODE_DOCKING 0x0A 68 #define PCI_CLASS_CODE_PROCESSOR 0x0B 69 #define PCI_CLASS_CODE_SERIAL 0x0C 70 #define PCI_CLASS_CODE_WIRELESS 0x0D 71 #define PCI_CLASS_CODE_I2O 0x0E 72 #define PCI_CLASS_CODE_SATELLITE 0x0F 73 #define PCI_CLASS_CODE_CRYPTO 0x10 74 #define PCI_CLASS_CODE_DATA 0x11 75 /* Base Class 0x12 - 0xFE is reserved */ 76 #define PCI_CLASS_CODE_OTHER 0xFF 77 78 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */ 79 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00 80 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01 81 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00 82 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01 83 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02 84 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03 85 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04 86 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05 87 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06 88 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07 89 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80 90 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00 91 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01 92 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02 93 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03 94 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04 95 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05 96 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06 97 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80 98 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00 99 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01 100 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02 101 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80 102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00 103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01 104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02 105 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80 106 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00 107 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01 108 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80 109 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00 110 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01 111 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02 112 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03 113 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04 114 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05 115 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06 116 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07 117 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08 118 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09 119 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A 120 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80 121 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00 122 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01 123 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02 124 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03 125 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04 126 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05 127 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80 128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00 129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01 130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02 131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03 132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04 133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05 134 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80 135 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00 136 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01 137 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02 138 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03 139 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04 140 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80 141 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00 142 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80 143 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00 144 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01 145 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02 146 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10 147 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20 148 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30 149 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40 150 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00 151 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01 152 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02 153 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03 154 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04 155 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05 156 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06 157 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07 158 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08 159 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09 160 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00 161 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01 162 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10 163 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11 164 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12 165 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20 166 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21 167 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80 168 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00 169 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01 170 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02 171 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03 172 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04 173 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00 174 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10 175 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80 176 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00 177 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01 178 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10 179 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20 180 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80 181 182 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */ 183 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */ 184 #define PCI_HEADER_TYPE 0x0e /* 8 bits */ 185 #define PCI_HEADER_TYPE_NORMAL 0 186 #define PCI_HEADER_TYPE_BRIDGE 1 187 #define PCI_HEADER_TYPE_CARDBUS 2 188 189 #define PCI_BIST 0x0f /* 8 bits */ 190 #define PCI_BIST_CODE_MASK 0x0f /* Return result */ 191 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */ 192 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */ 193 194 /* 195 * Base addresses specify locations in memory or I/O space. 196 * Decoded size can be determined by writing a value of 197 * 0xffffffff to the register, and reading it back. Only 198 * 1 bits are decoded. 199 */ 200 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */ 201 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */ 202 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */ 203 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */ 204 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */ 205 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */ 206 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */ 207 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 208 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 209 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 210 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */ 211 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */ 212 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */ 213 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 214 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL) 215 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL) 216 /* bit 1 is reserved if address_space = 1 */ 217 218 /* Header type 0 (normal devices) */ 219 #define PCI_CARDBUS_CIS 0x28 220 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 221 #define PCI_SUBSYSTEM_ID 0x2e 222 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */ 223 #define PCI_ROM_ADDRESS_ENABLE 0x01 224 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL) 225 226 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */ 227 228 /* 0x35-0x3b are reserved */ 229 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ 230 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ 231 #define PCI_MIN_GNT 0x3e /* 8 bits */ 232 #define PCI_MAX_LAT 0x3f /* 8 bits */ 233 234 #define PCI_INTERRUPT_LINE_DISABLE 0xff 235 236 /* Header type 1 (PCI-to-PCI bridges) */ 237 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */ 238 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */ 239 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */ 240 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */ 241 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */ 242 #define PCI_IO_LIMIT 0x1d 243 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */ 244 #define PCI_IO_RANGE_TYPE_16 0x00 245 #define PCI_IO_RANGE_TYPE_32 0x01 246 #define PCI_IO_RANGE_MASK ~0x0f 247 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */ 248 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */ 249 #define PCI_MEMORY_LIMIT 0x22 250 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f 251 #define PCI_MEMORY_RANGE_MASK ~0x0f 252 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ 253 #define PCI_PREF_MEMORY_LIMIT 0x26 254 #define PCI_PREF_RANGE_TYPE_MASK 0x0f 255 #define PCI_PREF_RANGE_TYPE_32 0x00 256 #define PCI_PREF_RANGE_TYPE_64 0x01 257 #define PCI_PREF_RANGE_MASK ~0x0f 258 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ 259 #define PCI_PREF_LIMIT_UPPER32 0x2c 260 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */ 261 #define PCI_IO_LIMIT_UPPER16 0x32 262 /* 0x34 same as for htype 0 */ 263 /* 0x35-0x3b is reserved */ 264 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ 265 /* 0x3c-0x3d are same as for htype 0 */ 266 #define PCI_BRIDGE_CONTROL 0x3e 267 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ 268 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ 269 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ 270 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ 271 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ 272 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ 273 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */ 274 275 /* From 440ep */ 276 #define PCI_ERREN 0x48 /* Error Enable */ 277 #define PCI_ERRSTS 0x49 /* Error Status */ 278 #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */ 279 #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */ 280 #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */ 281 #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */ 282 #define PCI_CAPID 0x58 /* Capability Identifier */ 283 #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */ 284 #define PCI_PMC 0x5A /* Power Management Capabilities */ 285 #define PCI_PMCSR 0x5C /* Power Management Control Status */ 286 #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */ 287 #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */ 288 #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */ 289 290 /* Header type 2 (CardBus bridges) */ 291 #define PCI_CB_CAPABILITY_LIST 0x14 292 /* 0x15 reserved */ 293 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ 294 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ 295 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ 296 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ 297 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ 298 #define PCI_CB_MEMORY_BASE_0 0x1c 299 #define PCI_CB_MEMORY_LIMIT_0 0x20 300 #define PCI_CB_MEMORY_BASE_1 0x24 301 #define PCI_CB_MEMORY_LIMIT_1 0x28 302 #define PCI_CB_IO_BASE_0 0x2c 303 #define PCI_CB_IO_BASE_0_HI 0x2e 304 #define PCI_CB_IO_LIMIT_0 0x30 305 #define PCI_CB_IO_LIMIT_0_HI 0x32 306 #define PCI_CB_IO_BASE_1 0x34 307 #define PCI_CB_IO_BASE_1_HI 0x36 308 #define PCI_CB_IO_LIMIT_1 0x38 309 #define PCI_CB_IO_LIMIT_1_HI 0x3a 310 #define PCI_CB_IO_RANGE_MASK ~0x03 311 /* 0x3c-0x3d are same as for htype 0 */ 312 #define PCI_CB_BRIDGE_CONTROL 0x3e 313 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */ 314 #define PCI_CB_BRIDGE_CTL_SERR 0x02 315 #define PCI_CB_BRIDGE_CTL_ISA 0x04 316 #define PCI_CB_BRIDGE_CTL_VGA 0x08 317 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 318 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */ 319 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */ 320 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */ 321 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 322 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 323 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 324 #define PCI_CB_SUBSYSTEM_ID 0x42 325 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */ 326 /* 0x48-0x7f reserved */ 327 328 /* Capability lists */ 329 330 #define PCI_CAP_LIST_ID 0 /* Capability ID */ 331 #define PCI_CAP_ID_PM 0x01 /* Power Management */ 332 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ 333 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ 334 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ 335 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */ 336 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ 337 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */ 338 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ 339 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */ 340 #define PCI_CAP_SIZEOF 4 341 342 /* Power Management Registers */ 343 344 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */ 345 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */ 346 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */ 347 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */ 348 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ 349 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ 350 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */ 351 #define PCI_PM_CTRL 4 /* PM control and status register */ 352 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ 353 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ 354 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ 355 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ 356 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ 357 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */ 358 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */ 359 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */ 360 #define PCI_PM_DATA_REGISTER 7 /* (??) */ 361 #define PCI_PM_SIZEOF 8 362 363 /* AGP registers */ 364 365 #define PCI_AGP_VERSION 2 /* BCD version number */ 366 #define PCI_AGP_RFU 3 /* Rest of capability flags */ 367 #define PCI_AGP_STATUS 4 /* Status register */ 368 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */ 369 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */ 370 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */ 371 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */ 372 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */ 373 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */ 374 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */ 375 #define PCI_AGP_COMMAND 8 /* Control register */ 376 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */ 377 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ 378 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */ 379 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */ 380 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */ 381 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */ 382 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */ 383 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */ 384 #define PCI_AGP_SIZEOF 12 385 386 /* PCI-X registers */ 387 388 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */ 389 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */ 390 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */ 391 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */ 392 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */ 393 394 395 /* Slot Identification */ 396 397 #define PCI_SID_ESR 2 /* Expansion Slot Register */ 398 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */ 399 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ 400 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ 401 402 /* Message Signalled Interrupts registers */ 403 404 #define PCI_MSI_FLAGS 2 /* Various flags */ 405 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */ 406 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */ 407 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */ 408 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */ 409 #define PCI_MSI_RFU 3 /* Rest of capability flags */ 410 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ 411 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */ 412 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */ 413 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ 414 415 #define PCI_MAX_PCI_DEVICES 32 416 #define PCI_MAX_PCI_FUNCTIONS 8 417 418 #define PCI_FIND_CAP_TTL 0x48 419 #define CAP_START_POS 0x40 420 421 /* Extended Capabilities (PCI-X 2.0 and Express) */ 422 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 423 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 424 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 425 426 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ 427 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */ 428 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ 429 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */ 430 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */ 431 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */ 432 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */ 433 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */ 434 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */ 435 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */ 436 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */ 437 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */ 438 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */ 439 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */ 440 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */ 441 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ 442 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */ 443 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */ 444 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ 445 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */ 446 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */ 447 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */ 448 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */ 449 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */ 450 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */ 451 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */ 452 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ 453 454 /* Include the ID list */ 455 456 #include <pci_ids.h> 457 458 #ifndef __ASSEMBLY__ 459 460 #ifdef CONFIG_SYS_PCI_64BIT 461 typedef u64 pci_addr_t; 462 typedef u64 pci_size_t; 463 #else 464 typedef u32 pci_addr_t; 465 typedef u32 pci_size_t; 466 #endif 467 468 struct pci_region { 469 pci_addr_t bus_start; /* Start on the bus */ 470 phys_addr_t phys_start; /* Start in physical address space */ 471 pci_size_t size; /* Size */ 472 unsigned long flags; /* Resource flags */ 473 474 pci_addr_t bus_lower; 475 }; 476 477 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */ 478 #define PCI_REGION_IO 0x00000001 /* PCI IO space */ 479 #define PCI_REGION_TYPE 0x00000001 480 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ 481 482 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ 483 #define PCI_REGION_RO 0x00000200 /* Read-only memory */ 484 485 static inline void pci_set_region(struct pci_region *reg, 486 pci_addr_t bus_start, 487 phys_addr_t phys_start, 488 pci_size_t size, 489 unsigned long flags) { 490 reg->bus_start = bus_start; 491 reg->phys_start = phys_start; 492 reg->size = size; 493 reg->flags = flags; 494 } 495 496 typedef int pci_dev_t; 497 498 #define PCI_BUS(d) (((d) >> 16) & 0xff) 499 #define PCI_DEV(d) (((d) >> 11) & 0x1f) 500 #define PCI_FUNC(d) (((d) >> 8) & 0x7) 501 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8) 502 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff) 503 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn)) 504 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) 505 #define PCI_VENDEV(v, d) (((v) << 16) | (d)) 506 #define PCI_ANY_ID (~0) 507 508 struct pci_device_id { 509 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 510 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */ 511 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */ 512 unsigned long driver_data; /* Data private to the driver */ 513 }; 514 515 struct pci_controller; 516 517 struct pci_config_table { 518 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */ 519 unsigned int class; /* Class ID, or PCI_ANY_ID */ 520 unsigned int bus; /* Bus number, or PCI_ANY_ID */ 521 unsigned int dev; /* Device number, or PCI_ANY_ID */ 522 unsigned int func; /* Function number, or PCI_ANY_ID */ 523 524 void (*config_device)(struct pci_controller* hose, pci_dev_t dev, 525 struct pci_config_table *); 526 unsigned long priv[3]; 527 }; 528 529 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, 530 struct pci_config_table *); 531 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, 532 struct pci_config_table *); 533 534 #define MAX_PCI_REGIONS 7 535 536 #define INDIRECT_TYPE_NO_PCIE_LINK 1 537 538 /* 539 * Structure of a PCI controller (host bridge) 540 * 541 * With driver model this is dev_get_uclass_priv(bus) 542 */ 543 struct pci_controller { 544 #ifdef CONFIG_DM_PCI 545 struct udevice *bus; 546 struct udevice *ctlr; 547 #else 548 struct pci_controller *next; 549 #endif 550 551 int first_busno; 552 int last_busno; 553 554 volatile unsigned int *cfg_addr; 555 volatile unsigned char *cfg_data; 556 557 int indirect_type; 558 559 /* 560 * TODO(sjg@chromium.org): With driver model we use struct 561 * pci_controller for both the controller and any bridge devices 562 * attached to it. But there is only one region list and it is in the 563 * top-level controller. 564 * 565 * This could be changed so that struct pci_controller is only used 566 * for PCI controllers and a separate UCLASS (or perhaps 567 * UCLASS_PCI_GENERIC) is used for bridges. 568 */ 569 struct pci_region regions[MAX_PCI_REGIONS]; 570 int region_count; 571 572 struct pci_config_table *config_table; 573 574 void (*fixup_irq)(struct pci_controller *, pci_dev_t); 575 #ifndef CONFIG_DM_PCI 576 /* Low-level architecture-dependent routines */ 577 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *); 578 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *); 579 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *); 580 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8); 581 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16); 582 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32); 583 #endif 584 585 /* Used by auto config */ 586 struct pci_region *pci_mem, *pci_io, *pci_prefetch; 587 588 #ifndef CONFIG_DM_PCI 589 int current_busno; 590 591 void *priv_data; 592 #endif 593 }; 594 595 #ifndef CONFIG_DM_PCI 596 static inline void pci_set_ops(struct pci_controller *hose, 597 int (*read_byte)(struct pci_controller*, 598 pci_dev_t, int where, u8 *), 599 int (*read_word)(struct pci_controller*, 600 pci_dev_t, int where, u16 *), 601 int (*read_dword)(struct pci_controller*, 602 pci_dev_t, int where, u32 *), 603 int (*write_byte)(struct pci_controller*, 604 pci_dev_t, int where, u8), 605 int (*write_word)(struct pci_controller*, 606 pci_dev_t, int where, u16), 607 int (*write_dword)(struct pci_controller*, 608 pci_dev_t, int where, u32)) { 609 hose->read_byte = read_byte; 610 hose->read_word = read_word; 611 hose->read_dword = read_dword; 612 hose->write_byte = write_byte; 613 hose->write_word = write_word; 614 hose->write_dword = write_dword; 615 } 616 #endif 617 618 #ifdef CONFIG_PCI_INDIRECT_BRIDGE 619 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data); 620 #endif 621 622 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 623 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose, 624 pci_addr_t addr, unsigned long flags); 625 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, 626 phys_addr_t addr, unsigned long flags); 627 628 #define pci_phys_to_bus(dev, addr, flags) \ 629 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 630 #define pci_bus_to_phys(dev, addr, flags) \ 631 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) 632 633 #define pci_virt_to_bus(dev, addr, flags) \ 634 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ 635 (virt_to_phys(addr)), (flags)) 636 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 637 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ 638 (addr), (flags)), \ 639 (len), (map_flags)) 640 641 #define pci_phys_to_mem(dev, addr) \ 642 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 643 #define pci_mem_to_phys(dev, addr) \ 644 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 645 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 646 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 647 648 #define pci_virt_to_mem(dev, addr) \ 649 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 650 #define pci_mem_to_virt(dev, addr, len, map_flags) \ 651 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 652 #define pci_virt_to_io(dev, addr) \ 653 pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 654 #define pci_io_to_virt(dev, addr, len, map_flags) \ 655 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 656 657 /* For driver model these are defined in macros in pci_compat.c */ 658 extern int pci_hose_read_config_byte(struct pci_controller *hose, 659 pci_dev_t dev, int where, u8 *val); 660 extern int pci_hose_read_config_word(struct pci_controller *hose, 661 pci_dev_t dev, int where, u16 *val); 662 extern int pci_hose_read_config_dword(struct pci_controller *hose, 663 pci_dev_t dev, int where, u32 *val); 664 extern int pci_hose_write_config_byte(struct pci_controller *hose, 665 pci_dev_t dev, int where, u8 val); 666 extern int pci_hose_write_config_word(struct pci_controller *hose, 667 pci_dev_t dev, int where, u16 val); 668 extern int pci_hose_write_config_dword(struct pci_controller *hose, 669 pci_dev_t dev, int where, u32 val); 670 #endif 671 672 #ifndef CONFIG_DM_PCI 673 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val); 674 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val); 675 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val); 676 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val); 677 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val); 678 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val); 679 #endif 680 681 void pciauto_region_init(struct pci_region *res); 682 void pciauto_region_align(struct pci_region *res, pci_size_t size); 683 void pciauto_config_init(struct pci_controller *hose); 684 int pciauto_region_allocate(struct pci_region *res, pci_size_t size, 685 pci_addr_t *bar); 686 687 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 688 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose, 689 pci_dev_t dev, int where, u8 *val); 690 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose, 691 pci_dev_t dev, int where, u16 *val); 692 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, 693 pci_dev_t dev, int where, u8 val); 694 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, 695 pci_dev_t dev, int where, u16 val); 696 697 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); 698 extern void pci_register_hose(struct pci_controller* hose); 699 extern struct pci_controller* pci_bus_to_hose(int bus); 700 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); 701 extern struct pci_controller *pci_get_hose_head(void); 702 703 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); 704 extern int pci_hose_scan(struct pci_controller *hose); 705 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus); 706 707 extern void pciauto_setup_device(struct pci_controller *hose, 708 pci_dev_t dev, int bars_num, 709 struct pci_region *mem, 710 struct pci_region *prefetch, 711 struct pci_region *io); 712 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose, 713 pci_dev_t dev, int sub_bus); 714 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose, 715 pci_dev_t dev, int sub_bus); 716 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev); 717 718 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index); 719 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index); 720 pci_dev_t pci_find_class(unsigned int find_class, int index); 721 722 extern int pci_hose_config_device(struct pci_controller *hose, 723 pci_dev_t dev, 724 unsigned long io, 725 pci_addr_t mem, 726 unsigned long command); 727 728 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev, 729 int cap); 730 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev, 731 u8 hdr_type); 732 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, 733 int cap); 734 735 int pci_find_next_ext_capability(struct pci_controller *hose, 736 pci_dev_t dev, int start, int cap); 737 int pci_hose_find_ext_capability(struct pci_controller *hose, 738 pci_dev_t dev, int cap); 739 740 #ifdef CONFIG_PCI_FIXUP_DEV 741 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, 742 unsigned short vendor, 743 unsigned short device, 744 unsigned short class); 745 #endif 746 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */ 747 748 const char * pci_class_str(u8 class); 749 int pci_last_busno(void); 750 751 #ifdef CONFIG_MPC85xx 752 extern void pci_mpc85xx_init (struct pci_controller *hose); 753 #endif 754 755 #ifdef CONFIG_PCIE_IMX 756 extern void imx_pcie_remove(void); 757 #endif 758 759 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) 760 /** 761 * pci_write_bar32() - Write the address of a BAR including control bits 762 * 763 * This writes a raw address (with control bits) to a bar. This can be used 764 * with devices which require hard-coded addresses, not part of the normal 765 * PCI enumeration process. 766 * 767 * @hose: PCI hose to use 768 * @dev: PCI device to update 769 * @barnum: BAR number (0-5) 770 * @addr: BAR address with control bits 771 */ 772 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum, 773 u32 addr); 774 775 /** 776 * pci_read_bar32() - read the address of a bar 777 * 778 * @hose: PCI hose to use 779 * @dev: PCI device to inspect 780 * @barnum: BAR number (0-5) 781 * @return address of the bar, masking out any control bits 782 * */ 783 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum); 784 785 /** 786 * pci_hose_find_devices() - Find devices by vendor/device ID 787 * 788 * @hose: PCI hose to search 789 * @busnum: Bus number to search 790 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 791 * @indexp: Pointer to device index to find. To find the first matching 792 * device, pass 0; to find the second, pass 1, etc. This 793 * parameter is decremented for each non-matching device so 794 * can be called repeatedly. 795 */ 796 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum, 797 struct pci_device_id *ids, int *indexp); 798 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */ 799 800 /* Access sizes for PCI reads and writes */ 801 enum pci_size_t { 802 PCI_SIZE_8, 803 PCI_SIZE_16, 804 PCI_SIZE_32, 805 }; 806 807 struct udevice; 808 809 #ifdef CONFIG_DM_PCI 810 /** 811 * struct pci_child_platdata - information stored about each PCI device 812 * 813 * Every device on a PCI bus has this per-child data. 814 * 815 * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a 816 * PCI bus (i.e. UCLASS_PCI) 817 * 818 * @devfn: Encoded device and function index - see PCI_DEVFN() 819 * @vendor: PCI vendor ID (see pci_ids.h) 820 * @device: PCI device ID (see pci_ids.h) 821 * @class: PCI class, 3 bytes: (base, sub, prog-if) 822 */ 823 struct pci_child_platdata { 824 int devfn; 825 unsigned short vendor; 826 unsigned short device; 827 unsigned int class; 828 }; 829 830 /* PCI bus operations */ 831 struct dm_pci_ops { 832 /** 833 * read_config() - Read a PCI configuration value 834 * 835 * PCI buses must support reading and writing configuration values 836 * so that the bus can be scanned and its devices configured. 837 * 838 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always. 839 * If bridges exist it is possible to use the top-level bus to 840 * access a sub-bus. In that case @bus will be the top-level bus 841 * and PCI_BUS(bdf) will be a different (higher) value 842 * 843 * @bus: Bus to read from 844 * @bdf: Bus, device and function to read 845 * @offset: Byte offset within the device's configuration space 846 * @valuep: Place to put the returned value 847 * @size: Access size 848 * @return 0 if OK, -ve on error 849 */ 850 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 851 ulong *valuep, enum pci_size_t size); 852 /** 853 * write_config() - Write a PCI configuration value 854 * 855 * @bus: Bus to write to 856 * @bdf: Bus, device and function to write 857 * @offset: Byte offset within the device's configuration space 858 * @value: Value to write 859 * @size: Access size 860 * @return 0 if OK, -ve on error 861 */ 862 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset, 863 ulong value, enum pci_size_t size); 864 }; 865 866 /* Get access to a PCI bus' operations */ 867 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops) 868 869 /** 870 * dm_pci_get_bdf() - Get the BDF value for a device 871 * 872 * @dev: Device to check 873 * @return bus/device/function value (see PCI_BDF()) 874 */ 875 pci_dev_t dm_pci_get_bdf(struct udevice *dev); 876 877 /** 878 * pci_bind_bus_devices() - scan a PCI bus and bind devices 879 * 880 * Scan a PCI bus looking for devices. Bind each one that is found. If 881 * devices are already bound that match the scanned devices, just update the 882 * child data so that the device can be used correctly (this happens when 883 * the device tree describes devices we expect to see on the bus). 884 * 885 * Devices that are bound in this way will use a generic PCI driver which 886 * does nothing. The device can still be accessed but will not provide any 887 * driver interface. 888 * 889 * @bus: Bus containing devices to bind 890 * @return 0 if OK, -ve on error 891 */ 892 int pci_bind_bus_devices(struct udevice *bus); 893 894 /** 895 * pci_auto_config_devices() - configure bus devices ready for use 896 * 897 * This works through all devices on a bus by scanning the driver model 898 * data structures (normally these have been set up by pci_bind_bus_devices() 899 * earlier). 900 * 901 * Space is allocated for each PCI base address register (BAR) so that the 902 * devices are mapped into memory and I/O space ready for use. 903 * 904 * @bus: Bus containing devices to bind 905 * @return 0 if OK, -ve on error 906 */ 907 int pci_auto_config_devices(struct udevice *bus); 908 909 /** 910 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address 911 * 912 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 913 * @devp: Returns the device for this address, if found 914 * @return 0 if OK, -ENODEV if not found 915 */ 916 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp); 917 918 /** 919 * pci_bus_find_devfn() - Find a device on a bus 920 * 921 * @find_devfn: PCI device address (device and function only) 922 * @devp: Returns the device for this address, if found 923 * @return 0 if OK, -ENODEV if not found 924 */ 925 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn, 926 struct udevice **devp); 927 928 /** 929 * pci_find_first_device() - return the first available PCI device 930 * 931 * This function and pci_find_first_device() allow iteration through all 932 * available PCI devices on all buses. Assuming there are any, this will 933 * return the first one. 934 * 935 * @devp: Set to the first available device, or NULL if no more are left 936 * or we got an error 937 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 938 */ 939 int pci_find_first_device(struct udevice **devp); 940 941 /** 942 * pci_find_next_device() - return the next available PCI device 943 * 944 * Finds the next available PCI device after the one supplied, or sets @devp 945 * to NULL if there are no more. 946 * 947 * @devp: On entry, the last device returned. Set to the next available 948 * device, or NULL if no more are left or we got an error 949 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe) 950 */ 951 int pci_find_next_device(struct udevice **devp); 952 953 /** 954 * pci_get_ff() - Returns a mask for the given access size 955 * 956 * @size: Access size 957 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for 958 * PCI_SIZE_32 959 */ 960 int pci_get_ff(enum pci_size_t size); 961 962 /** 963 * pci_bus_find_devices () - Find devices on a bus 964 * 965 * @bus: Bus to search 966 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 967 * @indexp: Pointer to device index to find. To find the first matching 968 * device, pass 0; to find the second, pass 1, etc. This 969 * parameter is decremented for each non-matching device so 970 * can be called repeatedly. 971 * @devp: Returns matching device if found 972 * @return 0 if found, -ENODEV if not 973 */ 974 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids, 975 int *indexp, struct udevice **devp); 976 977 /** 978 * pci_find_device_id() - Find a device on any bus 979 * 980 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record 981 * @index: Index number of device to find, 0 for the first match, 1 for 982 * the second, etc. 983 * @devp: Returns matching device if found 984 * @return 0 if found, -ENODEV if not 985 */ 986 int pci_find_device_id(struct pci_device_id *ids, int index, 987 struct udevice **devp); 988 989 /** 990 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices 991 * 992 * This probes the given bus which causes it to be scanned for devices. The 993 * devices will be bound but not probed. 994 * 995 * @hose specifies the PCI hose that will be used for the scan. This is 996 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is 997 * in @bdf, and is a subordinate bus reachable from @hose. 998 * 999 * @hose: PCI hose to scan 1000 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number) 1001 * @return 0 if OK, -ve on error 1002 */ 1003 int dm_pci_hose_probe_bus(struct udevice *bus); 1004 1005 /** 1006 * pci_bus_read_config() - Read a configuration value from a device 1007 * 1008 * TODO(sjg@chromium.org): We should be able to pass just a device and have 1009 * it do the right thing. It would be good to have that function also. 1010 * 1011 * @bus: Bus to read from 1012 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1013 * @offset: Register offset to read 1014 * @valuep: Place to put the returned value 1015 * @size: Access size 1016 * @return 0 if OK, -ve on error 1017 */ 1018 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset, 1019 unsigned long *valuep, enum pci_size_t size); 1020 1021 /** 1022 * pci_bus_write_config() - Write a configuration value to a device 1023 * 1024 * @bus: Bus to write from 1025 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1026 * @offset: Register offset to write 1027 * @value: Value to write 1028 * @size: Access size 1029 * @return 0 if OK, -ve on error 1030 */ 1031 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, 1032 unsigned long value, enum pci_size_t size); 1033 1034 /** 1035 * pci_bus_clrset_config32() - Update a configuration value for a device 1036 * 1037 * The register at @offset is updated to (oldvalue & ~clr) | set. 1038 * 1039 * @bus: Bus to access 1040 * @bdf: PCI device address: bus, device and function -see PCI_BDF() 1041 * @offset: Register offset to update 1042 * @clr: Bits to clear 1043 * @set: Bits to set 1044 * @return 0 if OK, -ve on error 1045 */ 1046 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset, 1047 u32 clr, u32 set); 1048 1049 /** 1050 * Driver model PCI config access functions. Use these in preference to others 1051 * when you have a valid device 1052 */ 1053 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep, 1054 enum pci_size_t size); 1055 1056 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep); 1057 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep); 1058 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep); 1059 1060 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value, 1061 enum pci_size_t size); 1062 1063 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value); 1064 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value); 1065 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value); 1066 1067 /** 1068 * These permit convenient read/modify/write on PCI configuration. The 1069 * register is updated to (oldvalue & ~clr) | set. 1070 */ 1071 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set); 1072 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set); 1073 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set); 1074 1075 /* 1076 * The following functions provide access to the above without needing the 1077 * size parameter. We are trying to encourage the use of the 8/16/32-style 1078 * functions, rather than byte/word/dword. But both are supported. 1079 */ 1080 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value); 1081 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value); 1082 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value); 1083 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep); 1084 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep); 1085 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep); 1086 1087 /** 1088 * pci_generic_mmap_write_config() - Generic helper for writing to 1089 * memory-mapped PCI configuration space. 1090 * @bus: Pointer to the PCI bus 1091 * @addr_f: Callback for calculating the config space address 1092 * @bdf: Identifies the PCI device to access 1093 * @offset: The offset into the device's configuration space 1094 * @value: The value to write 1095 * @size: Indicates the size of access to perform 1096 * 1097 * Write the value @value of size @size from offset @offset within the 1098 * configuration space of the device identified by the bus, device & function 1099 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is 1100 * responsible for calculating the CPU address of the respective configuration 1101 * space offset. 1102 * 1103 * Return: 0 on success, else -EINVAL 1104 */ 1105 int pci_generic_mmap_write_config( 1106 struct udevice *bus, 1107 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), 1108 pci_dev_t bdf, 1109 uint offset, 1110 ulong value, 1111 enum pci_size_t size); 1112 1113 /** 1114 * pci_generic_mmap_read_config() - Generic helper for reading from 1115 * memory-mapped PCI configuration space. 1116 * @bus: Pointer to the PCI bus 1117 * @addr_f: Callback for calculating the config space address 1118 * @bdf: Identifies the PCI device to access 1119 * @offset: The offset into the device's configuration space 1120 * @valuep: A pointer at which to store the read value 1121 * @size: Indicates the size of access to perform 1122 * 1123 * Read a value of size @size from offset @offset within the configuration 1124 * space of the device identified by the bus, device & function numbers in @bdf 1125 * on the PCI bus @bus. The callback function @addr_f is responsible for 1126 * calculating the CPU address of the respective configuration space offset. 1127 * 1128 * Return: 0 on success, else -EINVAL 1129 */ 1130 int pci_generic_mmap_read_config( 1131 struct udevice *bus, 1132 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp), 1133 pci_dev_t bdf, 1134 uint offset, 1135 ulong *valuep, 1136 enum pci_size_t size); 1137 1138 #ifdef CONFIG_DM_PCI_COMPAT 1139 /* Compatibility with old naming */ 1140 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, 1141 u32 value) 1142 { 1143 return pci_write_config32(pcidev, offset, value); 1144 } 1145 1146 /* Compatibility with old naming */ 1147 static inline int pci_write_config_word(pci_dev_t pcidev, int offset, 1148 u16 value) 1149 { 1150 return pci_write_config16(pcidev, offset, value); 1151 } 1152 1153 /* Compatibility with old naming */ 1154 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset, 1155 u8 value) 1156 { 1157 return pci_write_config8(pcidev, offset, value); 1158 } 1159 1160 /* Compatibility with old naming */ 1161 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset, 1162 u32 *valuep) 1163 { 1164 return pci_read_config32(pcidev, offset, valuep); 1165 } 1166 1167 /* Compatibility with old naming */ 1168 static inline int pci_read_config_word(pci_dev_t pcidev, int offset, 1169 u16 *valuep) 1170 { 1171 return pci_read_config16(pcidev, offset, valuep); 1172 } 1173 1174 /* Compatibility with old naming */ 1175 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset, 1176 u8 *valuep) 1177 { 1178 return pci_read_config8(pcidev, offset, valuep); 1179 } 1180 #endif /* CONFIG_DM_PCI_COMPAT */ 1181 1182 /** 1183 * dm_pciauto_config_device() - configure a device ready for use 1184 * 1185 * Space is allocated for each PCI base address register (BAR) so that the 1186 * devices are mapped into memory and I/O space ready for use. 1187 * 1188 * @dev: Device to configure 1189 * @return 0 if OK, -ve on error 1190 */ 1191 int dm_pciauto_config_device(struct udevice *dev); 1192 1193 /** 1194 * pci_conv_32_to_size() - convert a 32-bit read value to the given size 1195 * 1196 * Some PCI buses must always perform 32-bit reads. The data must then be 1197 * shifted and masked to reflect the required access size and offset. This 1198 * function performs this transformation. 1199 * 1200 * @value: Value to transform (32-bit value read from @offset & ~3) 1201 * @offset: Register offset that was read 1202 * @size: Required size of the result 1203 * @return the value that would have been obtained if the read had been 1204 * performed at the given offset with the correct size 1205 */ 1206 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size); 1207 1208 /** 1209 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write 1210 * 1211 * Some PCI buses must always perform 32-bit writes. To emulate a smaller 1212 * write the old 32-bit data must be read, updated with the required new data 1213 * and written back as a 32-bit value. This function performs the 1214 * transformation from the old value to the new value. 1215 * 1216 * @value: Value to transform (32-bit value read from @offset & ~3) 1217 * @offset: Register offset that should be written 1218 * @size: Required size of the write 1219 * @return the value that should be written as a 32-bit access to @offset & ~3. 1220 */ 1221 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset, 1222 enum pci_size_t size); 1223 1224 /** 1225 * pci_get_controller() - obtain the controller to use for a bus 1226 * 1227 * @dev: Device to check 1228 * @return pointer to the controller device for this bus 1229 */ 1230 struct udevice *pci_get_controller(struct udevice *dev); 1231 1232 /** 1233 * pci_get_regions() - obtain pointers to all the region types 1234 * 1235 * @dev: Device to check 1236 * @iop: Returns a pointer to the I/O region, or NULL if none 1237 * @memp: Returns a pointer to the memory region, or NULL if none 1238 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none 1239 * @return the number of non-NULL regions returned, normally 3 1240 */ 1241 int pci_get_regions(struct udevice *dev, struct pci_region **iop, 1242 struct pci_region **memp, struct pci_region **prefp); 1243 1244 /** 1245 * dm_pci_write_bar32() - Write the address of a BAR 1246 * 1247 * This writes a raw address to a bar 1248 * 1249 * @dev: PCI device to update 1250 * @barnum: BAR number (0-5) 1251 * @addr: BAR address 1252 */ 1253 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr); 1254 1255 /** 1256 * dm_pci_read_bar32() - read a base address register from a device 1257 * 1258 * @dev: Device to check 1259 * @barnum: Bar number to read (numbered from 0) 1260 * @return: value of BAR 1261 */ 1262 u32 dm_pci_read_bar32(struct udevice *dev, int barnum); 1263 1264 /** 1265 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address 1266 * 1267 * @dev: Device containing the PCI address 1268 * @addr: PCI address to convert 1269 * @flags: Flags for the region type (PCI_REGION_...) 1270 * @return physical address corresponding to that PCI bus address 1271 */ 1272 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr, 1273 unsigned long flags); 1274 1275 /** 1276 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address 1277 * 1278 * @dev: Device containing the bus address 1279 * @addr: Physical address to convert 1280 * @flags: Flags for the region type (PCI_REGION_...) 1281 * @return PCI bus address corresponding to that physical address 1282 */ 1283 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr, 1284 unsigned long flags); 1285 1286 /** 1287 * dm_pci_map_bar() - get a virtual address associated with a BAR region 1288 * 1289 * Looks up a base address register and finds the physical memory address 1290 * that corresponds to it 1291 * 1292 * @dev: Device to check 1293 * @bar: Bar number to read (numbered from 0) 1294 * @flags: Flags for the region type (PCI_REGION_...) 1295 * @return: pointer to the virtual address to use 1296 */ 1297 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags); 1298 1299 #define dm_pci_virt_to_bus(dev, addr, flags) \ 1300 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags)) 1301 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \ 1302 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \ 1303 (len), (map_flags)) 1304 1305 #define dm_pci_phys_to_mem(dev, addr) \ 1306 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) 1307 #define dm_pci_mem_to_phys(dev, addr) \ 1308 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) 1309 #define dm_pci_phys_to_io(dev, addr) \ 1310 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO) 1311 #define dm_pci_io_to_phys(dev, addr) \ 1312 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO) 1313 1314 #define dm_pci_virt_to_mem(dev, addr) \ 1315 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) 1316 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \ 1317 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) 1318 #define dm_pci_virt_to_io(dev, addr) \ 1319 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO) 1320 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \ 1321 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) 1322 1323 /** 1324 * dm_pci_find_device() - find a device by vendor/device ID 1325 * 1326 * @vendor: Vendor ID 1327 * @device: Device ID 1328 * @index: 0 to find the first match, 1 for second, etc. 1329 * @devp: Returns pointer to the device, if found 1330 * @return 0 if found, -ve on error 1331 */ 1332 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index, 1333 struct udevice **devp); 1334 1335 /** 1336 * dm_pci_find_class() - find a device by class 1337 * 1338 * @find_class: 3-byte (24-bit) class value to find 1339 * @index: 0 to find the first match, 1 for second, etc. 1340 * @devp: Returns pointer to the device, if found 1341 * @return 0 if found, -ve on error 1342 */ 1343 int dm_pci_find_class(uint find_class, int index, struct udevice **devp); 1344 1345 /** 1346 * struct dm_pci_emul_ops - PCI device emulator operations 1347 */ 1348 struct dm_pci_emul_ops { 1349 /** 1350 * get_devfn(): Check which device and function this emulators 1351 * 1352 * @dev: device to check 1353 * @return the device and function this emulates, or -ve on error 1354 */ 1355 int (*get_devfn)(struct udevice *dev); 1356 /** 1357 * read_config() - Read a PCI configuration value 1358 * 1359 * @dev: Emulated device to read from 1360 * @offset: Byte offset within the device's configuration space 1361 * @valuep: Place to put the returned value 1362 * @size: Access size 1363 * @return 0 if OK, -ve on error 1364 */ 1365 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep, 1366 enum pci_size_t size); 1367 /** 1368 * write_config() - Write a PCI configuration value 1369 * 1370 * @dev: Emulated device to write to 1371 * @offset: Byte offset within the device's configuration space 1372 * @value: Value to write 1373 * @size: Access size 1374 * @return 0 if OK, -ve on error 1375 */ 1376 int (*write_config)(struct udevice *dev, uint offset, ulong value, 1377 enum pci_size_t size); 1378 /** 1379 * read_io() - Read a PCI I/O value 1380 * 1381 * @dev: Emulated device to read from 1382 * @addr: I/O address to read 1383 * @valuep: Place to put the returned value 1384 * @size: Access size 1385 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1386 * other -ve value on error 1387 */ 1388 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep, 1389 enum pci_size_t size); 1390 /** 1391 * write_io() - Write a PCI I/O value 1392 * 1393 * @dev: Emulated device to write from 1394 * @addr: I/O address to write 1395 * @value: Value to write 1396 * @size: Access size 1397 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1398 * other -ve value on error 1399 */ 1400 int (*write_io)(struct udevice *dev, unsigned int addr, 1401 ulong value, enum pci_size_t size); 1402 /** 1403 * map_physmem() - Map a device into sandbox memory 1404 * 1405 * @dev: Emulated device to map 1406 * @addr: Memory address, normally corresponding to a PCI BAR. 1407 * The device should have been configured to have a BAR 1408 * at this address. 1409 * @lenp: On entry, the size of the area to map, On exit it is 1410 * updated to the size actually mapped, which may be less 1411 * if the device has less space 1412 * @ptrp: Returns a pointer to the mapped address. The device's 1413 * space can be accessed as @lenp bytes starting here 1414 * @return 0 if OK, -ENOENT if @addr is not mapped by this device, 1415 * other -ve value on error 1416 */ 1417 int (*map_physmem)(struct udevice *dev, phys_addr_t addr, 1418 unsigned long *lenp, void **ptrp); 1419 /** 1420 * unmap_physmem() - undo a memory mapping 1421 * 1422 * This must be called after map_physmem() to undo the mapping. 1423 * Some devices can use this to check what has been written into 1424 * their mapped memory and perform an operations they require on it. 1425 * In this way, map/unmap can be used as a sort of handshake between 1426 * the emulated device and its users. 1427 * 1428 * @dev: Emuated device to unmap 1429 * @vaddr: Mapped memory address, as passed to map_physmem() 1430 * @len: Size of area mapped, as returned by map_physmem() 1431 * @return 0 if OK, -ve on error 1432 */ 1433 int (*unmap_physmem)(struct udevice *dev, const void *vaddr, 1434 unsigned long len); 1435 }; 1436 1437 /* Get access to a PCI device emulator's operations */ 1438 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops) 1439 1440 /** 1441 * sandbox_pci_get_emul() - Get the emulation device for a PCI device 1442 * 1443 * Searches for a suitable emulator for the given PCI bus device 1444 * 1445 * @bus: PCI bus to search 1446 * @find_devfn: PCI device and function address (PCI_DEVFN()) 1447 * @emulp: Returns emulated device if found 1448 * @return 0 if found, -ENODEV if not found 1449 */ 1450 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn, 1451 struct udevice **emulp); 1452 1453 #endif /* CONFIG_DM_PCI */ 1454 1455 /** 1456 * PCI_DEVICE - macro used to describe a specific pci device 1457 * @vend: the 16 bit PCI Vendor ID 1458 * @dev: the 16 bit PCI Device ID 1459 * 1460 * This macro is used to create a struct pci_device_id that matches a 1461 * specific device. The subvendor and subdevice fields will be set to 1462 * PCI_ANY_ID. 1463 */ 1464 #define PCI_DEVICE(vend, dev) \ 1465 .vendor = (vend), .device = (dev), \ 1466 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1467 1468 /** 1469 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem 1470 * @vend: the 16 bit PCI Vendor ID 1471 * @dev: the 16 bit PCI Device ID 1472 * @subvend: the 16 bit PCI Subvendor ID 1473 * @subdev: the 16 bit PCI Subdevice ID 1474 * 1475 * This macro is used to create a struct pci_device_id that matches a 1476 * specific device with subsystem information. 1477 */ 1478 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \ 1479 .vendor = (vend), .device = (dev), \ 1480 .subvendor = (subvend), .subdevice = (subdev) 1481 1482 /** 1483 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class 1484 * @dev_class: the class, subclass, prog-if triple for this device 1485 * @dev_class_mask: the class mask for this device 1486 * 1487 * This macro is used to create a struct pci_device_id that matches a 1488 * specific PCI class. The vendor, device, subvendor, and subdevice 1489 * fields will be set to PCI_ANY_ID. 1490 */ 1491 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \ 1492 .class = (dev_class), .class_mask = (dev_class_mask), \ 1493 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \ 1494 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID 1495 1496 /** 1497 * PCI_VDEVICE - macro used to describe a specific pci device in short form 1498 * @vend: the vendor name 1499 * @dev: the 16 bit PCI Device ID 1500 * 1501 * This macro is used to create a struct pci_device_id that matches a 1502 * specific PCI device. The subvendor, and subdevice fields will be set 1503 * to PCI_ANY_ID. The macro allows the next field to follow as the device 1504 * private data. 1505 */ 1506 1507 #define PCI_VDEVICE(vend, dev) \ 1508 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \ 1509 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0 1510 1511 /** 1512 * struct pci_driver_entry - Matches a driver to its pci_device_id list 1513 * @driver: Driver to use 1514 * @match: List of match records for this driver, terminated by {} 1515 */ 1516 struct pci_driver_entry { 1517 struct driver *driver; 1518 const struct pci_device_id *match; 1519 }; 1520 1521 #define U_BOOT_PCI_DEVICE(__name, __match) \ 1522 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\ 1523 .driver = llsym(struct driver, __name, driver), \ 1524 .match = __match, \ 1525 } 1526 1527 #endif /* __ASSEMBLY__ */ 1528 #endif /* _PCI_H */ 1529