xref: /openbmc/u-boot/include/ns16550.h (revision cd71b1d5)
1 /*
2  * NS16550 Serial Port
3  * originally from linux source (arch/powerpc/boot/ns16550.h)
4  *
5  * Cleanup and unification
6  * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
7  *
8  * modified slightly to
9  * have addresses as offsets from CONFIG_SYS_ISA_BASE
10  * added a few more definitions
11  * added prototypes for ns16550.c
12  * reduced no of com ports to 2
13  * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
14  *
15  * added support for port on 64-bit bus
16  * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
17  */
18 
19 /*
20  * Note that the following macro magic uses the fact that the compiler
21  * will not allocate storage for arrays of size 0
22  */
23 
24 #include <linux/types.h>
25 
26 #ifdef CONFIG_DM_SERIAL
27 /*
28  * For driver model we always use one byte per register, and sort out the
29  * differences in the driver
30  */
31 #define CONFIG_SYS_NS16550_REG_SIZE (-1)
32 #endif
33 
34 #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
35 #error "Please define NS16550 registers size."
36 #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
37 #define UART_REG(x) u32 x
38 #elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
39 #define UART_REG(x)						   \
40 	unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
41 	unsigned char x;
42 #elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
43 #define UART_REG(x)							\
44 	unsigned char x;						\
45 	unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
46 #endif
47 
48 /**
49  * struct ns16550_platdata - information about a NS16550 port
50  *
51  * @base:		Base register address
52  * @reg_width:		IO accesses size of registers (in bytes)
53  * @reg_shift:		Shift size of registers (0=byte, 1=16bit, 2=32bit...)
54  * @clock:		UART base clock speed in Hz
55  */
56 struct ns16550_platdata {
57 	unsigned long base;
58 	int reg_width;
59 	int reg_shift;
60 	int reg_offset;
61 	int clock;
62 	u32 fcr;
63 };
64 
65 struct udevice;
66 
67 struct NS16550 {
68 	UART_REG(rbr);		/* 0 */
69 	UART_REG(ier);		/* 1 */
70 	UART_REG(fcr);		/* 2 */
71 	UART_REG(lcr);		/* 3 */
72 	UART_REG(mcr);		/* 4 */
73 	UART_REG(lsr);		/* 5 */
74 	UART_REG(msr);		/* 6 */
75 	UART_REG(spr);		/* 7 */
76 #ifdef CONFIG_SOC_DA8XX
77 	UART_REG(reg8);		/* 8 */
78 	UART_REG(reg9);		/* 9 */
79 	UART_REG(revid1);	/* A */
80 	UART_REG(revid2);	/* B */
81 	UART_REG(pwr_mgmt);	/* C */
82 	UART_REG(mdr1);		/* D */
83 #else
84 	UART_REG(mdr1);		/* 8 */
85 	UART_REG(reg9);		/* 9 */
86 	UART_REG(regA);		/* A */
87 	UART_REG(regB);		/* B */
88 	UART_REG(regC);		/* C */
89 	UART_REG(regD);		/* D */
90 	UART_REG(regE);		/* E */
91 	UART_REG(uasr);		/* F */
92 	UART_REG(scr);		/* 10*/
93 	UART_REG(ssr);		/* 11*/
94 #endif
95 #ifdef CONFIG_DM_SERIAL
96 	struct ns16550_platdata *plat;
97 #endif
98 };
99 
100 #define thr rbr
101 #define iir fcr
102 #define dll rbr
103 #define dlm ier
104 
105 typedef struct NS16550 *NS16550_t;
106 
107 /*
108  * These are the definitions for the FIFO Control Register
109  */
110 #define UART_FCR_FIFO_EN	0x01 /* Fifo enable */
111 #define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
112 #define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
113 #define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
114 #define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
115 #define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
116 #define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
117 #define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
118 #define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
119 
120 #define UART_FCR_RXSR		0x02 /* Receiver soft reset */
121 #define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
122 
123 /* Ingenic JZ47xx specific UART-enable bit. */
124 #define UART_FCR_UME		0x10
125 
126 /* Clear & enable FIFOs */
127 #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
128 			UART_FCR_RXSR |	\
129 			UART_FCR_TXSR)
130 
131 /*
132  * These are the definitions for the Modem Control Register
133  */
134 #define UART_MCR_DTR	0x01		/* DTR   */
135 #define UART_MCR_RTS	0x02		/* RTS   */
136 #define UART_MCR_OUT1	0x04		/* Out 1 */
137 #define UART_MCR_OUT2	0x08		/* Out 2 */
138 #define UART_MCR_LOOP	0x10		/* Enable loopback test mode */
139 #define UART_MCR_AFE	0x20		/* Enable auto-RTS/CTS */
140 
141 #define UART_MCR_DMA_EN	0x04
142 #define UART_MCR_TX_DFR	0x08
143 
144 /*
145  * These are the definitions for the Line Control Register
146  *
147  * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
148  * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
149  */
150 #define UART_LCR_WLS_MSK 0x03		/* character length select mask */
151 #define UART_LCR_WLS_5	0x00		/* 5 bit character length */
152 #define UART_LCR_WLS_6	0x01		/* 6 bit character length */
153 #define UART_LCR_WLS_7	0x02		/* 7 bit character length */
154 #define UART_LCR_WLS_8	0x03		/* 8 bit character length */
155 #define UART_LCR_STB	0x04		/* # stop Bits, off=1, on=1.5 or 2) */
156 #define UART_LCR_PEN	0x08		/* Parity eneble */
157 #define UART_LCR_EPS	0x10		/* Even Parity Select */
158 #define UART_LCR_STKP	0x20		/* Stick Parity */
159 #define UART_LCR_SBRK	0x40		/* Set Break */
160 #define UART_LCR_BKSE	0x80		/* Bank select enable */
161 #define UART_LCR_DLAB	0x80		/* Divisor latch access bit */
162 
163 /*
164  * These are the definitions for the Line Status Register
165  */
166 #define UART_LSR_DR	0x01		/* Data ready */
167 #define UART_LSR_OE	0x02		/* Overrun */
168 #define UART_LSR_PE	0x04		/* Parity error */
169 #define UART_LSR_FE	0x08		/* Framing error */
170 #define UART_LSR_BI	0x10		/* Break */
171 #define UART_LSR_THRE	0x20		/* Xmit holding register empty */
172 #define UART_LSR_TEMT	0x40		/* Xmitter empty */
173 #define UART_LSR_ERR	0x80		/* Error */
174 
175 #define UART_MSR_DCD	0x80		/* Data Carrier Detect */
176 #define UART_MSR_RI	0x40		/* Ring Indicator */
177 #define UART_MSR_DSR	0x20		/* Data Set Ready */
178 #define UART_MSR_CTS	0x10		/* Clear to Send */
179 #define UART_MSR_DDCD	0x08		/* Delta DCD */
180 #define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
181 #define UART_MSR_DDSR	0x02		/* Delta DSR */
182 #define UART_MSR_DCTS	0x01		/* Delta CTS */
183 
184 /*
185  * These are the definitions for the Interrupt Identification Register
186  */
187 #define UART_IIR_NO_INT	0x01	/* No interrupts pending */
188 #define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
189 
190 #define UART_IIR_MSI	0x00	/* Modem status interrupt */
191 #define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
192 #define UART_IIR_RDI	0x04	/* Receiver data interrupt */
193 #define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
194 
195 /*
196  * These are the definitions for the Interrupt Enable Register
197  */
198 #define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
199 #define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
200 #define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
201 #define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
202 
203 /* useful defaults for LCR */
204 #define UART_LCR_8N1	0x03
205 
206 void NS16550_init(NS16550_t com_port, int baud_divisor);
207 void NS16550_putc(NS16550_t com_port, char c);
208 char NS16550_getc(NS16550_t com_port);
209 int NS16550_tstc(NS16550_t com_port);
210 void NS16550_reinit(NS16550_t com_port, int baud_divisor);
211 
212 /**
213  * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
214  *
215  * Given the UART input clock and required baudrate, calculate the divisor
216  * that should be used.
217  *
218  * @port:	UART port
219  * @clock:	UART input clock speed in Hz
220  * @baudrate:	Required baud rate
221  * @return baud rate divisor that should be used
222  */
223 int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate);
224 
225 /**
226  * ns16550_serial_ofdata_to_platdata() - convert DT to platform data
227  *
228  * Decode a device tree node for an ns16550 device. This includes the
229  * register base address and register shift properties. The caller must set
230  * up the clock frequency.
231  *
232  * @dev:	dev to decode platform data for
233  * @return:	0 if OK, -EINVAL on error
234  */
235 int ns16550_serial_ofdata_to_platdata(struct udevice *dev);
236 
237 /**
238  * ns16550_serial_probe() - probe a serial port
239  *
240  * This sets up the serial port ready for use, except for the baud rate
241  * @return 0, or -ve on error
242  */
243 int ns16550_serial_probe(struct udevice *dev);
244 
245 /**
246  * struct ns16550_serial_ops - ns16550 serial operations
247  *
248  * These should be used by the client driver for the driver's 'ops' member
249  */
250 extern const struct dm_serial_ops ns16550_serial_ops;
251