xref: /openbmc/u-boot/include/ns16550.h (revision 9b643e312d528f291966c1f30b0d90bf3b1d43dc)
1  /*
2   * NS16550 Serial Port
3   * originally from linux source (arch/powerpc/boot/ns16550.h)
4   *
5   * Cleanup and unification
6   * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
7   *
8   * modified slightly to
9   * have addresses as offsets from CONFIG_SYS_ISA_BASE
10   * added a few more definitions
11   * added prototypes for ns16550.c
12   * reduced no of com ports to 2
13   * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
14   *
15   * added support for port on 64-bit bus
16   * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
17   */
18  
19  /*
20   * Note that the following macro magic uses the fact that the compiler
21   * will not allocate storage for arrays of size 0
22   */
23  
24  #include <linux/types.h>
25  
26  #ifdef CONFIG_DM_SERIAL
27  /*
28   * For driver model we always use one byte per register, and sort out the
29   * differences in the driver
30   */
31  #define CONFIG_SYS_NS16550_REG_SIZE (-1)
32  #endif
33  
34  #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
35  #error "Please define NS16550 registers size."
36  #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
37  #define UART_REG(x) u32 x
38  #elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
39  #define UART_REG(x)						   \
40  	unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
41  	unsigned char x;
42  #elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
43  #define UART_REG(x)							\
44  	unsigned char x;						\
45  	unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
46  #endif
47  
48  /**
49   * struct ns16550_platdata - information about a NS16550 port
50   *
51   * @base:		Base register address
52   * @reg_shift:		Shift size of registers (0=byte, 1=16bit, 2=32bit...)
53   * @clock:		UART base clock speed in Hz
54   */
55  struct ns16550_platdata {
56  	unsigned long base;
57  	int reg_shift;
58  	int clock;
59  	int reg_offset;
60  	u32 fcr;
61  };
62  
63  struct udevice;
64  
65  struct NS16550 {
66  	UART_REG(rbr);		/* 0 */
67  	UART_REG(ier);		/* 1 */
68  	UART_REG(fcr);		/* 2 */
69  	UART_REG(lcr);		/* 3 */
70  	UART_REG(mcr);		/* 4 */
71  	UART_REG(lsr);		/* 5 */
72  	UART_REG(msr);		/* 6 */
73  	UART_REG(spr);		/* 7 */
74  #ifdef CONFIG_SOC_DA8XX
75  	UART_REG(reg8);		/* 8 */
76  	UART_REG(reg9);		/* 9 */
77  	UART_REG(revid1);	/* A */
78  	UART_REG(revid2);	/* B */
79  	UART_REG(pwr_mgmt);	/* C */
80  	UART_REG(mdr1);		/* D */
81  #else
82  	UART_REG(mdr1);		/* 8 */
83  	UART_REG(reg9);		/* 9 */
84  	UART_REG(regA);		/* A */
85  	UART_REG(regB);		/* B */
86  	UART_REG(regC);		/* C */
87  	UART_REG(regD);		/* D */
88  	UART_REG(regE);		/* E */
89  	UART_REG(uasr);		/* F */
90  	UART_REG(scr);		/* 10*/
91  	UART_REG(ssr);		/* 11*/
92  #endif
93  #ifdef CONFIG_DM_SERIAL
94  	struct ns16550_platdata *plat;
95  #endif
96  };
97  
98  #define thr rbr
99  #define iir fcr
100  #define dll rbr
101  #define dlm ier
102  
103  typedef struct NS16550 *NS16550_t;
104  
105  /*
106   * These are the definitions for the FIFO Control Register
107   */
108  #define UART_FCR_FIFO_EN	0x01 /* Fifo enable */
109  #define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
110  #define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
111  #define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
112  #define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
113  #define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
114  #define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
115  #define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
116  #define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
117  
118  #define UART_FCR_RXSR		0x02 /* Receiver soft reset */
119  #define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
120  
121  /* Ingenic JZ47xx specific UART-enable bit. */
122  #define UART_FCR_UME		0x10
123  
124  /* Clear & enable FIFOs */
125  #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
126  			UART_FCR_RXSR |	\
127  			UART_FCR_TXSR)
128  
129  /*
130   * These are the definitions for the Modem Control Register
131   */
132  #define UART_MCR_DTR	0x01		/* DTR   */
133  #define UART_MCR_RTS	0x02		/* RTS   */
134  #define UART_MCR_OUT1	0x04		/* Out 1 */
135  #define UART_MCR_OUT2	0x08		/* Out 2 */
136  #define UART_MCR_LOOP	0x10		/* Enable loopback test mode */
137  #define UART_MCR_AFE	0x20		/* Enable auto-RTS/CTS */
138  
139  #define UART_MCR_DMA_EN	0x04
140  #define UART_MCR_TX_DFR	0x08
141  
142  /*
143   * These are the definitions for the Line Control Register
144   *
145   * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
146   * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
147   */
148  #define UART_LCR_WLS_MSK 0x03		/* character length select mask */
149  #define UART_LCR_WLS_5	0x00		/* 5 bit character length */
150  #define UART_LCR_WLS_6	0x01		/* 6 bit character length */
151  #define UART_LCR_WLS_7	0x02		/* 7 bit character length */
152  #define UART_LCR_WLS_8	0x03		/* 8 bit character length */
153  #define UART_LCR_STB	0x04		/* # stop Bits, off=1, on=1.5 or 2) */
154  #define UART_LCR_PEN	0x08		/* Parity eneble */
155  #define UART_LCR_EPS	0x10		/* Even Parity Select */
156  #define UART_LCR_STKP	0x20		/* Stick Parity */
157  #define UART_LCR_SBRK	0x40		/* Set Break */
158  #define UART_LCR_BKSE	0x80		/* Bank select enable */
159  #define UART_LCR_DLAB	0x80		/* Divisor latch access bit */
160  
161  /*
162   * These are the definitions for the Line Status Register
163   */
164  #define UART_LSR_DR	0x01		/* Data ready */
165  #define UART_LSR_OE	0x02		/* Overrun */
166  #define UART_LSR_PE	0x04		/* Parity error */
167  #define UART_LSR_FE	0x08		/* Framing error */
168  #define UART_LSR_BI	0x10		/* Break */
169  #define UART_LSR_THRE	0x20		/* Xmit holding register empty */
170  #define UART_LSR_TEMT	0x40		/* Xmitter empty */
171  #define UART_LSR_ERR	0x80		/* Error */
172  
173  #define UART_MSR_DCD	0x80		/* Data Carrier Detect */
174  #define UART_MSR_RI	0x40		/* Ring Indicator */
175  #define UART_MSR_DSR	0x20		/* Data Set Ready */
176  #define UART_MSR_CTS	0x10		/* Clear to Send */
177  #define UART_MSR_DDCD	0x08		/* Delta DCD */
178  #define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
179  #define UART_MSR_DDSR	0x02		/* Delta DSR */
180  #define UART_MSR_DCTS	0x01		/* Delta CTS */
181  
182  /*
183   * These are the definitions for the Interrupt Identification Register
184   */
185  #define UART_IIR_NO_INT	0x01	/* No interrupts pending */
186  #define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
187  
188  #define UART_IIR_MSI	0x00	/* Modem status interrupt */
189  #define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
190  #define UART_IIR_RDI	0x04	/* Receiver data interrupt */
191  #define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
192  
193  /*
194   * These are the definitions for the Interrupt Enable Register
195   */
196  #define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
197  #define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
198  #define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
199  #define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
200  
201  /* useful defaults for LCR */
202  #define UART_LCR_8N1	0x03
203  
204  void NS16550_init(NS16550_t com_port, int baud_divisor);
205  void NS16550_putc(NS16550_t com_port, char c);
206  char NS16550_getc(NS16550_t com_port);
207  int NS16550_tstc(NS16550_t com_port);
208  void NS16550_reinit(NS16550_t com_port, int baud_divisor);
209  
210  /**
211   * ns16550_calc_divisor() - calculate the divisor given clock and baud rate
212   *
213   * Given the UART input clock and required baudrate, calculate the divisor
214   * that should be used.
215   *
216   * @port:	UART port
217   * @clock:	UART input clock speed in Hz
218   * @baudrate:	Required baud rate
219   * @return baud rate divisor that should be used
220   */
221  int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate);
222  
223  /**
224   * ns16550_serial_ofdata_to_platdata() - convert DT to platform data
225   *
226   * Decode a device tree node for an ns16550 device. This includes the
227   * register base address and register shift properties. The caller must set
228   * up the clock frequency.
229   *
230   * @dev:	dev to decode platform data for
231   * @return:	0 if OK, -EINVAL on error
232   */
233  int ns16550_serial_ofdata_to_platdata(struct udevice *dev);
234  
235  /**
236   * ns16550_serial_probe() - probe a serial port
237   *
238   * This sets up the serial port ready for use, except for the baud rate
239   * @return 0, or -ve on error
240   */
241  int ns16550_serial_probe(struct udevice *dev);
242  
243  /**
244   * struct ns16550_serial_ops - ns16550 serial operations
245   *
246   * These should be used by the client driver for the driver's 'ops' member
247   */
248  extern const struct dm_serial_ops ns16550_serial_ops;
249