1 /* 2 * NS16550 Serial Port 3 * originally from linux source (arch/powerpc/boot/ns16550.h) 4 * 5 * Cleanup and unification 6 * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH 7 * 8 * modified slightly to 9 * have addresses as offsets from CONFIG_SYS_ISA_BASE 10 * added a few more definitions 11 * added prototypes for ns16550.c 12 * reduced no of com ports to 2 13 * modifications (c) Rob Taylor, Flying Pig Systems. 2000. 14 * 15 * added support for port on 64-bit bus 16 * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems 17 */ 18 19 /* 20 * Note that the following macro magic uses the fact that the compiler 21 * will not allocate storage for arrays of size 0 22 */ 23 24 #include <linux/types.h> 25 26 #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) 27 #error "Please define NS16550 registers size." 28 #elif defined(CONFIG_SYS_NS16550_MEM32) 29 #define UART_REG(x) u32 x 30 #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) 31 #define UART_REG(x) \ 32 unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ 33 unsigned char x; 34 #elif (CONFIG_SYS_NS16550_REG_SIZE < 0) 35 #define UART_REG(x) \ 36 unsigned char x; \ 37 unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; 38 #endif 39 40 struct NS16550 { 41 UART_REG(rbr); /* 0 */ 42 UART_REG(ier); /* 1 */ 43 UART_REG(fcr); /* 2 */ 44 UART_REG(lcr); /* 3 */ 45 UART_REG(mcr); /* 4 */ 46 UART_REG(lsr); /* 5 */ 47 UART_REG(msr); /* 6 */ 48 UART_REG(spr); /* 7 */ 49 #ifdef CONFIG_SOC_DA8XX 50 UART_REG(reg8); /* 8 */ 51 UART_REG(reg9); /* 9 */ 52 UART_REG(revid1); /* A */ 53 UART_REG(revid2); /* B */ 54 UART_REG(pwr_mgmt); /* C */ 55 UART_REG(mdr1); /* D */ 56 #else 57 UART_REG(mdr1); /* 8 */ 58 UART_REG(reg9); /* 9 */ 59 UART_REG(regA); /* A */ 60 UART_REG(regB); /* B */ 61 UART_REG(regC); /* C */ 62 UART_REG(regD); /* D */ 63 UART_REG(regE); /* E */ 64 UART_REG(uasr); /* F */ 65 UART_REG(scr); /* 10*/ 66 UART_REG(ssr); /* 11*/ 67 UART_REG(reg12); /* 12*/ 68 UART_REG(osc_12m_sel); /* 13*/ 69 #endif 70 }; 71 72 #define thr rbr 73 #define iir fcr 74 #define dll rbr 75 #define dlm ier 76 77 typedef struct NS16550 *NS16550_t; 78 79 /* 80 * These are the definitions for the FIFO Control Register 81 */ 82 #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ 83 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 84 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 85 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 86 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ 87 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ 88 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ 89 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ 90 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ 91 92 #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ 93 #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ 94 95 /* 96 * These are the definitions for the Modem Control Register 97 */ 98 #define UART_MCR_DTR 0x01 /* DTR */ 99 #define UART_MCR_RTS 0x02 /* RTS */ 100 #define UART_MCR_OUT1 0x04 /* Out 1 */ 101 #define UART_MCR_OUT2 0x08 /* Out 2 */ 102 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 103 104 #define UART_MCR_DMA_EN 0x04 105 #define UART_MCR_TX_DFR 0x08 106 107 /* 108 * These are the definitions for the Line Control Register 109 * 110 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 111 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 112 */ 113 #define UART_LCR_WLS_MSK 0x03 /* character length select mask */ 114 #define UART_LCR_WLS_5 0x00 /* 5 bit character length */ 115 #define UART_LCR_WLS_6 0x01 /* 6 bit character length */ 116 #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ 117 #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ 118 #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ 119 #define UART_LCR_PEN 0x08 /* Parity eneble */ 120 #define UART_LCR_EPS 0x10 /* Even Parity Select */ 121 #define UART_LCR_STKP 0x20 /* Stick Parity */ 122 #define UART_LCR_SBRK 0x40 /* Set Break */ 123 #define UART_LCR_BKSE 0x80 /* Bank select enable */ 124 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 125 126 /* 127 * These are the definitions for the Line Status Register 128 */ 129 #define UART_LSR_DR 0x01 /* Data ready */ 130 #define UART_LSR_OE 0x02 /* Overrun */ 131 #define UART_LSR_PE 0x04 /* Parity error */ 132 #define UART_LSR_FE 0x08 /* Framing error */ 133 #define UART_LSR_BI 0x10 /* Break */ 134 #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ 135 #define UART_LSR_TEMT 0x40 /* Xmitter empty */ 136 #define UART_LSR_ERR 0x80 /* Error */ 137 138 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 139 #define UART_MSR_RI 0x40 /* Ring Indicator */ 140 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 141 #define UART_MSR_CTS 0x10 /* Clear to Send */ 142 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 143 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 144 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 145 #define UART_MSR_DCTS 0x01 /* Delta CTS */ 146 147 /* 148 * These are the definitions for the Interrupt Identification Register 149 */ 150 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 151 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 152 153 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 154 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 155 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 156 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 157 158 /* 159 * These are the definitions for the Interrupt Enable Register 160 */ 161 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 162 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 163 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 164 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 165 166 167 #ifdef CONFIG_OMAP1510 168 #define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */ 169 #endif 170 171 /* useful defaults for LCR */ 172 #define UART_LCR_8N1 0x03 173 174 void NS16550_init(NS16550_t com_port, int baud_divisor); 175 void NS16550_putc(NS16550_t com_port, char c); 176 char NS16550_getc(NS16550_t com_port); 177 int NS16550_tstc(NS16550_t com_port); 178 void NS16550_reinit(NS16550_t com_port, int baud_divisor); 179