1*cf4c3448SCalvin Johnson /* 2*cf4c3448SCalvin Johnson * Copyright 2015-2016 Freescale Semiconductor, Inc. 3*cf4c3448SCalvin Johnson * Copyright 2017 NXP 4*cf4c3448SCalvin Johnson * 5*cf4c3448SCalvin Johnson * SPDX-License-Identifier: GPL-2.0+ 6*cf4c3448SCalvin Johnson */ 7*cf4c3448SCalvin Johnson 8*cf4c3448SCalvin Johnson #ifndef _UTIL_CSR_H_ 9*cf4c3448SCalvin Johnson #define _UTIL_CSR_H_ 10*cf4c3448SCalvin Johnson 11*cf4c3448SCalvin Johnson #define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000) 12*cf4c3448SCalvin Johnson #define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004) 13*cf4c3448SCalvin Johnson #define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010) 14*cf4c3448SCalvin Johnson 15*cf4c3448SCalvin Johnson #define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014) 16*cf4c3448SCalvin Johnson 17*cf4c3448SCalvin Johnson #define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020) 18*cf4c3448SCalvin Johnson #define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024) 19*cf4c3448SCalvin Johnson #define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060) 20*cf4c3448SCalvin Johnson #define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064) 21*cf4c3448SCalvin Johnson 22*cf4c3448SCalvin Johnson #define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100) 23*cf4c3448SCalvin Johnson #define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104) 24*cf4c3448SCalvin Johnson #define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108) 25*cf4c3448SCalvin Johnson 26*cf4c3448SCalvin Johnson #define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114) 27*cf4c3448SCalvin Johnson #define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118) 28*cf4c3448SCalvin Johnson 29*cf4c3448SCalvin Johnson #define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200) 30*cf4c3448SCalvin Johnson #define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204) 31*cf4c3448SCalvin Johnson #define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208) 32*cf4c3448SCalvin Johnson #define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c) 33*cf4c3448SCalvin Johnson #define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210) 34*cf4c3448SCalvin Johnson #define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214) 35*cf4c3448SCalvin Johnson #define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218) 36*cf4c3448SCalvin Johnson #define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c) 37*cf4c3448SCalvin Johnson #define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220) 38*cf4c3448SCalvin Johnson #define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224) 39*cf4c3448SCalvin Johnson 40*cf4c3448SCalvin Johnson #define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228) 41*cf4c3448SCalvin Johnson #define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c) 42*cf4c3448SCalvin Johnson #define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230) 43*cf4c3448SCalvin Johnson 44*cf4c3448SCalvin Johnson #define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234) 45*cf4c3448SCalvin Johnson #define UTIL_AXI_CTRL (UTIL_CSR_BASE_ADDR + 0x240) 46*cf4c3448SCalvin Johnson 47*cf4c3448SCalvin Johnson #endif /* _UTIL_CSR_H_ */ 48