1 /* 2 * Copyright 2015-2016 Freescale Semiconductor, Inc. 3 * Copyright 2017 NXP 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _GPI_H_ 9 #define _GPI_H_ 10 11 #define GPI_VERSION 0x00 12 #define GPI_CTRL 0x04 13 #define GPI_RX_CONFIG 0x08 14 #define GPI_HDR_SIZE 0x0c 15 #define GPI_BUF_SIZE 0x10 16 #define GPI_LMEM_ALLOC_ADDR 0x14 17 #define GPI_LMEM_FREE_ADDR 0x18 18 #define GPI_DDR_ALLOC_ADDR 0x1c 19 #define GPI_DDR_FREE_ADDR 0x20 20 #define GPI_CLASS_ADDR 0x24 21 #define GPI_DRX_FIFO 0x28 22 #define GPI_TRX_FIFO 0x2c 23 #define GPI_INQ_PKTPTR 0x30 24 #define GPI_DDR_DATA_OFFSET 0x34 25 #define GPI_LMEM_DATA_OFFSET 0x38 26 #define GPI_TMLF_TX 0x4c 27 #define GPI_DTX_ASEQ 0x50 28 #define GPI_FIFO_STATUS 0x54 29 #define GPI_FIFO_DEBUG 0x58 30 #define GPI_TX_PAUSE_TIME 0x5c 31 #define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60 32 #define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64 33 #define GPI_TOE_CHKSUM_EN 0x68 34 #define GPI_OVERRUN_DROPCNT 0x6c 35 #define GPI_AXI_CTRL 0x70 36 37 struct gpi_cfg { 38 u32 lmem_rtry_cnt; 39 u32 tmlf_txthres; 40 u32 aseq_len; 41 }; 42 43 /* GPI commons defines */ 44 #define GPI_LMEM_BUF_EN 0x1 45 #define GPI_DDR_BUF_EN 0x1 46 47 /* EGPI 1 defines */ 48 #define EGPI1_LMEM_RTRY_CNT 0x40 49 #define EGPI1_TMLF_TXTHRES 0xBC 50 #define EGPI1_ASEQ_LEN 0x50 51 52 /* EGPI 2 defines */ 53 #define EGPI2_LMEM_RTRY_CNT 0x40 54 #define EGPI2_TMLF_TXTHRES 0xBC 55 #define EGPI2_ASEQ_LEN 0x40 56 57 /* HGPI defines */ 58 #define HGPI_LMEM_RTRY_CNT 0x40 59 #define HGPI_TMLF_TXTHRES 0xBC 60 #define HGPI_ASEQ_LEN 0x40 61 62 #endif /* _GPI_H_ */ 63