1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2015-2016 Freescale Semiconductor, Inc. 4 * Copyright 2017 NXP 5 */ 6 7 #ifndef _EMAC_H_ 8 #define _EMAC_H_ 9 10 #define EMAC_IEVENT_REG 0x004 11 #define EMAC_IMASK_REG 0x008 12 #define EMAC_R_DES_ACTIVE_REG 0x010 13 #define EMAC_X_DES_ACTIVE_REG 0x014 14 #define EMAC_ECNTRL_REG 0x024 15 #define EMAC_MII_DATA_REG 0x040 16 #define EMAC_MII_CTRL_REG 0x044 17 #define EMAC_MIB_CTRL_STS_REG 0x064 18 #define EMAC_RCNTRL_REG 0x084 19 #define EMAC_TCNTRL_REG 0x0C4 20 #define EMAC_PHY_ADDR_LOW 0x0E4 21 #define EMAC_PHY_ADDR_HIGH 0x0E8 22 #define EMAC_TFWR_STR_FWD 0x144 23 #define EMAC_RX_SECTIOM_FULL 0x190 24 #define EMAC_TX_SECTION_EMPTY 0x1A0 25 #define EMAC_TRUNC_FL 0x1B0 26 27 /* GEMAC definitions and settings */ 28 #define EMAC_PORT_0 0 29 #define EMAC_PORT_1 1 30 31 /* GEMAC Bit definitions */ 32 #define EMAC_IEVENT_HBERR BIT(31) 33 #define EMAC_IEVENT_BABR BIT(30) 34 #define EMAC_IEVENT_BABT BIT(29) 35 #define EMAC_IEVENT_GRA BIT(28) 36 #define EMAC_IEVENT_TXF BIT(27) 37 #define EMAC_IEVENT_TXB BIT(26) 38 #define EMAC_IEVENT_RXF BIT(25) 39 #define EMAC_IEVENT_RXB BIT(24) 40 #define EMAC_IEVENT_MII BIT(23) 41 #define EMAC_IEVENT_EBERR BIT(22) 42 #define EMAC_IEVENT_LC BIT(21) 43 #define EMAC_IEVENT_RL BIT(20) 44 #define EMAC_IEVENT_UN BIT(19) 45 46 #define EMAC_IMASK_HBERR BIT(31) 47 #define EMAC_IMASK_BABR BIT(30) 48 #define EMAC_IMASKT_BABT BIT(29) 49 #define EMAC_IMASK_GRA BIT(28) 50 #define EMAC_IMASKT_TXF BIT(27) 51 #define EMAC_IMASK_TXB BIT(26) 52 #define EMAC_IMASKT_RXF BIT(25) 53 #define EMAC_IMASK_RXB BIT(24) 54 #define EMAC_IMASK_MII BIT(23) 55 #define EMAC_IMASK_EBERR BIT(22) 56 #define EMAC_IMASK_LC BIT(21) 57 #define EMAC_IMASKT_RL BIT(20) 58 #define EMAC_IMASK_UN BIT(19) 59 60 #define EMAC_RCNTRL_MAX_FL_SHIFT 16 61 #define EMAC_RCNTRL_LOOP BIT(0) 62 #define EMAC_RCNTRL_DRT BIT(1) 63 #define EMAC_RCNTRL_MII_MODE BIT(2) 64 #define EMAC_RCNTRL_PROM BIT(3) 65 #define EMAC_RCNTRL_BC_REJ BIT(4) 66 #define EMAC_RCNTRL_FCE BIT(5) 67 #define EMAC_RCNTRL_RGMII BIT(6) 68 #define EMAC_RCNTRL_SGMII BIT(7) 69 #define EMAC_RCNTRL_RMII BIT(8) 70 #define EMAC_RCNTRL_RMII_10T BIT(9) 71 #define EMAC_RCNTRL_CRC_FWD BIT(10) 72 73 #define EMAC_TCNTRL_GTS BIT(0) 74 #define EMAC_TCNTRL_HBC BIT(1) 75 #define EMAC_TCNTRL_FDEN BIT(2) 76 #define EMAC_TCNTRL_TFC_PAUSE BIT(3) 77 #define EMAC_TCNTRL_RFC_PAUSE BIT(4) 78 79 #define EMAC_ECNTRL_RESET BIT(0) /* reset the EMAC */ 80 #define EMAC_ECNTRL_ETHER_EN BIT(1) /* enable the EMAC */ 81 #define EMAC_ECNTRL_SPEED BIT(5) 82 #define EMAC_ECNTRL_DBSWAP BIT(8) 83 84 #define EMAC_X_WMRK_STRFWD BIT(8) 85 86 #define EMAC_X_DES_ACTIVE_TDAR BIT(24) 87 #define EMAC_R_DES_ACTIVE_RDAR BIT(24) 88 89 #define EMAC_TFWR (0x4) 90 #define EMAC_RX_SECTION_FULL_32 (0x5) 91 #define EMAC_TRUNC_FL_16K (0x3FFF) 92 #define EMAC_TX_SECTION_EMPTY_30 (0x30) 93 #define EMAC_MIBC_NO_CLR_NO_DIS (0x0) 94 95 /* 96 * The possible operating speeds of the MAC, currently supporting 10, 100 and 97 * 1000Mb modes. 98 */ 99 enum mac_speed {PFE_MAC_SPEED_10M, PFE_MAC_SPEED_100M, PFE_MAC_SPEED_1000M, 100 PFE_MAC_SPEED_1000M_PCS}; 101 102 /* MII-related definitios */ 103 #define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ 104 #define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ 105 #define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */ 106 #define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ 107 #define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */ 108 #define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ 109 #define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ 110 #define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */ 111 #define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ 112 113 #define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ 114 #define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */ 115 #define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ 116 #define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */ 117 118 #define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\ 119 EMAC_MII_DATA_RA_SHIFT) 120 #define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\ 121 EMAC_MII_DATA_PA_SHIFT) 122 #define EMAC_MII_DATA(v) (v & 0xffff) 123 124 #define EMAC_MII_SPEED_SHIFT 1 125 #define EMAC_HOLDTIME_SHIFT 8 126 #define EMAC_HOLDTIME_MASK 0x7 127 #define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT) 128 129 /* Internal PHY Registers - SGMII */ 130 #define PHY_SGMII_CR_PHY_RESET 0x8000 131 #define PHY_SGMII_CR_RESET_AN 0x0200 132 #define PHY_SGMII_CR_DEF_VAL 0x1140 133 #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 134 #define PHY_SGMII_IF_MODE_AN 0x0002 135 #define PHY_SGMII_IF_MODE_SGMII 0x0001 136 #define PHY_SGMII_IF_MODE_SGMII_GBT 0x0008 137 #define PHY_SGMII_ENABLE_AN 0x1000 138 139 #endif /* _EMAC_H_ */ 140