1*cf4c3448SCalvin Johnson /* 2*cf4c3448SCalvin Johnson * Copyright 2015-2016 Freescale Semiconductor, Inc. 3*cf4c3448SCalvin Johnson * Copyright 2017 NXP 4*cf4c3448SCalvin Johnson * 5*cf4c3448SCalvin Johnson * SPDX-License-Identifier: GPL-2.0+ 6*cf4c3448SCalvin Johnson */ 7*cf4c3448SCalvin Johnson 8*cf4c3448SCalvin Johnson #ifndef _EMAC_H_ 9*cf4c3448SCalvin Johnson #define _EMAC_H_ 10*cf4c3448SCalvin Johnson 11*cf4c3448SCalvin Johnson #define EMAC_IEVENT_REG 0x004 12*cf4c3448SCalvin Johnson #define EMAC_IMASK_REG 0x008 13*cf4c3448SCalvin Johnson #define EMAC_R_DES_ACTIVE_REG 0x010 14*cf4c3448SCalvin Johnson #define EMAC_X_DES_ACTIVE_REG 0x014 15*cf4c3448SCalvin Johnson #define EMAC_ECNTRL_REG 0x024 16*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_REG 0x040 17*cf4c3448SCalvin Johnson #define EMAC_MII_CTRL_REG 0x044 18*cf4c3448SCalvin Johnson #define EMAC_MIB_CTRL_STS_REG 0x064 19*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_REG 0x084 20*cf4c3448SCalvin Johnson #define EMAC_TCNTRL_REG 0x0C4 21*cf4c3448SCalvin Johnson #define EMAC_PHY_ADDR_LOW 0x0E4 22*cf4c3448SCalvin Johnson #define EMAC_PHY_ADDR_HIGH 0x0E8 23*cf4c3448SCalvin Johnson #define EMAC_TFWR_STR_FWD 0x144 24*cf4c3448SCalvin Johnson #define EMAC_RX_SECTIOM_FULL 0x190 25*cf4c3448SCalvin Johnson #define EMAC_TX_SECTION_EMPTY 0x1A0 26*cf4c3448SCalvin Johnson #define EMAC_TRUNC_FL 0x1B0 27*cf4c3448SCalvin Johnson 28*cf4c3448SCalvin Johnson /* GEMAC definitions and settings */ 29*cf4c3448SCalvin Johnson #define EMAC_PORT_0 0 30*cf4c3448SCalvin Johnson #define EMAC_PORT_1 1 31*cf4c3448SCalvin Johnson 32*cf4c3448SCalvin Johnson /* GEMAC Bit definitions */ 33*cf4c3448SCalvin Johnson #define EMAC_IEVENT_HBERR BIT(31) 34*cf4c3448SCalvin Johnson #define EMAC_IEVENT_BABR BIT(30) 35*cf4c3448SCalvin Johnson #define EMAC_IEVENT_BABT BIT(29) 36*cf4c3448SCalvin Johnson #define EMAC_IEVENT_GRA BIT(28) 37*cf4c3448SCalvin Johnson #define EMAC_IEVENT_TXF BIT(27) 38*cf4c3448SCalvin Johnson #define EMAC_IEVENT_TXB BIT(26) 39*cf4c3448SCalvin Johnson #define EMAC_IEVENT_RXF BIT(25) 40*cf4c3448SCalvin Johnson #define EMAC_IEVENT_RXB BIT(24) 41*cf4c3448SCalvin Johnson #define EMAC_IEVENT_MII BIT(23) 42*cf4c3448SCalvin Johnson #define EMAC_IEVENT_EBERR BIT(22) 43*cf4c3448SCalvin Johnson #define EMAC_IEVENT_LC BIT(21) 44*cf4c3448SCalvin Johnson #define EMAC_IEVENT_RL BIT(20) 45*cf4c3448SCalvin Johnson #define EMAC_IEVENT_UN BIT(19) 46*cf4c3448SCalvin Johnson 47*cf4c3448SCalvin Johnson #define EMAC_IMASK_HBERR BIT(31) 48*cf4c3448SCalvin Johnson #define EMAC_IMASK_BABR BIT(30) 49*cf4c3448SCalvin Johnson #define EMAC_IMASKT_BABT BIT(29) 50*cf4c3448SCalvin Johnson #define EMAC_IMASK_GRA BIT(28) 51*cf4c3448SCalvin Johnson #define EMAC_IMASKT_TXF BIT(27) 52*cf4c3448SCalvin Johnson #define EMAC_IMASK_TXB BIT(26) 53*cf4c3448SCalvin Johnson #define EMAC_IMASKT_RXF BIT(25) 54*cf4c3448SCalvin Johnson #define EMAC_IMASK_RXB BIT(24) 55*cf4c3448SCalvin Johnson #define EMAC_IMASK_MII BIT(23) 56*cf4c3448SCalvin Johnson #define EMAC_IMASK_EBERR BIT(22) 57*cf4c3448SCalvin Johnson #define EMAC_IMASK_LC BIT(21) 58*cf4c3448SCalvin Johnson #define EMAC_IMASKT_RL BIT(20) 59*cf4c3448SCalvin Johnson #define EMAC_IMASK_UN BIT(19) 60*cf4c3448SCalvin Johnson 61*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_MAX_FL_SHIFT 16 62*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_LOOP BIT(0) 63*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_DRT BIT(1) 64*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_MII_MODE BIT(2) 65*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_PROM BIT(3) 66*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_BC_REJ BIT(4) 67*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_FCE BIT(5) 68*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_RGMII BIT(6) 69*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_SGMII BIT(7) 70*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_RMII BIT(8) 71*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_RMII_10T BIT(9) 72*cf4c3448SCalvin Johnson #define EMAC_RCNTRL_CRC_FWD BIT(10) 73*cf4c3448SCalvin Johnson 74*cf4c3448SCalvin Johnson #define EMAC_TCNTRL_GTS BIT(0) 75*cf4c3448SCalvin Johnson #define EMAC_TCNTRL_HBC BIT(1) 76*cf4c3448SCalvin Johnson #define EMAC_TCNTRL_FDEN BIT(2) 77*cf4c3448SCalvin Johnson #define EMAC_TCNTRL_TFC_PAUSE BIT(3) 78*cf4c3448SCalvin Johnson #define EMAC_TCNTRL_RFC_PAUSE BIT(4) 79*cf4c3448SCalvin Johnson 80*cf4c3448SCalvin Johnson #define EMAC_ECNTRL_RESET BIT(0) /* reset the EMAC */ 81*cf4c3448SCalvin Johnson #define EMAC_ECNTRL_ETHER_EN BIT(1) /* enable the EMAC */ 82*cf4c3448SCalvin Johnson #define EMAC_ECNTRL_SPEED BIT(5) 83*cf4c3448SCalvin Johnson #define EMAC_ECNTRL_DBSWAP BIT(8) 84*cf4c3448SCalvin Johnson 85*cf4c3448SCalvin Johnson #define EMAC_X_WMRK_STRFWD BIT(8) 86*cf4c3448SCalvin Johnson 87*cf4c3448SCalvin Johnson #define EMAC_X_DES_ACTIVE_TDAR BIT(24) 88*cf4c3448SCalvin Johnson #define EMAC_R_DES_ACTIVE_RDAR BIT(24) 89*cf4c3448SCalvin Johnson 90*cf4c3448SCalvin Johnson #define EMAC_TFWR (0x4) 91*cf4c3448SCalvin Johnson #define EMAC_RX_SECTION_FULL_32 (0x5) 92*cf4c3448SCalvin Johnson #define EMAC_TRUNC_FL_16K (0x3FFF) 93*cf4c3448SCalvin Johnson #define EMAC_TX_SECTION_EMPTY_30 (0x30) 94*cf4c3448SCalvin Johnson #define EMAC_MIBC_NO_CLR_NO_DIS (0x0) 95*cf4c3448SCalvin Johnson 96*cf4c3448SCalvin Johnson /* 97*cf4c3448SCalvin Johnson * The possible operating speeds of the MAC, currently supporting 10, 100 and 98*cf4c3448SCalvin Johnson * 1000Mb modes. 99*cf4c3448SCalvin Johnson */ 100*cf4c3448SCalvin Johnson enum mac_speed {PFE_MAC_SPEED_10M, PFE_MAC_SPEED_100M, PFE_MAC_SPEED_1000M, 101*cf4c3448SCalvin Johnson PFE_MAC_SPEED_1000M_PCS}; 102*cf4c3448SCalvin Johnson 103*cf4c3448SCalvin Johnson /* MII-related definitios */ 104*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ 105*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ 106*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */ 107*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ 108*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */ 109*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ 110*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ 111*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */ 112*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ 113*cf4c3448SCalvin Johnson 114*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ 115*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */ 116*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ 117*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */ 118*cf4c3448SCalvin Johnson 119*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\ 120*cf4c3448SCalvin Johnson EMAC_MII_DATA_RA_SHIFT) 121*cf4c3448SCalvin Johnson #define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\ 122*cf4c3448SCalvin Johnson EMAC_MII_DATA_PA_SHIFT) 123*cf4c3448SCalvin Johnson #define EMAC_MII_DATA(v) (v & 0xffff) 124*cf4c3448SCalvin Johnson 125*cf4c3448SCalvin Johnson #define EMAC_MII_SPEED_SHIFT 1 126*cf4c3448SCalvin Johnson #define EMAC_HOLDTIME_SHIFT 8 127*cf4c3448SCalvin Johnson #define EMAC_HOLDTIME_MASK 0x7 128*cf4c3448SCalvin Johnson #define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT) 129*cf4c3448SCalvin Johnson 130*cf4c3448SCalvin Johnson /* Internal PHY Registers - SGMII */ 131*cf4c3448SCalvin Johnson #define PHY_SGMII_CR_PHY_RESET 0x8000 132*cf4c3448SCalvin Johnson #define PHY_SGMII_CR_RESET_AN 0x0200 133*cf4c3448SCalvin Johnson #define PHY_SGMII_CR_DEF_VAL 0x1140 134*cf4c3448SCalvin Johnson #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 135*cf4c3448SCalvin Johnson #define PHY_SGMII_IF_MODE_AN 0x0002 136*cf4c3448SCalvin Johnson #define PHY_SGMII_IF_MODE_SGMII 0x0001 137*cf4c3448SCalvin Johnson #define PHY_SGMII_IF_MODE_SGMII_GBT 0x0008 138*cf4c3448SCalvin Johnson #define PHY_SGMII_ENABLE_AN 0x1000 139*cf4c3448SCalvin Johnson 140*cf4c3448SCalvin Johnson #endif /* _EMAC_H_ */ 141