1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2cf4c3448SCalvin Johnson /* 3cf4c3448SCalvin Johnson * Copyright 2015-2016 Freescale Semiconductor, Inc. 4cf4c3448SCalvin Johnson * Copyright 2017 NXP 5cf4c3448SCalvin Johnson */ 6cf4c3448SCalvin Johnson 7cf4c3448SCalvin Johnson #ifndef _EMAC_H_ 8cf4c3448SCalvin Johnson #define _EMAC_H_ 9cf4c3448SCalvin Johnson 10cf4c3448SCalvin Johnson #define EMAC_IEVENT_REG 0x004 11cf4c3448SCalvin Johnson #define EMAC_IMASK_REG 0x008 12cf4c3448SCalvin Johnson #define EMAC_R_DES_ACTIVE_REG 0x010 13cf4c3448SCalvin Johnson #define EMAC_X_DES_ACTIVE_REG 0x014 14cf4c3448SCalvin Johnson #define EMAC_ECNTRL_REG 0x024 15cf4c3448SCalvin Johnson #define EMAC_MII_DATA_REG 0x040 16cf4c3448SCalvin Johnson #define EMAC_MII_CTRL_REG 0x044 17cf4c3448SCalvin Johnson #define EMAC_MIB_CTRL_STS_REG 0x064 18cf4c3448SCalvin Johnson #define EMAC_RCNTRL_REG 0x084 19cf4c3448SCalvin Johnson #define EMAC_TCNTRL_REG 0x0C4 20cf4c3448SCalvin Johnson #define EMAC_PHY_ADDR_LOW 0x0E4 21cf4c3448SCalvin Johnson #define EMAC_PHY_ADDR_HIGH 0x0E8 22cf4c3448SCalvin Johnson #define EMAC_TFWR_STR_FWD 0x144 23cf4c3448SCalvin Johnson #define EMAC_RX_SECTIOM_FULL 0x190 24cf4c3448SCalvin Johnson #define EMAC_TX_SECTION_EMPTY 0x1A0 25cf4c3448SCalvin Johnson #define EMAC_TRUNC_FL 0x1B0 26cf4c3448SCalvin Johnson 27cf4c3448SCalvin Johnson /* GEMAC definitions and settings */ 28cf4c3448SCalvin Johnson #define EMAC_PORT_0 0 29cf4c3448SCalvin Johnson #define EMAC_PORT_1 1 30cf4c3448SCalvin Johnson 31cf4c3448SCalvin Johnson /* GEMAC Bit definitions */ 32cf4c3448SCalvin Johnson #define EMAC_IEVENT_HBERR BIT(31) 33cf4c3448SCalvin Johnson #define EMAC_IEVENT_BABR BIT(30) 34cf4c3448SCalvin Johnson #define EMAC_IEVENT_BABT BIT(29) 35cf4c3448SCalvin Johnson #define EMAC_IEVENT_GRA BIT(28) 36cf4c3448SCalvin Johnson #define EMAC_IEVENT_TXF BIT(27) 37cf4c3448SCalvin Johnson #define EMAC_IEVENT_TXB BIT(26) 38cf4c3448SCalvin Johnson #define EMAC_IEVENT_RXF BIT(25) 39cf4c3448SCalvin Johnson #define EMAC_IEVENT_RXB BIT(24) 40cf4c3448SCalvin Johnson #define EMAC_IEVENT_MII BIT(23) 41cf4c3448SCalvin Johnson #define EMAC_IEVENT_EBERR BIT(22) 42cf4c3448SCalvin Johnson #define EMAC_IEVENT_LC BIT(21) 43cf4c3448SCalvin Johnson #define EMAC_IEVENT_RL BIT(20) 44cf4c3448SCalvin Johnson #define EMAC_IEVENT_UN BIT(19) 45cf4c3448SCalvin Johnson 46cf4c3448SCalvin Johnson #define EMAC_IMASK_HBERR BIT(31) 47cf4c3448SCalvin Johnson #define EMAC_IMASK_BABR BIT(30) 48cf4c3448SCalvin Johnson #define EMAC_IMASKT_BABT BIT(29) 49cf4c3448SCalvin Johnson #define EMAC_IMASK_GRA BIT(28) 50cf4c3448SCalvin Johnson #define EMAC_IMASKT_TXF BIT(27) 51cf4c3448SCalvin Johnson #define EMAC_IMASK_TXB BIT(26) 52cf4c3448SCalvin Johnson #define EMAC_IMASKT_RXF BIT(25) 53cf4c3448SCalvin Johnson #define EMAC_IMASK_RXB BIT(24) 54cf4c3448SCalvin Johnson #define EMAC_IMASK_MII BIT(23) 55cf4c3448SCalvin Johnson #define EMAC_IMASK_EBERR BIT(22) 56cf4c3448SCalvin Johnson #define EMAC_IMASK_LC BIT(21) 57cf4c3448SCalvin Johnson #define EMAC_IMASKT_RL BIT(20) 58cf4c3448SCalvin Johnson #define EMAC_IMASK_UN BIT(19) 59cf4c3448SCalvin Johnson 60cf4c3448SCalvin Johnson #define EMAC_RCNTRL_MAX_FL_SHIFT 16 61cf4c3448SCalvin Johnson #define EMAC_RCNTRL_LOOP BIT(0) 62cf4c3448SCalvin Johnson #define EMAC_RCNTRL_DRT BIT(1) 63cf4c3448SCalvin Johnson #define EMAC_RCNTRL_MII_MODE BIT(2) 64cf4c3448SCalvin Johnson #define EMAC_RCNTRL_PROM BIT(3) 65cf4c3448SCalvin Johnson #define EMAC_RCNTRL_BC_REJ BIT(4) 66cf4c3448SCalvin Johnson #define EMAC_RCNTRL_FCE BIT(5) 67cf4c3448SCalvin Johnson #define EMAC_RCNTRL_RGMII BIT(6) 68cf4c3448SCalvin Johnson #define EMAC_RCNTRL_SGMII BIT(7) 69cf4c3448SCalvin Johnson #define EMAC_RCNTRL_RMII BIT(8) 70cf4c3448SCalvin Johnson #define EMAC_RCNTRL_RMII_10T BIT(9) 71cf4c3448SCalvin Johnson #define EMAC_RCNTRL_CRC_FWD BIT(10) 72cf4c3448SCalvin Johnson 73cf4c3448SCalvin Johnson #define EMAC_TCNTRL_GTS BIT(0) 74cf4c3448SCalvin Johnson #define EMAC_TCNTRL_HBC BIT(1) 75cf4c3448SCalvin Johnson #define EMAC_TCNTRL_FDEN BIT(2) 76cf4c3448SCalvin Johnson #define EMAC_TCNTRL_TFC_PAUSE BIT(3) 77cf4c3448SCalvin Johnson #define EMAC_TCNTRL_RFC_PAUSE BIT(4) 78cf4c3448SCalvin Johnson 79cf4c3448SCalvin Johnson #define EMAC_ECNTRL_RESET BIT(0) /* reset the EMAC */ 80cf4c3448SCalvin Johnson #define EMAC_ECNTRL_ETHER_EN BIT(1) /* enable the EMAC */ 81cf4c3448SCalvin Johnson #define EMAC_ECNTRL_SPEED BIT(5) 82cf4c3448SCalvin Johnson #define EMAC_ECNTRL_DBSWAP BIT(8) 83cf4c3448SCalvin Johnson 84cf4c3448SCalvin Johnson #define EMAC_X_WMRK_STRFWD BIT(8) 85cf4c3448SCalvin Johnson 86cf4c3448SCalvin Johnson #define EMAC_X_DES_ACTIVE_TDAR BIT(24) 87cf4c3448SCalvin Johnson #define EMAC_R_DES_ACTIVE_RDAR BIT(24) 88cf4c3448SCalvin Johnson 89cf4c3448SCalvin Johnson #define EMAC_TFWR (0x4) 90cf4c3448SCalvin Johnson #define EMAC_RX_SECTION_FULL_32 (0x5) 91cf4c3448SCalvin Johnson #define EMAC_TRUNC_FL_16K (0x3FFF) 92cf4c3448SCalvin Johnson #define EMAC_TX_SECTION_EMPTY_30 (0x30) 93cf4c3448SCalvin Johnson #define EMAC_MIBC_NO_CLR_NO_DIS (0x0) 94cf4c3448SCalvin Johnson 95cf4c3448SCalvin Johnson /* 96cf4c3448SCalvin Johnson * The possible operating speeds of the MAC, currently supporting 10, 100 and 97cf4c3448SCalvin Johnson * 1000Mb modes. 98cf4c3448SCalvin Johnson */ 99cf4c3448SCalvin Johnson enum mac_speed {PFE_MAC_SPEED_10M, PFE_MAC_SPEED_100M, PFE_MAC_SPEED_1000M, 100cf4c3448SCalvin Johnson PFE_MAC_SPEED_1000M_PCS}; 101cf4c3448SCalvin Johnson 102cf4c3448SCalvin Johnson /* MII-related definitios */ 103cf4c3448SCalvin Johnson #define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ 104cf4c3448SCalvin Johnson #define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ 105cf4c3448SCalvin Johnson #define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */ 106cf4c3448SCalvin Johnson #define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ 107cf4c3448SCalvin Johnson #define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */ 108cf4c3448SCalvin Johnson #define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ 109cf4c3448SCalvin Johnson #define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ 110cf4c3448SCalvin Johnson #define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */ 111cf4c3448SCalvin Johnson #define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ 112cf4c3448SCalvin Johnson 113cf4c3448SCalvin Johnson #define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ 114cf4c3448SCalvin Johnson #define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */ 115cf4c3448SCalvin Johnson #define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ 116cf4c3448SCalvin Johnson #define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */ 117cf4c3448SCalvin Johnson 118cf4c3448SCalvin Johnson #define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\ 119cf4c3448SCalvin Johnson EMAC_MII_DATA_RA_SHIFT) 120cf4c3448SCalvin Johnson #define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) <<\ 121cf4c3448SCalvin Johnson EMAC_MII_DATA_PA_SHIFT) 122cf4c3448SCalvin Johnson #define EMAC_MII_DATA(v) (v & 0xffff) 123cf4c3448SCalvin Johnson 124cf4c3448SCalvin Johnson #define EMAC_MII_SPEED_SHIFT 1 125cf4c3448SCalvin Johnson #define EMAC_HOLDTIME_SHIFT 8 126cf4c3448SCalvin Johnson #define EMAC_HOLDTIME_MASK 0x7 127cf4c3448SCalvin Johnson #define EMAC_HOLDTIME(v) ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT) 128cf4c3448SCalvin Johnson 129cf4c3448SCalvin Johnson /* Internal PHY Registers - SGMII */ 130cf4c3448SCalvin Johnson #define PHY_SGMII_CR_PHY_RESET 0x8000 131cf4c3448SCalvin Johnson #define PHY_SGMII_CR_RESET_AN 0x0200 132cf4c3448SCalvin Johnson #define PHY_SGMII_CR_DEF_VAL 0x1140 133cf4c3448SCalvin Johnson #define PHY_SGMII_DEV_ABILITY_SGMII 0x4001 134cf4c3448SCalvin Johnson #define PHY_SGMII_IF_MODE_AN 0x0002 135cf4c3448SCalvin Johnson #define PHY_SGMII_IF_MODE_SGMII 0x0001 136cf4c3448SCalvin Johnson #define PHY_SGMII_IF_MODE_SGMII_GBT 0x0008 137cf4c3448SCalvin Johnson #define PHY_SGMII_ENABLE_AN 0x1000 138cf4c3448SCalvin Johnson 139cf4c3448SCalvin Johnson #endif /* _EMAC_H_ */ 140