1*cf4c3448SCalvin Johnson /* 2*cf4c3448SCalvin Johnson * Copyright 2015-2016 Freescale Semiconductor, Inc. 3*cf4c3448SCalvin Johnson * Copyright 2017 NXP 4*cf4c3448SCalvin Johnson * 5*cf4c3448SCalvin Johnson * SPDX-License-Identifier: GPL-2.0+ 6*cf4c3448SCalvin Johnson */ 7*cf4c3448SCalvin Johnson 8*cf4c3448SCalvin Johnson #ifndef _CBUS_H_ 9*cf4c3448SCalvin Johnson #define _CBUS_H_ 10*cf4c3448SCalvin Johnson 11*cf4c3448SCalvin Johnson #include "cbus/emac.h" 12*cf4c3448SCalvin Johnson #include "cbus/gpi.h" 13*cf4c3448SCalvin Johnson #include "cbus/bmu.h" 14*cf4c3448SCalvin Johnson #include "cbus/hif.h" 15*cf4c3448SCalvin Johnson #include "cbus/tmu_csr.h" 16*cf4c3448SCalvin Johnson #include "cbus/class_csr.h" 17*cf4c3448SCalvin Johnson #include "cbus/hif_nocpy.h" 18*cf4c3448SCalvin Johnson #include "cbus/util_csr.h" 19*cf4c3448SCalvin Johnson 20*cf4c3448SCalvin Johnson #define CBUS_BASE_ADDR ((void *)CONFIG_SYS_FSL_PFE_ADDR) 21*cf4c3448SCalvin Johnson 22*cf4c3448SCalvin Johnson /* PFE Control and Status Register Desciption */ 23*cf4c3448SCalvin Johnson #define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000) 24*cf4c3448SCalvin Johnson #define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000) 25*cf4c3448SCalvin Johnson #define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000) 26*cf4c3448SCalvin Johnson #define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000) 27*cf4c3448SCalvin Johnson #define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000) 28*cf4c3448SCalvin Johnson #define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000) 29*cf4c3448SCalvin Johnson #define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000) 30*cf4c3448SCalvin Johnson #define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000) 31*cf4c3448SCalvin Johnson #define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000) 32*cf4c3448SCalvin Johnson #define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000) 33*cf4c3448SCalvin Johnson #define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000) 34*cf4c3448SCalvin Johnson #define LMEM_SIZE 0x10000 35*cf4c3448SCalvin Johnson #define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE) 36*cf4c3448SCalvin Johnson #define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000) 37*cf4c3448SCalvin Johnson #define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) 38*cf4c3448SCalvin Johnson #define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000) 39*cf4c3448SCalvin Johnson #define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000) 40*cf4c3448SCalvin Johnson #define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000) 41*cf4c3448SCalvin Johnson 42*cf4c3448SCalvin Johnson /* 43*cf4c3448SCalvin Johnson * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR 44*cf4c3448SCalvin Johnson * XXX_MEM_ACCESS_ADDR register bit definitions. 45*cf4c3448SCalvin Johnson */ 46*cf4c3448SCalvin Johnson /* Internal Memory Write. */ 47*cf4c3448SCalvin Johnson #define PE_MEM_ACCESS_WRITE BIT(31) 48*cf4c3448SCalvin Johnson /* Internal Memory Read. */ 49*cf4c3448SCalvin Johnson #define PE_MEM_ACCESS_READ (0 << 31) 50*cf4c3448SCalvin Johnson 51*cf4c3448SCalvin Johnson #define PE_MEM_ACCESS_IMEM BIT(15) 52*cf4c3448SCalvin Johnson #define PE_MEM_ACCESS_DMEM BIT(16) 53*cf4c3448SCalvin Johnson 54*cf4c3448SCalvin Johnson /* Byte Enables of the Internal memory access. These are interpred in BE */ 55*cf4c3448SCalvin Johnson #define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) (((((1 << (size)) - 1) << (4 \ 56*cf4c3448SCalvin Johnson - (offset) - (size)))\ 57*cf4c3448SCalvin Johnson & 0xf) << 24) 58*cf4c3448SCalvin Johnson 59*cf4c3448SCalvin Johnson /* PFE cores states */ 60*cf4c3448SCalvin Johnson #define CORE_DISABLE 0x00000000 61*cf4c3448SCalvin Johnson #define CORE_ENABLE 0x00000001 62*cf4c3448SCalvin Johnson #define CORE_SW_RESET 0x00000002 63*cf4c3448SCalvin Johnson 64*cf4c3448SCalvin Johnson /* LMEM defines */ 65*cf4c3448SCalvin Johnson #define LMEM_HDR_SIZE 0x0010 66*cf4c3448SCalvin Johnson #define LMEM_BUF_SIZE_LN2 0x7 67*cf4c3448SCalvin Johnson #define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2) 68*cf4c3448SCalvin Johnson 69*cf4c3448SCalvin Johnson /* DDR defines */ 70*cf4c3448SCalvin Johnson #define DDR_HDR_SIZE 0x0100 71*cf4c3448SCalvin Johnson #define DDR_BUF_SIZE_LN2 0xb 72*cf4c3448SCalvin Johnson #define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2) 73*cf4c3448SCalvin Johnson 74*cf4c3448SCalvin Johnson /* Clock generation through PLL */ 75*cf4c3448SCalvin Johnson #define PLL_CLK_EN 1 76*cf4c3448SCalvin Johnson 77*cf4c3448SCalvin Johnson #endif /* _CBUS_H_ */ 78