1 /* 2 * (C) Copyright 2009 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25 #ifndef __CFI_FLASH_H__ 26 #define __CFI_FLASH_H__ 27 28 #define FLASH_CMD_CFI 0x98 29 #define FLASH_CMD_READ_ID 0x90 30 #define FLASH_CMD_RESET 0xff 31 #define FLASH_CMD_BLOCK_ERASE 0x20 32 #define FLASH_CMD_ERASE_CONFIRM 0xD0 33 #define FLASH_CMD_WRITE 0x40 34 #define FLASH_CMD_PROTECT 0x60 35 #define FLASH_CMD_SETUP 0x60 36 #define FLASH_CMD_SET_CR_CONFIRM 0x03 37 #define FLASH_CMD_PROTECT_SET 0x01 38 #define FLASH_CMD_PROTECT_CLEAR 0xD0 39 #define FLASH_CMD_CLEAR_STATUS 0x50 40 #define FLASH_CMD_READ_STATUS 0x70 41 #define FLASH_CMD_WRITE_TO_BUFFER 0xE8 42 #define FLASH_CMD_WRITE_BUFFER_PROG 0xE9 43 #define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0 44 45 #define FLASH_STATUS_DONE 0x80 46 #define FLASH_STATUS_ESS 0x40 47 #define FLASH_STATUS_ECLBS 0x20 48 #define FLASH_STATUS_PSLBS 0x10 49 #define FLASH_STATUS_VPENS 0x08 50 #define FLASH_STATUS_PSS 0x04 51 #define FLASH_STATUS_DPS 0x02 52 #define FLASH_STATUS_R 0x01 53 #define FLASH_STATUS_PROTECT 0x01 54 55 #define AMD_CMD_RESET 0xF0 56 #define AMD_CMD_WRITE 0xA0 57 #define AMD_CMD_ERASE_START 0x80 58 #define AMD_CMD_ERASE_SECTOR 0x30 59 #define AMD_CMD_UNLOCK_START 0xAA 60 #define AMD_CMD_UNLOCK_ACK 0x55 61 #define AMD_CMD_WRITE_TO_BUFFER 0x25 62 #define AMD_CMD_WRITE_BUFFER_CONFIRM 0x29 63 64 #define AMD_STATUS_TOGGLE 0x40 65 #define AMD_STATUS_ERROR 0x20 66 67 #define ATM_CMD_UNLOCK_SECT 0x70 68 #define ATM_CMD_SOFTLOCK_START 0x80 69 #define ATM_CMD_LOCK_SECT 0x40 70 71 #define FLASH_CONTINUATION_CODE 0x7F 72 73 #define FLASH_OFFSET_MANUFACTURER_ID 0x00 74 #define FLASH_OFFSET_DEVICE_ID 0x01 75 #define FLASH_OFFSET_DEVICE_ID2 0x0E 76 #define FLASH_OFFSET_DEVICE_ID3 0x0F 77 #define FLASH_OFFSET_CFI 0x55 78 #define FLASH_OFFSET_CFI_ALT 0x555 79 #define FLASH_OFFSET_CFI_RESP 0x10 80 #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 81 /* extended query table primary address */ 82 #define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 83 #define FLASH_OFFSET_WTOUT 0x1F 84 #define FLASH_OFFSET_WBTOUT 0x20 85 #define FLASH_OFFSET_ETOUT 0x21 86 #define FLASH_OFFSET_CETOUT 0x22 87 #define FLASH_OFFSET_WMAX_TOUT 0x23 88 #define FLASH_OFFSET_WBMAX_TOUT 0x24 89 #define FLASH_OFFSET_EMAX_TOUT 0x25 90 #define FLASH_OFFSET_CEMAX_TOUT 0x26 91 #define FLASH_OFFSET_SIZE 0x27 92 #define FLASH_OFFSET_INTERFACE 0x28 93 #define FLASH_OFFSET_BUFFER_SIZE 0x2A 94 #define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C 95 #define FLASH_OFFSET_ERASE_REGIONS 0x2D 96 #define FLASH_OFFSET_PROTECT 0x02 97 #define FLASH_OFFSET_USER_PROTECTION 0x85 98 #define FLASH_OFFSET_INTEL_PROTECTION 0x81 99 100 #define CFI_CMDSET_NONE 0 101 #define CFI_CMDSET_INTEL_EXTENDED 1 102 #define CFI_CMDSET_AMD_STANDARD 2 103 #define CFI_CMDSET_INTEL_STANDARD 3 104 #define CFI_CMDSET_AMD_EXTENDED 4 105 #define CFI_CMDSET_MITSU_STANDARD 256 106 #define CFI_CMDSET_MITSU_EXTENDED 257 107 #define CFI_CMDSET_SST 258 108 #define CFI_CMDSET_INTEL_PROG_REGIONS 512 109 110 #ifdef CONFIG_SYS_FLASH_CFI_AMD_RESET /* needed for STM_ID_29W320DB on UC100 */ 111 # undef FLASH_CMD_RESET 112 # define FLASH_CMD_RESET AMD_CMD_RESET /* use AMD-Reset instead */ 113 #endif 114 115 #define NUM_ERASE_REGIONS 4 /* max. number of erase regions */ 116 117 typedef union { 118 unsigned char c; 119 unsigned short w; 120 unsigned long l; 121 unsigned long long ll; 122 } cfiword_t; 123 124 /* CFI standard query structure */ 125 struct cfi_qry { 126 u8 qry[3]; 127 u16 p_id; 128 u16 p_adr; 129 u16 a_id; 130 u16 a_adr; 131 u8 vcc_min; 132 u8 vcc_max; 133 u8 vpp_min; 134 u8 vpp_max; 135 u8 word_write_timeout_typ; 136 u8 buf_write_timeout_typ; 137 u8 block_erase_timeout_typ; 138 u8 chip_erase_timeout_typ; 139 u8 word_write_timeout_max; 140 u8 buf_write_timeout_max; 141 u8 block_erase_timeout_max; 142 u8 chip_erase_timeout_max; 143 u8 dev_size; 144 u16 interface_desc; 145 u16 max_buf_write_size; 146 u8 num_erase_regions; 147 u32 erase_region_info[NUM_ERASE_REGIONS]; 148 } __attribute__((packed)); 149 150 struct cfi_pri_hdr { 151 u8 pri[3]; 152 u8 major_version; 153 u8 minor_version; 154 } __attribute__((packed)); 155 156 #ifndef CONFIG_SYS_FLASH_BANKS_LIST 157 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 158 #endif 159 160 /* 161 * CFI_MAX_FLASH_BANKS only used for flash_info struct declaration. 162 * 163 * Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined 164 */ 165 #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) 166 #define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks) 167 #define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT 168 /* board code can update this variable before CFI detection */ 169 extern int cfi_flash_num_flash_banks; 170 #else 171 #define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS 172 #endif 173 174 void flash_write_cmd(flash_info_t * info, flash_sect_t sect, 175 uint offset, u32 cmd); 176 177 #endif /* __CFI_FLASH_H__ */ 178