1*4a5b6a35Swdenk #ifndef _MPC8XX_IRQ_H 2*4a5b6a35Swdenk #define _MPC8XX_IRQ_H 3*4a5b6a35Swdenk 4*4a5b6a35Swdenk /* The MPC8xx cores have 16 possible interrupts. There are eight 5*4a5b6a35Swdenk * possible level sensitive interrupts assigned and generated internally 6*4a5b6a35Swdenk * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. 7*4a5b6a35Swdenk * There are eight external interrupts (IRQs) that can be configured 8*4a5b6a35Swdenk * as either level or edge sensitive. 9*4a5b6a35Swdenk * 10*4a5b6a35Swdenk * On some implementations, there is also the possibility of an 8259 11*4a5b6a35Swdenk * through the PCI and PCI-ISA bridges. 12*4a5b6a35Swdenk * 13*4a5b6a35Swdenk * We don't support the 8259 (yet). 14*4a5b6a35Swdenk */ 15*4a5b6a35Swdenk #define NR_SIU_INTS 16 16*4a5b6a35Swdenk #define NR_8259_INTS 0 17*4a5b6a35Swdenk 18*4a5b6a35Swdenk #define NR_IRQS (NR_SIU_INTS + NR_8259_INTS) 19*4a5b6a35Swdenk 20*4a5b6a35Swdenk /* These values must be zero-based and map 1:1 with the SIU configuration. 21*4a5b6a35Swdenk * They are used throughout the 8xx I/O subsystem to generate 22*4a5b6a35Swdenk * interrupt masks, flags, and other control patterns. This is why the 23*4a5b6a35Swdenk * current kernel assumption of the 8259 as the base controller is such 24*4a5b6a35Swdenk * a pain in the butt. 25*4a5b6a35Swdenk */ 26*4a5b6a35Swdenk #define SIU_IRQ0 (0) /* Highest priority */ 27*4a5b6a35Swdenk #define SIU_LEVEL0 (1) 28*4a5b6a35Swdenk #define SIU_IRQ1 (2) 29*4a5b6a35Swdenk #define SIU_LEVEL1 (3) 30*4a5b6a35Swdenk #define SIU_IRQ2 (4) 31*4a5b6a35Swdenk #define SIU_LEVEL2 (5) 32*4a5b6a35Swdenk #define SIU_IRQ3 (6) 33*4a5b6a35Swdenk #define SIU_LEVEL3 (7) 34*4a5b6a35Swdenk #define SIU_IRQ4 (8) 35*4a5b6a35Swdenk #define SIU_LEVEL4 (9) 36*4a5b6a35Swdenk #define SIU_IRQ5 (10) 37*4a5b6a35Swdenk #define SIU_LEVEL5 (11) 38*4a5b6a35Swdenk #define SIU_IRQ6 (12) 39*4a5b6a35Swdenk #define SIU_LEVEL6 (13) 40*4a5b6a35Swdenk #define SIU_IRQ7 (14) 41*4a5b6a35Swdenk #define SIU_LEVEL7 (15) 42*4a5b6a35Swdenk 43*4a5b6a35Swdenk /* The internal interrupts we can configure as we see fit. 44*4a5b6a35Swdenk * My personal preference is CPM at level 2, which puts it above the 45*4a5b6a35Swdenk * MBX PCI/ISA/IDE interrupts. 46*4a5b6a35Swdenk */ 47*4a5b6a35Swdenk 48*4a5b6a35Swdenk #ifdef CFG_CPM_INTERRUPT 49*4a5b6a35Swdenk # define CPM_INTERRUPT CFG_CPM_INTERRUPT 50*4a5b6a35Swdenk #else 51*4a5b6a35Swdenk # define CPM_INTERRUPT SIU_LEVEL2 52*4a5b6a35Swdenk #endif 53*4a5b6a35Swdenk 54*4a5b6a35Swdenk /* Some internal interrupt registers use an 8-bit mask for the interrupt 55*4a5b6a35Swdenk * level instead of a number. 56*4a5b6a35Swdenk */ 57*4a5b6a35Swdenk #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) 58*4a5b6a35Swdenk 59*4a5b6a35Swdenk #endif /* _MPC8XX_IRQ_H */ 60