xref: /openbmc/u-boot/include/mpc8xx.h (revision c916075f)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2000-2004
4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5  */
6 
7 /*
8  * mpc8xx.h
9  *
10  * MPC8xx specific definitions
11  */
12 
13 #ifndef __MPCXX_H__
14 #define __MPCXX_H__
15 
16 
17 /*-----------------------------------------------------------------------
18  * Exception offsets (PowerPC standard)
19  */
20 #define EXC_OFF_SYS_RESET	0x0100	/* System reset				*/
21 #define _START_OFFSET		EXC_OFF_SYS_RESET
22 
23 /*-----------------------------------------------------------------------
24  * SYPCR - System Protection Control Register				11-9
25  */
26 #define SYPCR_SWTC	0xFFFF0000	/* Software Watchdog Timer Count	*/
27 #define SYPCR_BMT	0x0000FF00	/* Bus Monitor Timing			*/
28 #define SYPCR_BME	0x00000080	/* Bus Monitor Enable			*/
29 #define SYPCR_SWF	0x00000008	/* Software Watchdog Freeze		*/
30 #define SYPCR_SWE	0x00000004	/* Software Watchdog Enable		*/
31 #define SYPCR_SWRI	0x00000002	/* Software Watchdog Reset/Int Select	*/
32 #define SYPCR_SWP	0x00000001	/* Software Watchdog Prescale		*/
33 
34 /*-----------------------------------------------------------------------
35  * SIUMCR - SIU Module Configuration Register				11-6
36  */
37 #define SIUMCR_EARB	0x80000000	/* External Arbitration			*/
38 #define SIUMCR_EARP0	0x00000000	/* External Arbi. Request priority 0	*/
39 #define SIUMCR_EARP1	0x10000000	/* External Arbi. Request priority 1	*/
40 #define SIUMCR_EARP2	0x20000000	/* External Arbi. Request priority 2	*/
41 #define SIUMCR_EARP3	0x30000000	/* External Arbi. Request priority 3	*/
42 #define SIUMCR_EARP4	0x40000000	/* External Arbi. Request priority 4	*/
43 #define SIUMCR_EARP5	0x50000000	/* External Arbi. Request priority 5	*/
44 #define SIUMCR_EARP6	0x60000000	/* External Arbi. Request priority 6	*/
45 #define SIUMCR_EARP7	0x70000000	/* External Arbi. Request priority 7	*/
46 #define SIUMCR_DSHW	0x00800000	/* Data Showcycles			*/
47 #define SIUMCR_DBGC00	0x00000000	/* Debug pins configuration		*/
48 #define SIUMCR_DBGC01	0x00200000	/* - " -				*/
49 #define SIUMCR_DBGC10	0x00400000	/* - " -				*/
50 #define SIUMCR_DBGC11	0x00600000	/* - " -				*/
51 #define SIUMCR_DBPC00	0x00000000	/* Debug Port pins Config.		*/
52 #define SIUMCR_DBPC01	0x00080000	/* - " -				*/
53 #define SIUMCR_DBPC10	0x00100000	/* - " -				*/
54 #define SIUMCR_DBPC11	0x00180000	/* - " -				*/
55 #define SIUMCR_FRC	0x00020000	/* FRZ pin Configuration		*/
56 #define SIUMCR_DLK	0x00010000	/* Debug Register Lock			*/
57 #define SIUMCR_PNCS	0x00008000	/* Parity Non-mem Crtl reg		*/
58 #define SIUMCR_OPAR	0x00004000	/* Odd Parity				*/
59 #define SIUMCR_DPC	0x00002000	/* Data Parity pins Config.		*/
60 #define SIUMCR_MPRE	0x00001000	/* Multi CPU Reserva. Enable		*/
61 #define SIUMCR_MLRC00	0x00000000	/* Multi Level Reserva. Ctrl		*/
62 #define SIUMCR_MLRC01	0x00000400	/* - " -				*/
63 #define SIUMCR_MLRC10	0x00000800	/* - " -				*/
64 #define SIUMCR_MLRC11	0x00000C00	/* - " -				*/
65 #define SIUMCR_AEME	0x00000200	/* Asynchro External Master		*/
66 #define SIUMCR_SEME	0x00000100	/* Synchro External Master		*/
67 #define SIUMCR_BSC	0x00000080	/* Byte Select Configuration		*/
68 #define SIUMCR_GB5E	0x00000040	/* GPL_B(5) Enable			*/
69 #define SIUMCR_B2DD	0x00000020	/* Bank 2 Double Drive			*/
70 #define SIUMCR_B3DD	0x00000010	/* Bank 3 Double Drive			*/
71 
72 /*-----------------------------------------------------------------------
73  * TBSCR - Time Base Status and Control Register			11-26
74  */
75 #define TBSCR_TBIRQ7	0x8000		/* Time Base Interrupt Request 7	*/
76 #define TBSCR_TBIRQ6	0x4000		/* Time Base Interrupt Request 6	*/
77 #define TBSCR_TBIRQ5	0x2000		/* Time Base Interrupt Request 5	*/
78 #define TBSCR_TBIRQ4	0x1000		/* Time Base Interrupt Request 4	*/
79 #define TBSCR_TBIRQ3	0x0800		/* Time Base Interrupt Request 3	*/
80 #define TBSCR_TBIRQ2	0x0400		/* Time Base Interrupt Request 2	*/
81 #define TBSCR_TBIRQ1	0x0200		/* Time Base Interrupt Request 1	*/
82 #define TBSCR_TBIRQ0	0x0100		/* Time Base Interrupt Request 0	*/
83 #if 0	/* already in asm/immap_8xx.h */
84 #define TBSCR_REFA	0x0080		/* Reference Interrupt Status A		*/
85 #define TBSCR_REFB	0x0040		/* Reference Interrupt Status B		*/
86 #define TBSCR_REFAE	0x0008		/* Second Interrupt Enable A		*/
87 #define TBSCR_REFBE	0x0004		/* Second Interrupt Enable B		*/
88 #define TBSCR_TBF	0x0002		/* Time Base Freeze			*/
89 #define TBSCR_TBE	0x0001		/* Time Base Enable			*/
90 #endif
91 
92 /*-----------------------------------------------------------------------
93  * PISCR - Periodic Interrupt Status and Control Register		11-31
94  */
95 #undef	PISCR_PIRQ			/* TBD					*/
96 #define PISCR_PITF	0x0002		/* Periodic Interrupt Timer Freeze	*/
97 #if 0	/* already in asm/immap_8xx.h */
98 #define PISCR_PS	0x0080		/* Periodic interrupt Status		*/
99 #define PISCR_PIE	0x0004		/* Periodic Interrupt Enable		*/
100 #define PISCR_PTE	0x0001		/* Periodic Timer Enable		*/
101 #endif
102 
103 /*-----------------------------------------------------------------------
104  * RSR - Reset Status Register						 5-4
105  */
106 #define RSR_JTRS	0x01000000	/* JTAG Reset Status		*/
107 #define RSR_DBSRS	0x02000000	/* Debug Port Soft Reset Status */
108 #define RSR_DBHRS	0x04000000	/* Debug Port Hard Reset Status */
109 #define RSR_CSRS	0x08000000	/* Check Stop Reset Status	*/
110 #define RSR_SWRS	0x10000000	/* Software Watchdog Reset Status*/
111 #define RSR_LLRS	0x20000000	/* Loss-of-Lock Reset Status	*/
112 #define RSR_ESRS	0x40000000	/* External Soft Reset Status	*/
113 #define RSR_EHRS	0x80000000	/* External Hard Reset Status	*/
114 
115 #define RSR_ALLBITS	(RSR_JTRS|RSR_DBSRS|RSR_DBHRS|RSR_CSRS|RSR_SWRS|RSR_LLRS|RSR_ESRS|RSR_EHRS)
116 
117 /*-----------------------------------------------------------------------
118  * Newer chips (MPC866 family and MPC87x/88x family) have different
119  * clock distribution system. Their IMMR lower half is >= 0x0800
120  */
121 #define MPC8xx_NEW_CLK 0x0800
122 
123 /*-----------------------------------------------------------------------
124  * PLPRCR - PLL, Low-Power, and Reset Control Register			15-30
125  */
126 /* Newer chips (MPC866/87x/88x et al) defines */
127 #define PLPRCR_MFN_MSK	0xF8000000	/* Multiplication factor numerator bits */
128 #define PLPRCR_MFN_SHIFT	27	/* Multiplication factor numerator shift*/
129 #define PLPRCR_MFD_MSK	0x07C00000	/* Multiplication factor denominator bits */
130 #define PLPRCR_MFD_SHIFT	22	/* Multiplication factor denominator shift*/
131 #define PLPRCR_S_MSK	0x00300000	/* Multiplication factor integer bits	*/
132 #define PLPRCR_S_SHIFT		20	/* Multiplication factor integer shift	*/
133 #define PLPRCR_MFI_MSK	0x000F0000	/* Multiplication factor integer bits	*/
134 #define PLPRCR_MFI_SHIFT	16	/* Multiplication factor integer shift	*/
135 
136 #define PLPRCR_PDF_MSK	0x0000001E	/* Predivision Factor bits		*/
137 #define PLPRCR_PDF_SHIFT	 1	/* Predivision Factor shift value	*/
138 #define PLPRCR_DBRMO	0x00000001	/* DPLL BRM Order bit			*/
139 
140 /* Multiplication factor + PDF bits */
141 #define PLPRCR_MFACT_MSK (PLPRCR_MFN_MSK | \
142 			  PLPRCR_MFD_MSK | \
143 			  PLPRCR_S_MSK	 | \
144 			  PLPRCR_MFI_MSK | \
145 			  PLPRCR_PDF_MSK)
146 
147 /* Common defines */
148 #define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
149 #define PLPRCR_CSRC	0x00000400	/* Clock Source				*/
150 
151 #define PLPRCR_CSR	0x00000080	/* CheskStop Reset value		*/
152 #define PLPRCR_LOLRE	0x00000040	/* Loss Of Lock Reset Enable		*/
153 #define PLPRCR_FIOPD	0x00000020	/* Force I/O Pull Down			*/
154 
155 /*-----------------------------------------------------------------------
156  * SCCR - System Clock and reset Control Register			15-27
157  */
158 #define SCCR_COM00	0x00000000	/* full strength CLKOUT output buffer	*/
159 #define SCCR_COM01	0x20000000	/* half strength CLKOUT output buffer	*/
160 #define SCCR_COM10	0x40000000	/* reserved				*/
161 #define SCCR_COM11	0x60000000	/* CLKOUT output buffer disabled	*/
162 #define SCCR_TBS	0x02000000	/* Time Base Source			*/
163 #define SCCR_RTDIV	0x01000000	/* RTC Clock Divide			*/
164 #define SCCR_RTSEL	0x00800000	/* RTC circuit input source select	*/
165 #define SCCR_CRQEN	0x00400000	/* CPM Request Enable			*/
166 #define SCCR_PRQEN	0x00200000	/* Power Management Request Enable	*/
167 #define SCCR_EBDF00	0x00000000	/* CLKOUT is GCLK2 / 1 (normal op.)	*/
168 #define SCCR_EBDF01	0x00020000	/* CLKOUT is GCLK2 / 2			*/
169 #define SCCR_EBDF10	0x00040000	/* reserved				*/
170 #define SCCR_EBDF11	0x00060000	/* reserved				*/
171 #define SCCR_DFSYNC00	0x00000000	/* SyncCLK division by 1 (normal op.)	*/
172 #define SCCR_DFSYNC01	0x00002000	/* SyncCLK division by 4		*/
173 #define SCCR_DFSYNC10	0x00004000	/* SyncCLK division by 16		*/
174 #define SCCR_DFSYNC11	0x00006000	/* SyncCLK division by 64		*/
175 #define SCCR_DFBRG00	0x00000000	/* BRGCLK division by 1 (normal op.)	*/
176 #define SCCR_DFBRG01	0x00000800	/* BRGCLK division by 4			*/
177 #define SCCR_DFBRG10	0x00001000	/* BRGCLK division by 16		*/
178 #define SCCR_DFBRG11	0x00001800	/* BRGCLK division by 64		*/
179 #define SCCR_DFNL000	0x00000000	/* Division by 2 (default = minimum)	*/
180 #define SCCR_DFNL001	0x00000100	/* Division by 4	                */
181 #define SCCR_DFNL010	0x00000200	/* Division by 8	                */
182 #define SCCR_DFNL011	0x00000300	/* Division by 16	                */
183 #define SCCR_DFNL100	0x00000400	/* Division by 32	                */
184 #define SCCR_DFNL101	0x00000500	/* Division by 64	                */
185 #define SCCR_DFNL110	0x00000600	/* Division by 128	                */
186 #define SCCR_DFNL111	0x00000700	/* Division by 256 (maximum)		*/
187 #define SCCR_DFNH000	0x00000000	/* Division by 1 (default = minimum)	*/
188 #define SCCR_DFNH110	0x000000D0	/* Division by 64 (maximum)		*/
189 #define SCCR_DFNH111	0x000000E0	/* reserved				*/
190 #define SCCR_DFLCD000	0x00000000	/* Division by 1 (default = minimum)	*/
191 #define SCCR_DFLCD001	0x00000004	/* Division by 2			*/
192 #define SCCR_DFLCD010	0x00000008	/* Division by 4			*/
193 #define SCCR_DFLCD011	0x0000000C	/* Division by 8			*/
194 #define SCCR_DFLCD100	0x00000010	/* Division by 16			*/
195 #define SCCR_DFLCD101	0x00000014	/* Division by 32			*/
196 #define SCCR_DFLCD110	0x00000018	/* Division by 64 (maximum)		*/
197 #define SCCR_DFLCD111	0x0000001C	/* reserved				*/
198 #define SCCR_DFALCD00	0x00000000	/* Division by 1 (default = minimum)	*/
199 #define SCCR_DFALCD01	0x00000001	/* Division by 3			*/
200 #define SCCR_DFALCD10	0x00000002	/* Division by 5			*/
201 #define SCCR_DFALCD11	0x00000003	/* Division by 7 (maximum)		*/
202 
203 
204 /*-----------------------------------------------------------------------
205  * BR - Memory Controler: Base Register					16-9
206  */
207 #define BR_BA_MSK	0xFFFF8000	/* Base Address Mask			*/
208 #define BR_AT_MSK	0x00007000	/* Address Type Mask			*/
209 #define BR_PS_MSK	0x00000C00	/* Port Size Mask			*/
210 #define BR_PS_32	0x00000000	/* 32 bit port size			*/
211 #define BR_PS_16	0x00000800	/* 16 bit port size			*/
212 #define BR_PS_8		0x00000400	/*  8 bit port size			*/
213 #define BR_PARE		0x00000200	/* Parity Enable			*/
214 #define BR_WP		0x00000100	/* Write Protect			*/
215 #define BR_MS_MSK	0x000000C0	/* Machine Select Mask			*/
216 #define BR_MS_GPCM	0x00000000	/* G.P.C.M. Machine Select		*/
217 #define BR_MS_UPMA	0x00000080	/* U.P.M.A Machine Select		*/
218 #define BR_MS_UPMB	0x000000C0	/* U.P.M.B Machine Select		*/
219 #define BR_V		0x00000001	/* Bank Valid				*/
220 
221 /*-----------------------------------------------------------------------
222  * OR - Memory Controler: Option Register				16-11
223  */
224 #define OR_AM_MSK	0xFFFF8000	/* Address Mask Mask			*/
225 #define OR_ATM_MSK	0x00007000	/* Address Type Mask Mask		*/
226 #define OR_CSNT_SAM	0x00000800	/* Chip Select Negation Time/ Start	*/
227 					/* Address Multiplex			*/
228 #define OR_ACS_MSK	0x00000600	/* Address to Chip Select Setup mask	*/
229 #define OR_ACS_DIV1	0x00000000	/* CS is output at the same time	*/
230 #define OR_ACS_DIV4	0x00000400	/* CS is output 1/4 a clock later	*/
231 #define OR_ACS_DIV2	0x00000600	/* CS is output 1/2 a clock later	*/
232 #define OR_G5LA		0x00000400	/* Output #GPL5 on #GPL_A5		*/
233 #define OR_G5LS		0x00000200	/* Drive #GPL high on falling edge of...*/
234 #define OR_BI		0x00000100	/* Burst inhibit			*/
235 #define OR_SCY_MSK	0x000000F0	/* Cycle Lenght in Clocks		*/
236 #define OR_SCY_0_CLK	0x00000000	/* 0 clock cycles wait states		*/
237 #define OR_SCY_1_CLK	0x00000010	/* 1 clock cycles wait states		*/
238 #define OR_SCY_2_CLK	0x00000020	/* 2 clock cycles wait states		*/
239 #define OR_SCY_3_CLK	0x00000030	/* 3 clock cycles wait states		*/
240 #define OR_SCY_4_CLK	0x00000040	/* 4 clock cycles wait states		*/
241 #define OR_SCY_5_CLK	0x00000050	/* 5 clock cycles wait states		*/
242 #define OR_SCY_6_CLK	0x00000060	/* 6 clock cycles wait states		*/
243 #define OR_SCY_7_CLK	0x00000070	/* 7 clock cycles wait states		*/
244 #define OR_SCY_8_CLK	0x00000080	/* 8 clock cycles wait states		*/
245 #define OR_SCY_9_CLK	0x00000090	/* 9 clock cycles wait states		*/
246 #define OR_SCY_10_CLK	0x000000A0	/* 10 clock cycles wait states		*/
247 #define OR_SCY_11_CLK	0x000000B0	/* 11 clock cycles wait states		*/
248 #define OR_SCY_12_CLK	0x000000C0	/* 12 clock cycles wait states		*/
249 #define OR_SCY_13_CLK	0x000000D0	/* 13 clock cycles wait states		*/
250 #define OR_SCY_14_CLK	0x000000E0	/* 14 clock cycles wait states		*/
251 #define OR_SCY_15_CLK	0x000000F0	/* 15 clock cycles wait states		*/
252 #define OR_SETA		0x00000008	/* External Transfer Acknowledge	*/
253 #define OR_TRLX		0x00000004	/* Timing Relaxed			*/
254 #define OR_EHTR		0x00000002	/* Extended Hold Time on Read		*/
255 
256 
257 /*-----------------------------------------------------------------------
258  * MPTPR - Memory Periodic Timer Prescaler Register			16-17
259  */
260 #define MPTPR_PTP_MSK	0xFF00		/* Periodic Timers Prescaler Mask	*/
261 #define MPTPR_PTP_DIV2	0x2000		/* BRGCLK divided by 2			*/
262 #define MPTPR_PTP_DIV4	0x1000		/* BRGCLK divided by 4			*/
263 #define MPTPR_PTP_DIV8	0x0800		/* BRGCLK divided by 8			*/
264 #define MPTPR_PTP_DIV16 0x0400		/* BRGCLK divided by 16			*/
265 #define MPTPR_PTP_DIV32 0x0200		/* BRGCLK divided by 32			*/
266 #define MPTPR_PTP_DIV64 0x0100		/* BRGCLK divided by 64			*/
267 
268 /*-----------------------------------------------------------------------
269  * MCR - Memory Command Register
270  */
271 #define MCR_OP_WRITE	0x00000000	/* WRITE command			*/
272 #define MCR_OP_READ	0x40000000	/* READ	 command			*/
273 #define MCR_OP_RUN	0x80000000	/* RUN	 command			*/
274 #define MCR_UPM_A	0x00000000	/* Select UPM A				*/
275 #define MCR_UPM_B	0x00800000	/* Select UPM B				*/
276 #define MCR_MB_CS0	0x00000000	/* Use Chip Select /CS0			*/
277 #define MCR_MB_CS1	0x00002000	/* Use Chip Select /CS1			*/
278 #define MCR_MB_CS2	0x00004000	/* Use Chip Select /CS2			*/
279 #define MCR_MB_CS3	0x00006000	/* Use Chip Select /CS3			*/
280 #define MCR_MB_CS4	0x00008000	/* Use Chip Select /CS4			*/
281 #define MCR_MB_CS5	0x0000A000	/* Use Chip Select /CS5			*/
282 #define MCR_MB_CS6	0x0000C000	/* Use Chip Select /CS6			*/
283 #define MCR_MB_CS7	0x0000E000	/* Use Chip Select /CS7			*/
284 #define MCR_MLCF(n)	(((n)&0xF)<<8)	/* Memory Command Loop Count Field	*/
285 #define MCR_MAD(addr)	((addr)&0x3F)	/* Memory Array Index			*/
286 
287 /*-----------------------------------------------------------------------
288  * Machine A Mode Register						16-13
289  */
290 #define MAMR_PTA_MSK	0xFF000000	/* Periodic Timer A period mask		*/
291 #define MAMR_PTA_SHIFT	0x00000018	/* Periodic Timer A period shift	*/
292 #define MAMR_PTAE	0x00800000	/* Periodic Timer A Enable		*/
293 #define MAMR_AMA_MSK	0x00700000	/* Addess Multiplexing size A		*/
294 #define MAMR_AMA_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
295 #define MAMR_AMA_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
296 #define MAMR_AMA_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
297 #define MAMR_AMA_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
298 #define MAMR_AMA_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
299 #define MAMR_AMA_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
300 #define MAMR_DSA_MSK	0x00060000	/* Disable Timer period mask		*/
301 #define MAMR_DSA_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
302 #define MAMR_DSA_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
303 #define MAMR_DSA_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
304 #define MAMR_DSA_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
305 #define MAMR_G0CLA_MSK	0x0000E000	/* General Line 0 Control A		*/
306 #define MAMR_G0CLA_A12	0x00000000	/* General Line 0 : A12			*/
307 #define MAMR_G0CLA_A11	0x00002000	/* General Line 0 : A11			*/
308 #define MAMR_G0CLA_A10	0x00004000	/* General Line 0 : A10			*/
309 #define MAMR_G0CLA_A9	0x00006000	/* General Line 0 : A9			*/
310 #define MAMR_G0CLA_A8	0x00008000	/* General Line 0 : A8			*/
311 #define MAMR_G0CLA_A7	0x0000A000	/* General Line 0 : A7			*/
312 #define MAMR_G0CLA_A6	0x0000C000	/* General Line 0 : A6			*/
313 #define MAMR_G0CLA_A5	0x0000E000	/* General Line 0 : A5			*/
314 #define MAMR_GPL_A4DIS	0x00001000	/* GPL_A4 ouput line Disable		*/
315 #define MAMR_RLFA_MSK	0x00000F00	/* Read Loop Field A mask		*/
316 #define MAMR_RLFA_1X	0x00000100	/* The Read Loop is executed 1 time	*/
317 #define MAMR_RLFA_2X	0x00000200	/* The Read Loop is executed 2 times	*/
318 #define MAMR_RLFA_3X	0x00000300	/* The Read Loop is executed 3 times	*/
319 #define MAMR_RLFA_4X	0x00000400	/* The Read Loop is executed 4 times	*/
320 #define MAMR_RLFA_5X	0x00000500	/* The Read Loop is executed 5 times	*/
321 #define MAMR_RLFA_6X	0x00000600	/* The Read Loop is executed 6 times	*/
322 #define MAMR_RLFA_7X	0x00000700	/* The Read Loop is executed 7 times	*/
323 #define MAMR_RLFA_8X	0x00000800	/* The Read Loop is executed 8 times	*/
324 #define MAMR_RLFA_9X	0x00000900	/* The Read Loop is executed 9 times	*/
325 #define MAMR_RLFA_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
326 #define MAMR_RLFA_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
327 #define MAMR_RLFA_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
328 #define MAMR_RLFA_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
329 #define MAMR_RLFA_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
330 #define MAMR_RLFA_15X	0x00000F00	/* The Read Loop is executed 15 times	*/
331 #define MAMR_RLFA_16X	0x00000000	/* The Read Loop is executed 16 times	*/
332 #define MAMR_WLFA_MSK	0x000000F0	/* Write Loop Field A mask		*/
333 #define MAMR_WLFA_1X	0x00000010	/* The Write Loop is executed 1 time	*/
334 #define MAMR_WLFA_2X	0x00000020	/* The Write Loop is executed 2 times	*/
335 #define MAMR_WLFA_3X	0x00000030	/* The Write Loop is executed 3 times	*/
336 #define MAMR_WLFA_4X	0x00000040	/* The Write Loop is executed 4 times	*/
337 #define MAMR_WLFA_5X	0x00000050	/* The Write Loop is executed 5 times	*/
338 #define MAMR_WLFA_6X	0x00000060	/* The Write Loop is executed 6 times	*/
339 #define MAMR_WLFA_7X	0x00000070	/* The Write Loop is executed 7 times	*/
340 #define MAMR_WLFA_8X	0x00000080	/* The Write Loop is executed 8 times	*/
341 #define MAMR_WLFA_9X	0x00000090	/* The Write Loop is executed 9 times	*/
342 #define MAMR_WLFA_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
343 #define MAMR_WLFA_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
344 #define MAMR_WLFA_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
345 #define MAMR_WLFA_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
346 #define MAMR_WLFA_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
347 #define MAMR_WLFA_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
348 #define MAMR_WLFA_16X	0x00000000	/* The Write Loop is executed 16 times	*/
349 #define MAMR_TLFA_MSK	0x0000000F	/* Timer Loop Field A mask		*/
350 #define MAMR_TLFA_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
351 #define MAMR_TLFA_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
352 #define MAMR_TLFA_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
353 #define MAMR_TLFA_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
354 #define MAMR_TLFA_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
355 #define MAMR_TLFA_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
356 #define MAMR_TLFA_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
357 #define MAMR_TLFA_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
358 #define MAMR_TLFA_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
359 #define MAMR_TLFA_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
360 #define MAMR_TLFA_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
361 #define MAMR_TLFA_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
362 #define MAMR_TLFA_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
363 #define MAMR_TLFA_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
364 #define MAMR_TLFA_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
365 #define MAMR_TLFA_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
366 
367 /*-----------------------------------------------------------------------
368  * Machine B Mode Register						16-13
369  */
370 #define MBMR_PTB_MSK	0xFF000000	/* Periodic Timer B period mask		*/
371 #define MBMR_PTB_SHIFT	0x00000018	/* Periodic Timer B period shift	*/
372 #define MBMR_PTBE	0x00800000	/* Periodic Timer B Enable		*/
373 #define MBMR_AMB_MSK	0x00700000	/* Addess Multiplex size B		*/
374 #define MBMR_AMB_TYPE_0 0x00000000	/* Addess Multiplexing Type 0		*/
375 #define MBMR_AMB_TYPE_1 0x00100000	/* Addess Multiplexing Type 1		*/
376 #define MBMR_AMB_TYPE_2 0x00200000	/* Addess Multiplexing Type 2		*/
377 #define MBMR_AMB_TYPE_3 0x00300000	/* Addess Multiplexing Type 3		*/
378 #define MBMR_AMB_TYPE_4 0x00400000	/* Addess Multiplexing Type 4		*/
379 #define MBMR_AMB_TYPE_5 0x00500000	/* Addess Multiplexing Type 5		*/
380 #define MBMR_DSB_MSK	0x00060000	/* Disable Timer period mask		*/
381 #define MBMR_DSB_1_CYCL 0x00000000	/* 1 cycle Disable Period		*/
382 #define MBMR_DSB_2_CYCL 0x00020000	/* 2 cycle Disable Period		*/
383 #define MBMR_DSB_3_CYCL 0x00040000	/* 3 cycle Disable Period		*/
384 #define MBMR_DSB_4_CYCL 0x00060000	/* 4 cycle Disable Period		*/
385 #define MBMR_G0CLB_MSK	0x0000E000	/* General Line 0 Control B		*/
386 #define MBMR_G0CLB_A12	0x00000000	/* General Line 0 : A12			*/
387 #define MBMR_G0CLB_A11	0x00002000	/* General Line 0 : A11			*/
388 #define MBMR_G0CLB_A10	0x00004000	/* General Line 0 : A10			*/
389 #define MBMR_G0CLB_A9	0x00006000	/* General Line 0 : A9			*/
390 #define MBMR_G0CLB_A8	0x00008000	/* General Line 0 : A8			*/
391 #define MBMR_G0CLB_A7	0x0000A000	/* General Line 0 : A7			*/
392 #define MBMR_G0CLB_A6	0x0000C000	/* General Line 0 : A6			*/
393 #define MBMR_G0CLB_A5	0x0000E000	/* General Line 0 : A5			*/
394 #define MBMR_GPL_B4DIS	0x00001000	/* GPL_B4 ouput line Disable		*/
395 #define MBMR_RLFB_MSK	0x00000F00	/* Read Loop Field B mask		*/
396 #define MBMR_RLFB_1X	0x00000100	/* The Read Loop is executed 1 time	*/
397 #define MBMR_RLFB_2X	0x00000200	/* The Read Loop is executed 2 times	*/
398 #define MBMR_RLFB_3X	0x00000300	/* The Read Loop is executed 3 times	*/
399 #define MBMR_RLFB_4X	0x00000400	/* The Read Loop is executed 4 times	*/
400 #define MBMR_RLFB_5X	0x00000500	/* The Read Loop is executed 5 times	*/
401 #define MBMR_RLFB_6X	0x00000600	/* The Read Loop is executed 6 times	*/
402 #define MBMR_RLFB_7X	0x00000700	/* The Read Loop is executed 7 times	*/
403 #define MBMR_RLFB_8X	0x00000800	/* The Read Loop is executed 8 times	*/
404 #define MBMR_RLFB_9X	0x00000900	/* The Read Loop is executed 9 times	*/
405 #define MBMR_RLFB_10X	0x00000A00	/* The Read Loop is executed 10 times	*/
406 #define MBMR_RLFB_11X	0x00000B00	/* The Read Loop is executed 11 times	*/
407 #define MBMR_RLFB_12X	0x00000C00	/* The Read Loop is executed 12 times	*/
408 #define MBMR_RLFB_13X	0x00000D00	/* The Read Loop is executed 13 times	*/
409 #define MBMR_RLFB_14X	0x00000E00	/* The Read Loop is executed 14 times	*/
410 #define MBMR_RLFB_15X	0x00000f00	/* The Read Loop is executed 15 times	*/
411 #define MBMR_RLFB_16X	0x00000000	/* The Read Loop is executed 16 times	*/
412 #define MBMR_WLFB_MSK	0x000000F0	/* Write Loop Field B mask		*/
413 #define MBMR_WLFB_1X	0x00000010	/* The Write Loop is executed 1 time	*/
414 #define MBMR_WLFB_2X	0x00000020	/* The Write Loop is executed 2 times	*/
415 #define MBMR_WLFB_3X	0x00000030	/* The Write Loop is executed 3 times	*/
416 #define MBMR_WLFB_4X	0x00000040	/* The Write Loop is executed 4 times	*/
417 #define MBMR_WLFB_5X	0x00000050	/* The Write Loop is executed 5 times	*/
418 #define MBMR_WLFB_6X	0x00000060	/* The Write Loop is executed 6 times	*/
419 #define MBMR_WLFB_7X	0x00000070	/* The Write Loop is executed 7 times	*/
420 #define MBMR_WLFB_8X	0x00000080	/* The Write Loop is executed 8 times	*/
421 #define MBMR_WLFB_9X	0x00000090	/* The Write Loop is executed 9 times	*/
422 #define MBMR_WLFB_10X	0x000000A0	/* The Write Loop is executed 10 times	*/
423 #define MBMR_WLFB_11X	0x000000B0	/* The Write Loop is executed 11 times	*/
424 #define MBMR_WLFB_12X	0x000000C0	/* The Write Loop is executed 12 times	*/
425 #define MBMR_WLFB_13X	0x000000D0	/* The Write Loop is executed 13 times	*/
426 #define MBMR_WLFB_14X	0x000000E0	/* The Write Loop is executed 14 times	*/
427 #define MBMR_WLFB_15X	0x000000F0	/* The Write Loop is executed 15 times	*/
428 #define MBMR_WLFB_16X	0x00000000	/* The Write Loop is executed 16 times	*/
429 #define MBMR_TLFB_MSK	0x0000000F	/* Timer Loop Field B mask		*/
430 #define MBMR_TLFB_1X	0x00000001	/* The Timer Loop is executed 1 time	*/
431 #define MBMR_TLFB_2X	0x00000002	/* The Timer Loop is executed 2 times	*/
432 #define MBMR_TLFB_3X	0x00000003	/* The Timer Loop is executed 3 times	*/
433 #define MBMR_TLFB_4X	0x00000004	/* The Timer Loop is executed 4 times	*/
434 #define MBMR_TLFB_5X	0x00000005	/* The Timer Loop is executed 5 times	*/
435 #define MBMR_TLFB_6X	0x00000006	/* The Timer Loop is executed 6 times	*/
436 #define MBMR_TLFB_7X	0x00000007	/* The Timer Loop is executed 7 times	*/
437 #define MBMR_TLFB_8X	0x00000008	/* The Timer Loop is executed 8 times	*/
438 #define MBMR_TLFB_9X	0x00000009	/* The Timer Loop is executed 9 times	*/
439 #define MBMR_TLFB_10X	0x0000000A	/* The Timer Loop is executed 10 times	*/
440 #define MBMR_TLFB_11X	0x0000000B	/* The Timer Loop is executed 11 times	*/
441 #define MBMR_TLFB_12X	0x0000000C	/* The Timer Loop is executed 12 times	*/
442 #define MBMR_TLFB_13X	0x0000000D	/* The Timer Loop is executed 13 times	*/
443 #define MBMR_TLFB_14X	0x0000000E	/* The Timer Loop is executed 14 times	*/
444 #define MBMR_TLFB_15X	0x0000000F	/* The Timer Loop is executed 15 times	*/
445 #define MBMR_TLFB_16X	0x00000000	/* The Timer Loop is executed 16 times	*/
446 
447 /*-----------------------------------------------------------------------
448  * Timer Global Configuration Register					18-8
449  */
450 #define TGCR_CAS4	0x8000		/* Cascade Timer 3 and 4	*/
451 #define TGCR_FRZ4	0x4000		/* Freeze timer 4		*/
452 #define TGCR_STP4	0x2000		/* Stop timer	4		*/
453 #define TGCR_RST4	0x1000		/* Reset timer	4		*/
454 #define TGCR_GM2	0x0800		/* Gate Mode for Pin 2		*/
455 #define TGCR_FRZ3	0x0400		/* Freeze timer 3		*/
456 #define TGCR_STP3	0x0200		/* Stop timer	3		*/
457 #define TGCR_RST3	0x0100		/* Reset timer	3		*/
458 #define TGCR_CAS2	0x0080		/* Cascade Timer 1 and 2	*/
459 #define TGCR_FRZ2	0x0040		/* Freeze timer 2		*/
460 #define TGCR_STP2	0x0020		/* Stop timer	2		*/
461 #define TGCR_RST2	0x0010		/* Reset timer	2		*/
462 #define TGCR_GM1	0x0008		/* Gate Mode for Pin 1		*/
463 #define TGCR_FRZ1	0x0004		/* Freeze timer 1		*/
464 #define TGCR_STP1	0x0002		/* Stop timer	1		*/
465 #define TGCR_RST1	0x0001		/* Reset timer	1		*/
466 
467 
468 /*-----------------------------------------------------------------------
469  * Timer Mode Register							18-9
470  */
471 #define TMR_PS_MSK		0xFF00	/* Prescaler Value			*/
472 #define TMR_PS_SHIFT		     8	/* Prescaler position			*/
473 #define TMR_CE_MSK		0x00C0	/* Capture Edge and Enable Interrupt	*/
474 #define TMR_CE_INTR_DIS		0x0000	/* Disable Interrupt on capture event	*/
475 #define TMR_CE_RISING		0x0040	/* Capture on Rising TINx edge only	*/
476 #define TMR_CE_FALLING		0x0080	/* Capture on Falling TINx edge only	*/
477 #define TMR_CE_ANY		0x00C0	/* Capture on any TINx edge		*/
478 #define TMR_OM			0x0020	/* Output Mode				*/
479 #define TMR_ORI			0x0010	/* Output Reference Interrupt Enable	*/
480 #define TMR_FRR			0x0008	/* Free Run/Restart			*/
481 #define TMR_ICLK_MSK		0x0006	/* Timer Input Clock Source mask	*/
482 #define TMR_ICLK_IN_CAS		0x0000	/* Internally cascaded input		*/
483 #define TMR_ICLK_IN_GEN		0x0002	/* Internal General system clock	*/
484 #define TMR_ICLK_IN_GEN_DIV16	0x0004	/* Internal General system clk div 16	*/
485 #define TMR_ICLK_TIN_PIN	0x0006	/* TINx pin				*/
486 #define TMR_GE			0x0001	/* Gate Enable				*/
487 
488 
489 /*-----------------------------------------------------------------------
490  * I2C Controller Registers
491  */
492 #define I2MOD_REVD		0x20	/* Reverese Data			*/
493 #define I2MOD_GCD		0x10	/* General Call Disable			*/
494 #define I2MOD_FLT		0x08	/* Clock Filter				*/
495 #define I2MOD_PDIV32		0x00	/* Pre-Divider 32			*/
496 #define I2MOD_PDIV16		0x02	/* Pre-Divider 16			*/
497 #define I2MOD_PDIV8		0x04	/* Pre-Divider	8			*/
498 #define I2MOD_PDIV4		0x06	/* Pre-Divider	4			*/
499 #define I2MOD_EN		0x01	/* Enable				*/
500 
501 #define I2CER_TXE		0x10	/* Tx Error				*/
502 #define I2CER_BSY		0x04	/* Busy Condition			*/
503 #define I2CER_TXB		0x02	/* Tx Buffer Transmitted		*/
504 #define I2CER_RXB		0x01	/* Rx Buffer Received			*/
505 #define I2CER_ALL		(I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB)
506 
507 #define I2COM_STR		0x80	/* Start Transmit			*/
508 #define I2COM_MASTER		0x01	/* Master mode				*/
509 
510 /*-----------------------------------------------------------------------
511  * SPI Controller Registers						31-10
512  */
513 #define SPI_EMASK		0x37	/* Event Mask				*/
514 #define SPI_MME			0x20	/* Multi-Master Error			*/
515 #define SPI_TXE			0x10	/* Transmit Error			*/
516 #define SPI_BSY			0x04	/* Busy					*/
517 #define SPI_TXB			0x02	/* Tx Buffer Empty			*/
518 #define SPI_RXB			0x01	/* RX Buffer full/closed		*/
519 
520 #define SPI_STR			0x80	/* SPCOM: Start transmit		*/
521 
522 /*-----------------------------------------------------------------------
523  * PCMCIA Interface General Control Register				17-12
524  */
525 #define PCMCIA_GCRX_CXRESET	0x00000040
526 #define PCMCIA_GCRX_CXOE	0x00000080
527 
528 #define PCMCIA_VS1(slot)	(0x80000000 >> (slot << 4))
529 #define PCMCIA_VS2(slot)	(0x40000000 >> (slot << 4))
530 #define PCMCIA_VS_MASK(slot)	(0xC0000000 >> (slot << 4))
531 #define PCMCIA_VS_SHIFT(slot)	(30 - (slot << 4))
532 
533 #define PCMCIA_WP(slot)		(0x20000000 >> (slot << 4))
534 #define PCMCIA_CD2(slot)	(0x10000000 >> (slot << 4))
535 #define PCMCIA_CD1(slot)	(0x08000000 >> (slot << 4))
536 #define PCMCIA_BVD2(slot)	(0x04000000 >> (slot << 4))
537 #define PCMCIA_BVD1(slot)	(0x02000000 >> (slot << 4))
538 #define PCMCIA_RDY(slot)	(0x01000000 >> (slot << 4))
539 #define PCMCIA_RDY_L(slot)	(0x00800000 >> (slot << 4))
540 #define PCMCIA_RDY_H(slot)	(0x00400000 >> (slot << 4))
541 #define PCMCIA_RDY_R(slot)	(0x00200000 >> (slot << 4))
542 #define PCMCIA_RDY_F(slot)	(0x00100000 >> (slot << 4))
543 #define PCMCIA_MASK(slot)	(0xFFFF0000 >> (slot << 4))
544 
545 /*-----------------------------------------------------------------------
546  * PCMCIA Option Register Definitions
547  *
548  * Bank Sizes:
549  */
550 #define PCMCIA_BSIZE_1		0x00000000	/* Bank size:	1 Bytes */
551 #define PCMCIA_BSIZE_2		0x08000000	/* Bank size:	2 Bytes */
552 #define PCMCIA_BSIZE_4		0x18000000	/* Bank size:	4 Bytes */
553 #define PCMCIA_BSIZE_8		0x10000000	/* Bank size:	8 Bytes */
554 #define PCMCIA_BSIZE_16		0x30000000	/* Bank size:  16 Bytes */
555 #define PCMCIA_BSIZE_32		0x38000000	/* Bank size:  32 Bytes */
556 #define PCMCIA_BSIZE_64		0x28000000	/* Bank size:  64 Bytes */
557 #define PCMCIA_BSIZE_128	0x20000000	/* Bank size: 128 Bytes */
558 #define PCMCIA_BSIZE_256	0x60000000	/* Bank size: 256 Bytes */
559 #define PCMCIA_BSIZE_512	0x68000000	/* Bank size: 512 Bytes */
560 #define PCMCIA_BSIZE_1K		0x78000000	/* Bank size:	1 kB	*/
561 #define PCMCIA_BSIZE_2K		0x70000000	/* Bank size:	2 kB	*/
562 #define PCMCIA_BSIZE_4K		0x50000000	/* Bank size:	4 kB	*/
563 #define PCMCIA_BSIZE_8K		0x58000000	/* Bank size:	8 kB	*/
564 #define PCMCIA_BSIZE_16K	0x48000000	/* Bank size:  16 kB	*/
565 #define PCMCIA_BSIZE_32K	0x40000000	/* Bank size:  32 kB	*/
566 #define PCMCIA_BSIZE_64K	0xC0000000	/* Bank size:  64 kB	*/
567 #define PCMCIA_BSIZE_128K	0xC8000000	/* Bank size: 128 kB	*/
568 #define PCMCIA_BSIZE_256K	0xD8000000	/* Bank size: 256 kB	*/
569 #define PCMCIA_BSIZE_512K	0xD0000000	/* Bank size: 512 kB	*/
570 #define PCMCIA_BSIZE_1M		0xF0000000	/* Bank size:	1 MB	*/
571 #define PCMCIA_BSIZE_2M		0xF8000000	/* Bank size:	2 MB	*/
572 #define PCMCIA_BSIZE_4M		0xE8000000	/* Bank size:	4 MB	*/
573 #define PCMCIA_BSIZE_8M		0xE0000000	/* Bank size:	8 MB	*/
574 #define PCMCIA_BSIZE_16M	0xA0000000	/* Bank size:  16 MB	*/
575 #define PCMCIA_BSIZE_32M	0xA8000000	/* Bank size:  32 MB	*/
576 #define PCMCIA_BSIZE_64M	0xB8000000	/* Bank size:  64 MB	*/
577 
578 /* PCMCIA Timing */
579 #define PCMCIA_SHT(t)	((t & 0x0F)<<16)	/* Strobe Hold	Time	*/
580 #define PCMCIA_SST(t)	((t & 0x0F)<<12)	/* Strobe Setup Time	*/
581 #define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length	*/
582 
583 /* PCMCIA Port Sizes */
584 #define PCMCIA_PPS_8		0x00000000	/*  8 bit port size	*/
585 #define PCMCIA_PPS_16		0x00000040	/* 16 bit port size	*/
586 
587 /* PCMCIA Region Select */
588 #define PCMCIA_PRS_MEM		0x00000000	/* Common Memory Space	*/
589 #define PCMCIA_PRS_ATTR		0x00000010	/*     Attribute Space	*/
590 #define PCMCIA_PRS_IO		0x00000018	/*	     I/O Space	*/
591 #define PCMCIA_PRS_DMA		0x00000020	/* DMA, normal transfer */
592 #define PCMCIA_PRS_DMA_LAST	0x00000028	/* DMA, last transactn	*/
593 #define PCMCIA_PRS_CEx		0x00000030	/* A[22:23] ==> CE1,CE2 */
594 
595 #define PCMCIA_PSLOT_A		0x00000000	/* Slot A		*/
596 #define PCMCIA_PSLOT_B		0x00000004	/* Slot B		*/
597 #define PCMCIA_WPROT		0x00000002	/* Write Protect	*/
598 #define PCMCIA_PV		0x00000001	/* Valid Bit		*/
599 
600 #define UPMA	0x00000000
601 #define UPMB	0x00800000
602 
603 #endif	/* __MPCXX_H__ */
604