1 /* 2 * Copyright 2006 Freescale Semiconductor. 3 * Jeffrey Brown 4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) 5 */ 6 7 #ifndef __MPC86xx_H__ 8 #define __MPC86xx_H__ 9 10 #include <asm/fsl_lbc.h> 11 12 #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ 13 #define _START_OFFSET EXC_OFF_SYS_RESET 14 15 /* 16 * platform register addresses 17 */ 18 19 #define GUTS_SVR (CONFIG_SYS_CCSRBAR + 0xE00A4) 20 #define MCM_ABCR (CONFIG_SYS_CCSRBAR + 0x01000) 21 #define MCM_DBCR (CONFIG_SYS_CCSRBAR + 0x01008) 22 23 /* 24 * l2cr values. Look in config_<BOARD>.h for the actual setup 25 */ 26 #define l2cr 1017 27 28 #define L2CR_L2E 0x80000000 /* bit 0 - enable */ 29 #define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ 30 #define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ 31 #define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ 32 #define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ 33 #define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ 34 #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ 35 #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ 36 37 /* 38 * BAT settings. Look in config_<BOARD>.h for the actual setup 39 */ 40 41 #define BATU_BL_128K 0x00000000 42 #define BATU_BL_256K 0x00000004 43 #define BATU_BL_512K 0x0000000c 44 #define BATU_BL_1M 0x0000001c 45 #define BATU_BL_2M 0x0000003c 46 #define BATU_BL_4M 0x0000007c 47 #define BATU_BL_8M 0x000000fc 48 #define BATU_BL_16M 0x000001fc 49 #define BATU_BL_32M 0x000003fc 50 #define BATU_BL_64M 0x000007fc 51 #define BATU_BL_128M 0x00000ffc 52 #define BATU_BL_256M 0x00001ffc 53 #define BATU_BL_512M 0x00003ffc 54 #define BATU_BL_1G 0x00007ffc 55 #define BATU_BL_2G 0x0000fffc 56 #define BATU_BL_4G 0x0001fffc 57 58 #define BATU_VS 0x00000002 59 #define BATU_VP 0x00000001 60 #define BATU_INVALID 0x00000000 61 62 #define BATL_WRITETHROUGH 0x00000040 63 #define BATL_CACHEINHIBIT 0x00000020 64 #define BATL_MEMCOHERENCE 0x00000010 65 #define BATL_GUARDEDSTORAGE 0x00000008 66 #define BATL_NO_ACCESS 0x00000000 67 68 #define BATL_PP_MSK 0x00000003 69 #define BATL_PP_00 0x00000000 /* No access */ 70 #define BATL_PP_01 0x00000001 /* Read-only */ 71 #define BATL_PP_10 0x00000002 /* Read-write */ 72 #define BATL_PP_11 0x00000003 73 74 #define BATL_PP_NO_ACCESS BATL_PP_00 75 #define BATL_PP_RO BATL_PP_01 76 #define BATL_PP_RW BATL_PP_10 77 78 #define HID0_XBSEN 0x00000100 79 #define HID0_HIGH_BAT_EN 0x00800000 80 #define HID0_XAEN 0x00020000 81 82 #ifndef __ASSEMBLY__ 83 84 typedef struct { 85 unsigned long freqProcessor; 86 unsigned long freqSystemBus; 87 unsigned long freqLocalBus; 88 } MPC86xx_SYS_INFO; 89 90 #define l1icache_enable icache_enable 91 92 void l2cache_enable(void); 93 void l1dcache_enable(void); 94 95 static __inline__ unsigned long get_hid0 (void) 96 { 97 unsigned long hid0; 98 asm volatile("mfspr %0, 1008" : "=r" (hid0) :); 99 return hid0; 100 } 101 102 static __inline__ unsigned long get_hid1 (void) 103 { 104 unsigned long hid1; 105 asm volatile("mfspr %0, 1009" : "=r" (hid1) :); 106 return hid1; 107 } 108 109 static __inline__ void set_hid0 (unsigned long hid0) 110 { 111 asm volatile("mtspr 1008, %0" : : "r" (hid0)); 112 } 113 114 static __inline__ void set_hid1 (unsigned long hid1) 115 { 116 asm volatile("mtspr 1009, %0" : : "r" (hid1)); 117 } 118 119 120 static __inline__ unsigned long get_l2cr (void) 121 { 122 unsigned long l2cr_val; 123 asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); 124 return l2cr_val; 125 } 126 127 #endif /* _ASMLANGUAGE */ 128 #endif /* __MPC86xx_H__ */ 129