1 /* 2 * Copyright 2004, 2007 Freescale Semiconductor. 3 * Copyright(c) 2003 Motorola Inc. 4 */ 5 6 #ifndef __MPC85xx_H__ 7 #define __MPC85xx_H__ 8 9 /* define for common ppc_asm.tmpl */ 10 #define EXC_OFF_SYS_RESET 0x100 /* System reset */ 11 #define _START_OFFSET 0 12 13 #if defined(CONFIG_E500) 14 #include <e500.h> 15 #endif 16 17 /* 18 * SCCR - System Clock Control Register, 9-8 19 */ 20 #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ 21 #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ 22 #define SCCR_DFBRG_SHIFT 0 23 24 #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ 25 #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ 26 #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ 27 #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ 28 29 #endif /* __MPC85xx_H__ */ 30