1 /* 2 * Copyright 2004 Freescale Semiconductor. 3 * Copyright(c) 2003 Motorola Inc. 4 * Xianghua Xiao (x.xiao@motorola.com) 5 */ 6 7 #ifndef __MPC85xx_H__ 8 #define __MPC85xx_H__ 9 10 #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ 11 12 #if defined(CONFIG_E500) 13 #include <e500.h> 14 #endif 15 16 /* 17 * SCCR - System Clock Control Register, 9-8 18 */ 19 #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ 20 #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ 21 #define SCCR_DFBRG_SHIFT 0 22 23 #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ 24 #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ 25 #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ 26 #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ 27 28 #endif /* __MPC85xx_H__ */ 29