1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #ifndef __MPC83XX_H__ 14 #define __MPC83XX_H__ 15 16 #include <config.h> 17 #include <asm/fsl_lbc.h> 18 #if defined(CONFIG_E300) 19 #include <asm/e300.h> 20 #endif 21 22 /* MPC83xx cpu provide RCR register to do reset thing specially 23 */ 24 #define MPC83xx_RESET 25 26 /* System reset offset (PowerPC standard) 27 */ 28 #define EXC_OFF_SYS_RESET 0x0100 29 #define _START_OFFSET EXC_OFF_SYS_RESET 30 31 /* IMMRBAR - Internal Memory Register Base Address 32 */ 33 #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 34 #define IMMRBAR 0x0000 /* Register offset to immr */ 35 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 36 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 37 38 /* LAWBAR - Local Access Window Base Address Register 39 */ 40 #define LBLAWBAR0 0x0020 /* Register offset to immr */ 41 #define LBLAWAR0 0x0024 42 #define LBLAWBAR1 0x0028 43 #define LBLAWAR1 0x002C 44 #define LBLAWBAR2 0x0030 45 #define LBLAWAR2 0x0034 46 #define LBLAWBAR3 0x0038 47 #define LBLAWAR3 0x003C 48 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 49 50 /* SPRIDR - System Part and Revision ID Register 51 */ 52 #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ 53 #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ 54 55 #if defined(CONFIG_MPC834X) 56 #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) 57 #define REVID_MINOR(spridr) (spridr & 0x000000FF) 58 #else 59 #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) 60 #define REVID_MINOR(spridr) (spridr & 0x0000000F) 61 #endif 62 63 #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) 64 #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) 65 66 #define SPR_831X_FAMILY 0x80B 67 #define SPR_8311 0x80B2 68 #define SPR_8313 0x80B0 69 #define SPR_8314 0x80B6 70 #define SPR_8315 0x80B4 71 #define SPR_832X_FAMILY 0x806 72 #define SPR_8321 0x8066 73 #define SPR_8323 0x8062 74 #define SPR_834X_FAMILY 0x803 75 #define SPR_8343 0x8036 76 #define SPR_8347_TBGA_ 0x8032 77 #define SPR_8347_PBGA_ 0x8034 78 #define SPR_8349 0x8030 79 #define SPR_836X_FAMILY 0x804 80 #define SPR_8358_TBGA_ 0x804A 81 #define SPR_8358_PBGA_ 0x804E 82 #define SPR_8360 0x8048 83 #define SPR_837X_FAMILY 0x80C 84 #define SPR_8377 0x80C6 85 #define SPR_8378 0x80C4 86 #define SPR_8379 0x80C2 87 88 /* SPCR - System Priority Configuration Register 89 */ 90 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 91 #define SPCR_PCIHPE_SHIFT (31-3) 92 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 93 #define SPCR_PCIPR_SHIFT (31-7) 94 #define SPCR_OPT 0x00800000 /* Optimize */ 95 #define SPCR_OPT_SHIFT (31-8) 96 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 97 #define SPCR_TBEN_SHIFT (31-9) 98 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 99 #define SPCR_COREPR_SHIFT (31-11) 100 101 #if defined(CONFIG_MPC834X) 102 /* SPCR bits - MPC8349 specific */ 103 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 104 #define SPCR_TSEC1DP_SHIFT (31-19) 105 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 106 #define SPCR_TSEC1BDP_SHIFT (31-21) 107 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 108 #define SPCR_TSEC1EP_SHIFT (31-23) 109 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 110 #define SPCR_TSEC2DP_SHIFT (31-27) 111 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 112 #define SPCR_TSEC2BDP_SHIFT (31-29) 113 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 114 #define SPCR_TSEC2EP_SHIFT (31-31) 115 116 #elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 117 /* SPCR bits - MPC831x and MPC837x specific */ 118 #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 119 #define SPCR_TSECDP_SHIFT (31-19) 120 #define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */ 121 #define SPCR_TSECBDP_SHIFT (31-21) 122 #define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */ 123 #define SPCR_TSECEP_SHIFT (31-23) 124 #endif 125 126 /* SICRL/H - System I/O Configuration Register Low/High 127 */ 128 #if defined(CONFIG_MPC834X) 129 /* SICRL bits - MPC8349 specific */ 130 #define SICRL_LDP_A 0x80000000 131 #define SICRL_USB1 0x40000000 132 #define SICRL_USB0 0x20000000 133 #define SICRL_UART 0x0C000000 134 #define SICRL_GPIO1_A 0x02000000 135 #define SICRL_GPIO1_B 0x01000000 136 #define SICRL_GPIO1_C 0x00800000 137 #define SICRL_GPIO1_D 0x00400000 138 #define SICRL_GPIO1_E 0x00200000 139 #define SICRL_GPIO1_F 0x00180000 140 #define SICRL_GPIO1_G 0x00040000 141 #define SICRL_GPIO1_H 0x00020000 142 #define SICRL_GPIO1_I 0x00010000 143 #define SICRL_GPIO1_J 0x00008000 144 #define SICRL_GPIO1_K 0x00004000 145 #define SICRL_GPIO1_L 0x00003000 146 147 /* SICRH bits - MPC8349 specific */ 148 #define SICRH_DDR 0x80000000 149 #define SICRH_TSEC1_A 0x10000000 150 #define SICRH_TSEC1_B 0x08000000 151 #define SICRH_TSEC1_C 0x04000000 152 #define SICRH_TSEC1_D 0x02000000 153 #define SICRH_TSEC1_E 0x01000000 154 #define SICRH_TSEC1_F 0x00800000 155 #define SICRH_TSEC2_A 0x00400000 156 #define SICRH_TSEC2_B 0x00200000 157 #define SICRH_TSEC2_C 0x00100000 158 #define SICRH_TSEC2_D 0x00080000 159 #define SICRH_TSEC2_E 0x00040000 160 #define SICRH_TSEC2_F 0x00020000 161 #define SICRH_TSEC2_G 0x00010000 162 #define SICRH_TSEC2_H 0x00008000 163 #define SICRH_GPIO2_A 0x00004000 164 #define SICRH_GPIO2_B 0x00002000 165 #define SICRH_GPIO2_C 0x00001000 166 #define SICRH_GPIO2_D 0x00000800 167 #define SICRH_GPIO2_E 0x00000400 168 #define SICRH_GPIO2_F 0x00000200 169 #define SICRH_GPIO2_G 0x00000180 170 #define SICRH_GPIO2_H 0x00000060 171 #define SICRH_TSOBI1 0x00000002 172 #define SICRH_TSOBI2 0x00000001 173 174 #elif defined(CONFIG_MPC8360) 175 /* SICRL bits - MPC8360 specific */ 176 #define SICRL_LDP_A 0xC0000000 177 #define SICRL_LCLK_1 0x10000000 178 #define SICRL_LCLK_2 0x08000000 179 #define SICRL_SRCID_A 0x03000000 180 #define SICRL_IRQ_CKSTP_A 0x00C00000 181 182 /* SICRH bits - MPC8360 specific */ 183 #define SICRH_DDR 0x80000000 184 #define SICRH_SECONDARY_DDR 0x40000000 185 #define SICRH_SDDROE 0x20000000 186 #define SICRH_IRQ3 0x10000000 187 #define SICRH_UC1EOBI 0x00000004 188 #define SICRH_UC2E1OBI 0x00000002 189 #define SICRH_UC2E2OBI 0x00000001 190 191 #elif defined(CONFIG_MPC832X) 192 /* SICRL bits - MPC832X specific */ 193 #define SICRL_LDP_LCS_A 0x80000000 194 #define SICRL_IRQ_CKS 0x20000000 195 #define SICRL_PCI_MSRC 0x10000000 196 #define SICRL_URT_CTPR 0x06000000 197 #define SICRL_IRQ_CTPR 0x00C00000 198 199 #elif defined(CONFIG_MPC8313) 200 /* SICRL bits - MPC8313 specific */ 201 #define SICRL_LBC 0x30000000 202 #define SICRL_UART 0x0C000000 203 #define SICRL_SPI_A 0x03000000 204 #define SICRL_SPI_B 0x00C00000 205 #define SICRL_SPI_C 0x00300000 206 #define SICRL_SPI_D 0x000C0000 207 #define SICRL_USBDR 0x00000C00 208 #define SICRL_ETSEC1_A 0x0000000C 209 #define SICRL_ETSEC2_A 0x00000003 210 211 /* SICRH bits - MPC8313 specific */ 212 #define SICRH_INTR_A 0x02000000 213 #define SICRH_INTR_B 0x00C00000 214 #define SICRH_IIC 0x00300000 215 #define SICRH_ETSEC2_B 0x000C0000 216 #define SICRH_ETSEC2_C 0x00030000 217 #define SICRH_ETSEC2_D 0x0000C000 218 #define SICRH_ETSEC2_E 0x00003000 219 #define SICRH_ETSEC2_F 0x00000C00 220 #define SICRH_ETSEC2_G 0x00000300 221 #define SICRH_ETSEC1_B 0x00000080 222 #define SICRH_ETSEC1_C 0x00000060 223 #define SICRH_GTX1_DLY 0x00000008 224 #define SICRH_GTX2_DLY 0x00000004 225 #define SICRH_TSOBI1 0x00000002 226 #define SICRH_TSOBI2 0x00000001 227 228 #elif defined(CONFIG_MPC8315) 229 /* SICRL bits - MPC8315 specific */ 230 #define SICRL_DMA_CH0 0xc0000000 231 #define SICRL_DMA_SPI 0x30000000 232 #define SICRL_UART 0x0c000000 233 #define SICRL_IRQ4 0x02000000 234 #define SICRL_IRQ5 0x01800000 235 #define SICRL_IRQ6_7 0x00400000 236 #define SICRL_IIC1 0x00300000 237 #define SICRL_TDM 0x000c0000 238 #define SICRL_TDM_SHARED 0x00030000 239 #define SICRL_PCI_A 0x0000c000 240 #define SICRL_ELBC_A 0x00003000 241 #define SICRL_ETSEC1_A 0x000000c0 242 #define SICRL_ETSEC1_B 0x00000030 243 #define SICRL_ETSEC1_C 0x0000000c 244 #define SICRL_TSEXPOBI 0x00000001 245 246 /* SICRH bits - MPC8315 specific */ 247 #define SICRH_GPIO_0 0xc0000000 248 #define SICRH_GPIO_1 0x30000000 249 #define SICRH_GPIO_2 0x0c000000 250 #define SICRH_GPIO_3 0x03000000 251 #define SICRH_GPIO_4 0x00c00000 252 #define SICRH_GPIO_5 0x00300000 253 #define SICRH_GPIO_6 0x000c0000 254 #define SICRH_GPIO_7 0x00030000 255 #define SICRH_GPIO_8 0x0000c000 256 #define SICRH_GPIO_9 0x00003000 257 #define SICRH_GPIO_10 0x00000c00 258 #define SICRH_GPIO_11 0x00000300 259 #define SICRH_ETSEC2_A 0x000000c0 260 #define SICRH_TSOBI1 0x00000002 261 #define SICRH_TSOBI2 0x00000001 262 263 #elif defined(CONFIG_MPC837X) 264 /* SICRL bits - MPC837x specific */ 265 #define SICRL_USB_A 0xC0000000 266 #define SICRL_USB_B 0x30000000 267 #define SICRL_UART 0x0C000000 268 #define SICRL_GPIO_A 0x02000000 269 #define SICRL_GPIO_B 0x01000000 270 #define SICRL_GPIO_C 0x00800000 271 #define SICRL_GPIO_D 0x00400000 272 #define SICRL_GPIO_E 0x00200000 273 #define SICRL_GPIO_F 0x00180000 274 #define SICRL_GPIO_G 0x00040000 275 #define SICRL_GPIO_H 0x00020000 276 #define SICRL_GPIO_I 0x00010000 277 #define SICRL_GPIO_J 0x00008000 278 #define SICRL_GPIO_K 0x00004000 279 #define SICRL_GPIO_L 0x00003000 280 #define SICRL_DMA_A 0x00000800 281 #define SICRL_DMA_B 0x00000400 282 #define SICRL_DMA_C 0x00000200 283 #define SICRL_DMA_D 0x00000100 284 #define SICRL_DMA_E 0x00000080 285 #define SICRL_DMA_F 0x00000040 286 #define SICRL_DMA_G 0x00000020 287 #define SICRL_DMA_H 0x00000010 288 #define SICRL_DMA_I 0x00000008 289 #define SICRL_DMA_J 0x00000004 290 #define SICRL_LDP_A 0x00000002 291 #define SICRL_LDP_B 0x00000001 292 293 /* SICRH bits - MPC837x specific */ 294 #define SICRH_DDR 0x80000000 295 #define SICRH_TSEC1_A 0x10000000 296 #define SICRH_TSEC1_B 0x08000000 297 #define SICRH_TSEC2_A 0x00400000 298 #define SICRH_TSEC2_B 0x00200000 299 #define SICRH_TSEC2_C 0x00100000 300 #define SICRH_TSEC2_D 0x00080000 301 #define SICRH_TSEC2_E 0x00040000 302 #define SICRH_TMR 0x00010000 303 #define SICRH_GPIO2_A 0x00008000 304 #define SICRH_GPIO2_B 0x00004000 305 #define SICRH_GPIO2_C 0x00002000 306 #define SICRH_GPIO2_D 0x00001000 307 #define SICRH_GPIO2_E 0x00000C00 308 #define SICRH_GPIO2_F 0x00000300 309 #define SICRH_GPIO2_G 0x000000C0 310 #define SICRH_GPIO2_H 0x00000030 311 #define SICRH_SPI 0x00000003 312 #endif 313 314 /* SWCRR - System Watchdog Control Register 315 */ 316 #define SWCRR 0x0204 /* Register offset to immr */ 317 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 318 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 319 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 320 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 321 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 322 323 /* SWCNR - System Watchdog Counter Register 324 */ 325 #define SWCNR 0x0208 /* Register offset to immr */ 326 #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 327 #define SWCNR_RES ~(SWCNR_SWCN) 328 329 /* SWSRR - System Watchdog Service Register 330 */ 331 #define SWSRR 0x020E /* Register offset to immr */ 332 333 /* ACR - Arbiter Configuration Register 334 */ 335 #define ACR_COREDIS 0x10000000 /* Core disable */ 336 #define ACR_COREDIS_SHIFT (31-7) 337 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 338 #define ACR_PIPE_DEP_SHIFT (31-15) 339 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 340 #define ACR_PCI_RPTCNT_SHIFT (31-19) 341 #define ACR_RPTCNT 0x00000700 /* Repeat count */ 342 #define ACR_RPTCNT_SHIFT (31-23) 343 #define ACR_APARK 0x00000030 /* Address parking */ 344 #define ACR_APARK_SHIFT (31-27) 345 #define ACR_PARKM 0x0000000F /* Parking master */ 346 #define ACR_PARKM_SHIFT (31-31) 347 348 /* ATR - Arbiter Timers Register 349 */ 350 #define ATR_DTO 0x00FF0000 /* Data time out */ 351 #define ATR_ATO 0x000000FF /* Address time out */ 352 353 /* AER - Arbiter Event Register 354 */ 355 #define AER_ETEA 0x00000020 /* Transfer error */ 356 #define AER_RES 0x00000010 /* Reserved transfer type */ 357 #define AER_ECW 0x00000008 /* External control word transfer type */ 358 #define AER_AO 0x00000004 /* Address Only transfer type */ 359 #define AER_DTO 0x00000002 /* Data time out */ 360 #define AER_ATO 0x00000001 /* Address time out */ 361 362 /* AEATR - Arbiter Event Address Register 363 */ 364 #define AEATR_EVENT 0x07000000 /* Event type */ 365 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 366 #define AEATR_TBST 0x00000800 /* Transfer burst */ 367 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 368 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 369 370 /* HRCWL - Hard Reset Configuration Word Low 371 */ 372 #define HRCWL_LBIUCM 0x80000000 373 #define HRCWL_LBIUCM_SHIFT 31 374 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 375 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 376 377 #define HRCWL_DDRCM 0x40000000 378 #define HRCWL_DDRCM_SHIFT 30 379 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 380 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 381 382 #define HRCWL_SPMF 0x0f000000 383 #define HRCWL_SPMF_SHIFT 24 384 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 385 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 386 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 387 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 388 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 389 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 390 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 391 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 392 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 393 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 394 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 395 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 396 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 397 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 398 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 399 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 400 401 #define HRCWL_VCO_BYPASS 0x00000000 402 #define HRCWL_VCO_1X2 0x00000000 403 #define HRCWL_VCO_1X4 0x00200000 404 #define HRCWL_VCO_1X8 0x00400000 405 406 #define HRCWL_COREPLL 0x007F0000 407 #define HRCWL_COREPLL_SHIFT 16 408 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 409 #define HRCWL_CORE_TO_CSB_1X1 0x00020000 410 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 411 #define HRCWL_CORE_TO_CSB_2X1 0x00040000 412 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 413 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 414 415 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 416 #define HRCWL_CEVCOD 0x000000C0 417 #define HRCWL_CEVCOD_SHIFT 6 418 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 419 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 420 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 421 422 #define HRCWL_CEPDF 0x00000020 423 #define HRCWL_CEPDF_SHIFT 5 424 #define HRCWL_CE_PLL_DIV_1X1 0x00000000 425 #define HRCWL_CE_PLL_DIV_2X1 0x00000020 426 427 #define HRCWL_CEPMF 0x0000001F 428 #define HRCWL_CEPMF_SHIFT 0 429 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 430 #define HRCWL_CE_TO_PLL_1X2 0x00000002 431 #define HRCWL_CE_TO_PLL_1X3 0x00000003 432 #define HRCWL_CE_TO_PLL_1X4 0x00000004 433 #define HRCWL_CE_TO_PLL_1X5 0x00000005 434 #define HRCWL_CE_TO_PLL_1X6 0x00000006 435 #define HRCWL_CE_TO_PLL_1X7 0x00000007 436 #define HRCWL_CE_TO_PLL_1X8 0x00000008 437 #define HRCWL_CE_TO_PLL_1X9 0x00000009 438 #define HRCWL_CE_TO_PLL_1X10 0x0000000A 439 #define HRCWL_CE_TO_PLL_1X11 0x0000000B 440 #define HRCWL_CE_TO_PLL_1X12 0x0000000C 441 #define HRCWL_CE_TO_PLL_1X13 0x0000000D 442 #define HRCWL_CE_TO_PLL_1X14 0x0000000E 443 #define HRCWL_CE_TO_PLL_1X15 0x0000000F 444 #define HRCWL_CE_TO_PLL_1X16 0x00000010 445 #define HRCWL_CE_TO_PLL_1X17 0x00000011 446 #define HRCWL_CE_TO_PLL_1X18 0x00000012 447 #define HRCWL_CE_TO_PLL_1X19 0x00000013 448 #define HRCWL_CE_TO_PLL_1X20 0x00000014 449 #define HRCWL_CE_TO_PLL_1X21 0x00000015 450 #define HRCWL_CE_TO_PLL_1X22 0x00000016 451 #define HRCWL_CE_TO_PLL_1X23 0x00000017 452 #define HRCWL_CE_TO_PLL_1X24 0x00000018 453 #define HRCWL_CE_TO_PLL_1X25 0x00000019 454 #define HRCWL_CE_TO_PLL_1X26 0x0000001A 455 #define HRCWL_CE_TO_PLL_1X27 0x0000001B 456 #define HRCWL_CE_TO_PLL_1X28 0x0000001C 457 #define HRCWL_CE_TO_PLL_1X29 0x0000001D 458 #define HRCWL_CE_TO_PLL_1X30 0x0000001E 459 #define HRCWL_CE_TO_PLL_1X31 0x0000001F 460 461 #elif defined(CONFIG_MPC8315) 462 #define HRCWL_SVCOD 0x30000000 463 #define HRCWL_SVCOD_SHIFT 28 464 #define HRCWL_SVCOD_DIV_2 0x00000000 465 #define HRCWL_SVCOD_DIV_4 0x10000000 466 #define HRCWL_SVCOD_DIV_8 0x20000000 467 #define HRCWL_SVCOD_DIV_1 0x30000000 468 469 #elif defined(CONFIG_MPC837X) 470 #define HRCWL_SVCOD 0x30000000 471 #define HRCWL_SVCOD_SHIFT 28 472 #define HRCWL_SVCOD_DIV_4 0x00000000 473 #define HRCWL_SVCOD_DIV_8 0x10000000 474 #define HRCWL_SVCOD_DIV_2 0x20000000 475 #define HRCWL_SVCOD_DIV_1 0x30000000 476 #endif 477 478 /* HRCWH - Hardware Reset Configuration Word High 479 */ 480 #define HRCWH_PCI_HOST 0x80000000 481 #define HRCWH_PCI_HOST_SHIFT 31 482 #define HRCWH_PCI_AGENT 0x00000000 483 484 #if defined(CONFIG_MPC834X) 485 #define HRCWH_32_BIT_PCI 0x00000000 486 #define HRCWH_64_BIT_PCI 0x40000000 487 #endif 488 489 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 490 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 491 492 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 493 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 494 495 #if defined(CONFIG_MPC834X) 496 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 497 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 498 499 #elif defined(CONFIG_MPC8360) 500 #define HRCWH_PCICKDRV_DISABLE 0x00000000 501 #define HRCWH_PCICKDRV_ENABLE 0x10000000 502 #endif 503 504 #define HRCWH_CORE_DISABLE 0x08000000 505 #define HRCWH_CORE_ENABLE 0x00000000 506 507 #define HRCWH_FROM_0X00000100 0x00000000 508 #define HRCWH_FROM_0XFFF00100 0x04000000 509 510 #define HRCWH_BOOTSEQ_DISABLE 0x00000000 511 #define HRCWH_BOOTSEQ_NORMAL 0x01000000 512 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 513 514 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 515 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 516 517 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 518 #define HRCWH_ROM_LOC_PCI1 0x00100000 519 #if defined(CONFIG_MPC834X) 520 #define HRCWH_ROM_LOC_PCI2 0x00200000 521 #endif 522 #if defined(CONIFG_MPC837X) 523 #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 524 #endif 525 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 526 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 527 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 528 529 #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 530 #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 531 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 532 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 533 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 534 535 #define HRCWH_RL_EXT_LEGACY 0x00000000 536 #define HRCWH_RL_EXT_NAND 0x00040000 537 538 #define HRCWH_TSEC1M_IN_MII 0x00000000 539 #define HRCWH_TSEC1M_IN_RMII 0x00002000 540 #define HRCWH_TSEC1M_IN_RGMII 0x00006000 541 #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 542 #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 543 544 #define HRCWH_TSEC2M_IN_MII 0x00000000 545 #define HRCWH_TSEC2M_IN_RMII 0x00000400 546 #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 547 #define HRCWH_TSEC2M_IN_RTBI 0x00001400 548 #define HRCWH_TSEC2M_IN_SGMII 0x00001800 549 #endif 550 551 #if defined(CONFIG_MPC834X) 552 #define HRCWH_TSEC1M_IN_RGMII 0x00000000 553 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 554 #define HRCWH_TSEC1M_IN_GMII 0x00008000 555 #define HRCWH_TSEC1M_IN_TBI 0x0000C000 556 #define HRCWH_TSEC2M_IN_RGMII 0x00000000 557 #define HRCWH_TSEC2M_IN_RTBI 0x00001000 558 #define HRCWH_TSEC2M_IN_GMII 0x00002000 559 #define HRCWH_TSEC2M_IN_TBI 0x00003000 560 #endif 561 562 #if defined(CONFIG_MPC8360) 563 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 564 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 565 #endif 566 567 #define HRCWH_BIG_ENDIAN 0x00000000 568 #define HRCWH_LITTLE_ENDIAN 0x00000008 569 570 #define HRCWH_LALE_NORMAL 0x00000000 571 #define HRCWH_LALE_EARLY 0x00000004 572 573 #define HRCWH_LDP_SET 0x00000000 574 #define HRCWH_LDP_CLEAR 0x00000002 575 576 /* RSR - Reset Status Register 577 */ 578 #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 579 #define RSR_RSTSRC 0xF0000000 /* Reset source */ 580 #define RSR_RSTSRC_SHIFT 28 581 #else 582 #define RSR_RSTSRC 0xE0000000 /* Reset source */ 583 #define RSR_RSTSRC_SHIFT 29 584 #endif 585 #define RSR_BSF 0x00010000 /* Boot seq. fail */ 586 #define RSR_BSF_SHIFT 16 587 #define RSR_SWSR 0x00002000 /* software soft reset */ 588 #define RSR_SWSR_SHIFT 13 589 #define RSR_SWHR 0x00001000 /* software hard reset */ 590 #define RSR_SWHR_SHIFT 12 591 #define RSR_JHRS 0x00000200 /* jtag hreset */ 592 #define RSR_JHRS_SHIFT 9 593 #define RSR_JSRS 0x00000100 /* jtag sreset status */ 594 #define RSR_JSRS_SHIFT 8 595 #define RSR_CSHR 0x00000010 /* checkstop reset status */ 596 #define RSR_CSHR_SHIFT 4 597 #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 598 #define RSR_SWRS_SHIFT 3 599 #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 600 #define RSR_BMRS_SHIFT 2 601 #define RSR_SRS 0x00000002 /* soft reset status */ 602 #define RSR_SRS_SHIFT 1 603 #define RSR_HRS 0x00000001 /* hard reset status */ 604 #define RSR_HRS_SHIFT 0 605 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 606 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 607 RSR_BMRS | RSR_SRS | RSR_HRS) 608 /* RMR - Reset Mode Register 609 */ 610 #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 611 #define RMR_CSRE_SHIFT 0 612 #define RMR_RES ~(RMR_CSRE) 613 614 /* RCR - Reset Control Register 615 */ 616 #define RCR_SWHR 0x00000002 /* software hard reset */ 617 #define RCR_SWSR 0x00000001 /* software soft reset */ 618 #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 619 620 /* RCER - Reset Control Enable Register 621 */ 622 #define RCER_CRE 0x00000001 /* software hard reset */ 623 #define RCER_RES ~(RCER_CRE) 624 625 /* SPMR - System PLL Mode Register 626 */ 627 #define SPMR_LBIUCM 0x80000000 628 #define SPMR_DDRCM 0x40000000 629 #define SPMR_SPMF 0x0F000000 630 #define SPMR_CKID 0x00800000 631 #define SPMR_CKID_SHIFT 23 632 #define SPMR_COREPLL 0x007F0000 633 #define SPMR_CEVCOD 0x000000C0 634 #define SPMR_CEPDF 0x00000020 635 #define SPMR_CEPMF 0x0000001F 636 637 /* OCCR - Output Clock Control Register 638 */ 639 #define OCCR_PCICOE0 0x80000000 640 #define OCCR_PCICOE1 0x40000000 641 #define OCCR_PCICOE2 0x20000000 642 #define OCCR_PCICOE3 0x10000000 643 #define OCCR_PCICOE4 0x08000000 644 #define OCCR_PCICOE5 0x04000000 645 #define OCCR_PCICOE6 0x02000000 646 #define OCCR_PCICOE7 0x01000000 647 #define OCCR_PCICD0 0x00800000 648 #define OCCR_PCICD1 0x00400000 649 #define OCCR_PCICD2 0x00200000 650 #define OCCR_PCICD3 0x00100000 651 #define OCCR_PCICD4 0x00080000 652 #define OCCR_PCICD5 0x00040000 653 #define OCCR_PCICD6 0x00020000 654 #define OCCR_PCICD7 0x00010000 655 #define OCCR_PCI1CR 0x00000002 656 #define OCCR_PCI2CR 0x00000001 657 #define OCCR_PCICR OCCR_PCI1CR 658 659 /* SCCR - System Clock Control Register 660 */ 661 #define SCCR_ENCCM 0x03000000 662 #define SCCR_ENCCM_SHIFT 24 663 #define SCCR_ENCCM_0 0x00000000 664 #define SCCR_ENCCM_1 0x01000000 665 #define SCCR_ENCCM_2 0x02000000 666 #define SCCR_ENCCM_3 0x03000000 667 668 #define SCCR_PCICM 0x00010000 669 #define SCCR_PCICM_SHIFT 16 670 671 #if defined(CONFIG_MPC834X) 672 /* SCCR bits - MPC834x specific */ 673 #define SCCR_TSEC1CM 0xc0000000 674 #define SCCR_TSEC1CM_SHIFT 30 675 #define SCCR_TSEC1CM_0 0x00000000 676 #define SCCR_TSEC1CM_1 0x40000000 677 #define SCCR_TSEC1CM_2 0x80000000 678 #define SCCR_TSEC1CM_3 0xC0000000 679 680 #define SCCR_TSEC2CM 0x30000000 681 #define SCCR_TSEC2CM_SHIFT 28 682 #define SCCR_TSEC2CM_0 0x00000000 683 #define SCCR_TSEC2CM_1 0x10000000 684 #define SCCR_TSEC2CM_2 0x20000000 685 #define SCCR_TSEC2CM_3 0x30000000 686 687 /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 688 #define SCCR_USBMPHCM 0x00c00000 689 #define SCCR_USBMPHCM_SHIFT 22 690 #define SCCR_USBDRCM 0x00300000 691 #define SCCR_USBDRCM_SHIFT 20 692 #define SCCR_USBCM 0x00f00000 693 #define SCCR_USBCM_SHIFT 20 694 #define SCCR_USBCM_0 0x00000000 695 #define SCCR_USBCM_1 0x00500000 696 #define SCCR_USBCM_2 0x00A00000 697 #define SCCR_USBCM_3 0x00F00000 698 699 #elif defined(CONFIG_MPC8313) 700 /* TSEC1 bits are for TSEC2 as well */ 701 #define SCCR_TSEC1CM 0xc0000000 702 #define SCCR_TSEC1CM_SHIFT 30 703 #define SCCR_TSEC1CM_0 0x00000000 704 #define SCCR_TSEC1CM_1 0x40000000 705 #define SCCR_TSEC1CM_2 0x80000000 706 #define SCCR_TSEC1CM_3 0xC0000000 707 708 #define SCCR_TSEC1ON 0x20000000 709 #define SCCR_TSEC1ON_SHIFT 29 710 #define SCCR_TSEC2ON 0x10000000 711 #define SCCR_TSEC2ON_SHIFT 28 712 713 #define SCCR_USBDRCM 0x00300000 714 #define SCCR_USBDRCM_SHIFT 20 715 #define SCCR_USBDRCM_0 0x00000000 716 #define SCCR_USBDRCM_1 0x00100000 717 #define SCCR_USBDRCM_2 0x00200000 718 #define SCCR_USBDRCM_3 0x00300000 719 720 #elif defined(CONFIG_MPC8315) 721 /* SCCR bits - MPC8315 specific */ 722 #define SCCR_TSEC1CM 0xc0000000 723 #define SCCR_TSEC1CM_SHIFT 30 724 #define SCCR_TSEC1CM_0 0x00000000 725 #define SCCR_TSEC1CM_1 0x40000000 726 #define SCCR_TSEC1CM_2 0x80000000 727 #define SCCR_TSEC1CM_3 0xC0000000 728 729 #define SCCR_TSEC2CM 0x30000000 730 #define SCCR_TSEC2CM_SHIFT 28 731 #define SCCR_TSEC2CM_0 0x00000000 732 #define SCCR_TSEC2CM_1 0x10000000 733 #define SCCR_TSEC2CM_2 0x20000000 734 #define SCCR_TSEC2CM_3 0x30000000 735 736 #define SCCR_USBDRCM 0x00c00000 737 #define SCCR_USBDRCM_SHIFT 22 738 #define SCCR_USBDRCM_0 0x00000000 739 #define SCCR_USBDRCM_1 0x00400000 740 #define SCCR_USBDRCM_2 0x00800000 741 #define SCCR_USBDRCM_3 0x00c00000 742 743 #define SCCR_PCIEXP1CM 0x00300000 744 #define SCCR_PCIEXP2CM 0x000c0000 745 746 #define SCCR_SATA1CM 0x00003000 747 #define SCCR_SATA1CM_SHIFT 12 748 #define SCCR_SATACM 0x00003c00 749 #define SCCR_SATACM_SHIFT 10 750 #define SCCR_SATACM_0 0x00000000 751 #define SCCR_SATACM_1 0x00001400 752 #define SCCR_SATACM_2 0x00002800 753 #define SCCR_SATACM_3 0x00003c00 754 755 #define SCCR_TDMCM 0x00000030 756 #define SCCR_TDMCM_SHIFT 4 757 #define SCCR_TDMCM_0 0x00000000 758 #define SCCR_TDMCM_1 0x00000010 759 #define SCCR_TDMCM_2 0x00000020 760 #define SCCR_TDMCM_3 0x00000030 761 762 #elif defined(CONFIG_MPC837X) 763 /* SCCR bits - MPC837x specific */ 764 #define SCCR_TSEC1CM 0xc0000000 765 #define SCCR_TSEC1CM_SHIFT 30 766 #define SCCR_TSEC1CM_0 0x00000000 767 #define SCCR_TSEC1CM_1 0x40000000 768 #define SCCR_TSEC1CM_2 0x80000000 769 #define SCCR_TSEC1CM_3 0xC0000000 770 771 #define SCCR_TSEC2CM 0x30000000 772 #define SCCR_TSEC2CM_SHIFT 28 773 #define SCCR_TSEC2CM_0 0x00000000 774 #define SCCR_TSEC2CM_1 0x10000000 775 #define SCCR_TSEC2CM_2 0x20000000 776 #define SCCR_TSEC2CM_3 0x30000000 777 778 #define SCCR_SDHCCM 0x0c000000 779 #define SCCR_SDHCCM_SHIFT 26 780 #define SCCR_SDHCCM_0 0x00000000 781 #define SCCR_SDHCCM_1 0x04000000 782 #define SCCR_SDHCCM_2 0x08000000 783 #define SCCR_SDHCCM_3 0x0c000000 784 785 #define SCCR_USBDRCM 0x00c00000 786 #define SCCR_USBDRCM_SHIFT 22 787 #define SCCR_USBDRCM_0 0x00000000 788 #define SCCR_USBDRCM_1 0x00400000 789 #define SCCR_USBDRCM_2 0x00800000 790 #define SCCR_USBDRCM_3 0x00c00000 791 792 #define SCCR_PCIEXP1CM 0x00300000 793 #define SCCR_PCIEXP1CM_SHIFT 20 794 #define SCCR_PCIEXP1CM_0 0x00000000 795 #define SCCR_PCIEXP1CM_1 0x00100000 796 #define SCCR_PCIEXP1CM_2 0x00200000 797 #define SCCR_PCIEXP1CM_3 0x00300000 798 799 #define SCCR_PCIEXP2CM 0x000c0000 800 #define SCCR_PCIEXP2CM_SHIFT 18 801 #define SCCR_PCIEXP2CM_0 0x00000000 802 #define SCCR_PCIEXP2CM_1 0x00040000 803 #define SCCR_PCIEXP2CM_2 0x00080000 804 #define SCCR_PCIEXP2CM_3 0x000c0000 805 806 /* All of the four SATA controllers must have the same clock ratio */ 807 #define SCCR_SATA1CM 0x000000c0 808 #define SCCR_SATA1CM_SHIFT 6 809 #define SCCR_SATACM 0x000000ff 810 #define SCCR_SATACM_SHIFT 0 811 #define SCCR_SATACM_0 0x00000000 812 #define SCCR_SATACM_1 0x00000055 813 #define SCCR_SATACM_2 0x000000aa 814 #define SCCR_SATACM_3 0x000000ff 815 #endif 816 817 /* CSn_BDNS - Chip Select memory Bounds Register 818 */ 819 #define CSBNDS_SA 0x00FF0000 820 #define CSBNDS_SA_SHIFT 8 821 #define CSBNDS_EA 0x000000FF 822 #define CSBNDS_EA_SHIFT 24 823 824 /* CSn_CONFIG - Chip Select Configuration Register 825 */ 826 #define CSCONFIG_EN 0x80000000 827 #define CSCONFIG_AP 0x00800000 828 #define CSCONFIG_ODT_WR_ACS 0x00010000 829 #define CSCONFIG_BANK_BIT_3 0x00004000 830 #define CSCONFIG_ROW_BIT 0x00000700 831 #define CSCONFIG_ROW_BIT_12 0x00000000 832 #define CSCONFIG_ROW_BIT_13 0x00000100 833 #define CSCONFIG_ROW_BIT_14 0x00000200 834 #define CSCONFIG_COL_BIT 0x00000007 835 #define CSCONFIG_COL_BIT_8 0x00000000 836 #define CSCONFIG_COL_BIT_9 0x00000001 837 #define CSCONFIG_COL_BIT_10 0x00000002 838 #define CSCONFIG_COL_BIT_11 0x00000003 839 840 /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 841 */ 842 #define TIMING_CFG0_RWT 0xC0000000 843 #define TIMING_CFG0_RWT_SHIFT 30 844 #define TIMING_CFG0_WRT 0x30000000 845 #define TIMING_CFG0_WRT_SHIFT 28 846 #define TIMING_CFG0_RRT 0x0C000000 847 #define TIMING_CFG0_RRT_SHIFT 26 848 #define TIMING_CFG0_WWT 0x03000000 849 #define TIMING_CFG0_WWT_SHIFT 24 850 #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 851 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 852 #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 853 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 854 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 855 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 856 #define TIMING_CFG0_MRS_CYC 0x0000000F 857 #define TIMING_CFG0_MRS_CYC_SHIFT 0 858 859 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 860 */ 861 #define TIMING_CFG1_PRETOACT 0x70000000 862 #define TIMING_CFG1_PRETOACT_SHIFT 28 863 #define TIMING_CFG1_ACTTOPRE 0x0F000000 864 #define TIMING_CFG1_ACTTOPRE_SHIFT 24 865 #define TIMING_CFG1_ACTTORW 0x00700000 866 #define TIMING_CFG1_ACTTORW_SHIFT 20 867 #define TIMING_CFG1_CASLAT 0x00070000 868 #define TIMING_CFG1_CASLAT_SHIFT 16 869 #define TIMING_CFG1_REFREC 0x0000F000 870 #define TIMING_CFG1_REFREC_SHIFT 12 871 #define TIMING_CFG1_WRREC 0x00000700 872 #define TIMING_CFG1_WRREC_SHIFT 8 873 #define TIMING_CFG1_ACTTOACT 0x00000070 874 #define TIMING_CFG1_ACTTOACT_SHIFT 4 875 #define TIMING_CFG1_WRTORD 0x00000007 876 #define TIMING_CFG1_WRTORD_SHIFT 0 877 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 878 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 879 #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 2.5 */ 880 881 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 882 */ 883 #define TIMING_CFG2_CPO 0x0F800000 884 #define TIMING_CFG2_CPO_SHIFT 23 885 #define TIMING_CFG2_ACSM 0x00080000 886 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 887 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 888 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 889 890 #define TIMING_CFG2_ADD_LAT 0x70000000 891 #define TIMING_CFG2_ADD_LAT_SHIFT 28 892 #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 893 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 894 #define TIMING_CFG2_RD_TO_PRE 0x0000E000 895 #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 896 #define TIMING_CFG2_CKE_PLS 0x000001C0 897 #define TIMING_CFG2_CKE_PLS_SHIFT 6 898 #define TIMING_CFG2_FOUR_ACT 0x0000003F 899 #define TIMING_CFG2_FOUR_ACT_SHIFT 0 900 901 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 902 */ 903 #define SDRAM_CFG_MEM_EN 0x80000000 904 #define SDRAM_CFG_SREN 0x40000000 905 #define SDRAM_CFG_ECC_EN 0x20000000 906 #define SDRAM_CFG_RD_EN 0x10000000 907 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 908 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 909 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 910 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 911 #define SDRAM_CFG_DYN_PWR 0x00200000 912 #define SDRAM_CFG_32_BE 0x00080000 913 #define SDRAM_CFG_8_BE 0x00040000 914 #define SDRAM_CFG_NCAP 0x00020000 915 #define SDRAM_CFG_2T_EN 0x00008000 916 #define SDRAM_CFG_BI 0x00000001 917 918 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 919 */ 920 #define SDRAM_MODE_ESD 0xFFFF0000 921 #define SDRAM_MODE_ESD_SHIFT 16 922 #define SDRAM_MODE_SD 0x0000FFFF 923 #define SDRAM_MODE_SD_SHIFT 0 924 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 925 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 926 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 927 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 928 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 929 #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 930 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 931 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 932 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 933 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 934 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 935 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 936 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 937 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 938 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 939 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 940 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 941 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 942 #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 943 944 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 945 */ 946 #define SDRAM_INTERVAL_REFINT 0x3FFF0000 947 #define SDRAM_INTERVAL_REFINT_SHIFT 16 948 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 949 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 950 951 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 952 */ 953 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 954 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 955 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 956 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 957 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 958 959 /* ECC_ERR_INJECT - Memory data path error injection mask ECC 960 */ 961 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 962 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 963 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 964 #define ECC_ERR_INJECT_EEIM_SHIFT 0 965 966 /* CAPTURE_ECC - Memory data path read capture ECC 967 */ 968 #define CAPTURE_ECC_ECE (0xff000000>>24) 969 #define CAPTURE_ECC_ECE_SHIFT 0 970 971 /* ERR_DETECT - Memory error detect 972 */ 973 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 974 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 975 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 976 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 977 978 /* ERR_DISABLE - Memory error disable 979 */ 980 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 981 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 982 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 983 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 984 ECC_ERROR_DISABLE_MBED) 985 /* ERR_INT_EN - Memory error interrupt enable 986 */ 987 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 988 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 989 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 990 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 991 ECC_ERR_INT_EN_MSEE) 992 /* CAPTURE_ATTRIBUTES - Memory error attributes capture 993 */ 994 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 995 #define ECC_CAPT_ATTR_BNUM_SHIFT 28 996 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 997 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 998 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 999 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1000 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1001 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 1002 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 1003 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1004 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1005 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1006 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1007 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1008 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1009 #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1010 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1011 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1012 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1013 #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1014 #define ECC_CAPT_ATTR_TSRC_SHIFT 16 1015 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 1016 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1017 #define ECC_CAPT_ATTR_TTYP_READ 0x2 1018 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1019 #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1020 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 1021 1022 /* ERR_SBE - Single bit ECC memory error management 1023 */ 1024 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 1025 #define ECC_ERROR_MAN_SBET_SHIFT 16 1026 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 1027 #define ECC_ERROR_MAN_SBEC_SHIFT 0 1028 1029 /* DMAMR - DMA Mode Register 1030 */ 1031 #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 1032 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 1033 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 1034 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 1035 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 1036 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 1037 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 1038 #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 1039 1040 /* DMASR - DMA Status Register 1041 */ 1042 #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 1043 #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 1044 1045 /* CONFIG_ADDRESS - PCI Config Address Register 1046 */ 1047 #define PCI_CONFIG_ADDRESS_EN 0x80000000 1048 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1049 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1050 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1051 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1052 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1053 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1054 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1055 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1056 1057 /* POTAR - PCI Outbound Translation Address Register 1058 */ 1059 #define POTAR_TA_MASK 0x000fffff 1060 1061 /* POBAR - PCI Outbound Base Address Register 1062 */ 1063 #define POBAR_BA_MASK 0x000fffff 1064 1065 /* POCMR - PCI Outbound Comparision Mask Register 1066 */ 1067 #define POCMR_EN 0x80000000 1068 #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1069 #define POCMR_SE 0x20000000 /* streaming enable */ 1070 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1071 #define POCMR_CM_MASK 0x000fffff 1072 #define POCMR_CM_4G 0x00000000 1073 #define POCMR_CM_2G 0x00080000 1074 #define POCMR_CM_1G 0x000C0000 1075 #define POCMR_CM_512M 0x000E0000 1076 #define POCMR_CM_256M 0x000F0000 1077 #define POCMR_CM_128M 0x000F8000 1078 #define POCMR_CM_64M 0x000FC000 1079 #define POCMR_CM_32M 0x000FE000 1080 #define POCMR_CM_16M 0x000FF000 1081 #define POCMR_CM_8M 0x000FF800 1082 #define POCMR_CM_4M 0x000FFC00 1083 #define POCMR_CM_2M 0x000FFE00 1084 #define POCMR_CM_1M 0x000FFF00 1085 #define POCMR_CM_512K 0x000FFF80 1086 #define POCMR_CM_256K 0x000FFFC0 1087 #define POCMR_CM_128K 0x000FFFE0 1088 #define POCMR_CM_64K 0x000FFFF0 1089 #define POCMR_CM_32K 0x000FFFF8 1090 #define POCMR_CM_16K 0x000FFFFC 1091 #define POCMR_CM_8K 0x000FFFFE 1092 #define POCMR_CM_4K 0x000FFFFF 1093 1094 /* PITAR - PCI Inbound Translation Address Register 1095 */ 1096 #define PITAR_TA_MASK 0x000fffff 1097 1098 /* PIBAR - PCI Inbound Base/Extended Address Register 1099 */ 1100 #define PIBAR_MASK 0xffffffff 1101 #define PIEBAR_EBA_MASK 0x000fffff 1102 1103 /* PIWAR - PCI Inbound Windows Attributes Register 1104 */ 1105 #define PIWAR_EN 0x80000000 1106 #define PIWAR_PF 0x20000000 1107 #define PIWAR_RTT_MASK 0x000f0000 1108 #define PIWAR_RTT_NO_SNOOP 0x00040000 1109 #define PIWAR_RTT_SNOOP 0x00050000 1110 #define PIWAR_WTT_MASK 0x0000f000 1111 #define PIWAR_WTT_NO_SNOOP 0x00004000 1112 #define PIWAR_WTT_SNOOP 0x00005000 1113 #define PIWAR_IWS_MASK 0x0000003F 1114 #define PIWAR_IWS_4K 0x0000000B 1115 #define PIWAR_IWS_8K 0x0000000C 1116 #define PIWAR_IWS_16K 0x0000000D 1117 #define PIWAR_IWS_32K 0x0000000E 1118 #define PIWAR_IWS_64K 0x0000000F 1119 #define PIWAR_IWS_128K 0x00000010 1120 #define PIWAR_IWS_256K 0x00000011 1121 #define PIWAR_IWS_512K 0x00000012 1122 #define PIWAR_IWS_1M 0x00000013 1123 #define PIWAR_IWS_2M 0x00000014 1124 #define PIWAR_IWS_4M 0x00000015 1125 #define PIWAR_IWS_8M 0x00000016 1126 #define PIWAR_IWS_16M 0x00000017 1127 #define PIWAR_IWS_32M 0x00000018 1128 #define PIWAR_IWS_64M 0x00000019 1129 #define PIWAR_IWS_128M 0x0000001A 1130 #define PIWAR_IWS_256M 0x0000001B 1131 #define PIWAR_IWS_512M 0x0000001C 1132 #define PIWAR_IWS_1G 0x0000001D 1133 #define PIWAR_IWS_2G 0x0000001E 1134 1135 /* PMCCR1 - PCI Configuration Register 1 1136 */ 1137 #define PMCCR1_POWER_OFF 0x00000020 1138 1139 /* FMR - Flash Mode Register 1140 */ 1141 #define FMR_CWTO 0x0000F000 1142 #define FMR_CWTO_SHIFT 12 1143 #define FMR_BOOT 0x00000800 1144 #define FMR_ECCM 0x00000100 1145 #define FMR_AL 0x00000030 1146 #define FMR_AL_SHIFT 4 1147 #define FMR_OP 0x00000003 1148 #define FMR_OP_SHIFT 0 1149 1150 /* FIR - Flash Instruction Register 1151 */ 1152 #define FIR_OP0 0xF0000000 1153 #define FIR_OP0_SHIFT 28 1154 #define FIR_OP1 0x0F000000 1155 #define FIR_OP1_SHIFT 24 1156 #define FIR_OP2 0x00F00000 1157 #define FIR_OP2_SHIFT 20 1158 #define FIR_OP3 0x000F0000 1159 #define FIR_OP3_SHIFT 16 1160 #define FIR_OP4 0x0000F000 1161 #define FIR_OP4_SHIFT 12 1162 #define FIR_OP5 0x00000F00 1163 #define FIR_OP5_SHIFT 8 1164 #define FIR_OP6 0x000000F0 1165 #define FIR_OP6_SHIFT 4 1166 #define FIR_OP7 0x0000000F 1167 #define FIR_OP7_SHIFT 0 1168 #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 1169 #define FIR_OP_CA 0x1 /* Issue current column address */ 1170 #define FIR_OP_PA 0x2 /* Issue current block+page address */ 1171 #define FIR_OP_UA 0x3 /* Issue user defined address */ 1172 #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 1173 #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 1174 #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 1175 #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 1176 #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 1177 #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 1178 #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 1179 #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 1180 #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 1181 #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 1182 #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 1183 #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 1184 1185 /* FCR - Flash Command Register 1186 */ 1187 #define FCR_CMD0 0xFF000000 1188 #define FCR_CMD0_SHIFT 24 1189 #define FCR_CMD1 0x00FF0000 1190 #define FCR_CMD1_SHIFT 16 1191 #define FCR_CMD2 0x0000FF00 1192 #define FCR_CMD2_SHIFT 8 1193 #define FCR_CMD3 0x000000FF 1194 #define FCR_CMD3_SHIFT 0 1195 1196 /* FBAR - Flash Block Address Register 1197 */ 1198 #define FBAR_BLK 0x00FFFFFF 1199 1200 /* FPAR - Flash Page Address Register 1201 */ 1202 #define FPAR_SP_PI 0x00007C00 1203 #define FPAR_SP_PI_SHIFT 10 1204 #define FPAR_SP_MS 0x00000200 1205 #define FPAR_SP_CI 0x000001FF 1206 #define FPAR_SP_CI_SHIFT 0 1207 #define FPAR_LP_PI 0x0003F000 1208 #define FPAR_LP_PI_SHIFT 12 1209 #define FPAR_LP_MS 0x00000800 1210 #define FPAR_LP_CI 0x000007FF 1211 #define FPAR_LP_CI_SHIFT 0 1212 1213 /* LTESR - Transfer Error Status Register 1214 */ 1215 #define LTESR_BM 0x80000000 1216 #define LTESR_FCT 0x40000000 1217 #define LTESR_PAR 0x20000000 1218 #define LTESR_WP 0x04000000 1219 #define LTESR_ATMW 0x00800000 1220 #define LTESR_ATMR 0x00400000 1221 #define LTESR_CS 0x00080000 1222 #define LTESR_CC 0x00000001 1223 1224 /* DDRCDR - DDR Control Driver Register 1225 */ 1226 #define DDRCDR_DHC_EN 0x80000000 1227 #define DDRCDR_EN 0x40000000 1228 #define DDRCDR_PZ 0x3C000000 1229 #define DDRCDR_PZ_MAXZ 0x00000000 1230 #define DDRCDR_PZ_HIZ 0x20000000 1231 #define DDRCDR_PZ_NOMZ 0x30000000 1232 #define DDRCDR_PZ_LOZ 0x38000000 1233 #define DDRCDR_PZ_MINZ 0x3C000000 1234 #define DDRCDR_NZ 0x3C000000 1235 #define DDRCDR_NZ_MAXZ 0x00000000 1236 #define DDRCDR_NZ_HIZ 0x02000000 1237 #define DDRCDR_NZ_NOMZ 0x03000000 1238 #define DDRCDR_NZ_LOZ 0x03800000 1239 #define DDRCDR_NZ_MINZ 0x03C00000 1240 #define DDRCDR_ODT 0x00080000 1241 #define DDRCDR_DDR_CFG 0x00040000 1242 #define DDRCDR_M_ODR 0x00000002 1243 #define DDRCDR_Q_DRN 0x00000001 1244 1245 #ifndef __ASSEMBLY__ 1246 struct pci_region; 1247 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 1248 #endif 1249 1250 #endif /* __MPC83XX_H__ */ 1251