1 /* 2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #ifndef __MPC83XX_H__ 14 #define __MPC83XX_H__ 15 16 #include <config.h> 17 #include <asm/fsl_lbc.h> 18 #if defined(CONFIG_E300) 19 #include <asm/e300.h> 20 #endif 21 22 /* MPC83xx cpu provide RCR register to do reset thing specially 23 */ 24 #define MPC83xx_RESET 25 26 /* System reset offset (PowerPC standard) 27 */ 28 #define EXC_OFF_SYS_RESET 0x0100 29 #define _START_OFFSET EXC_OFF_SYS_RESET 30 31 /* IMMRBAR - Internal Memory Register Base Address 32 */ 33 #ifndef CONFIG_DEFAULT_IMMR 34 #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 35 #endif 36 #define IMMRBAR 0x0000 /* Register offset to immr */ 37 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 38 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 39 40 /* LAWBAR - Local Access Window Base Address Register 41 */ 42 #define LBLAWBAR0 0x0020 /* Register offset to immr */ 43 #define LBLAWAR0 0x0024 44 #define LBLAWBAR1 0x0028 45 #define LBLAWAR1 0x002C 46 #define LBLAWBAR2 0x0030 47 #define LBLAWAR2 0x0034 48 #define LBLAWBAR3 0x0038 49 #define LBLAWAR3 0x003C 50 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 51 52 /* SPRIDR - System Part and Revision ID Register 53 */ 54 #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ 55 #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ 56 57 #if defined(CONFIG_MPC834x) 58 #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) 59 #define REVID_MINOR(spridr) (spridr & 0x000000FF) 60 #else 61 #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) 62 #define REVID_MINOR(spridr) (spridr & 0x0000000F) 63 #endif 64 65 #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) 66 #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) 67 68 #define SPR_831X_FAMILY 0x80B 69 #define SPR_8311 0x80B2 70 #define SPR_8313 0x80B0 71 #define SPR_8314 0x80B6 72 #define SPR_8315 0x80B4 73 #define SPR_832X_FAMILY 0x806 74 #define SPR_8321 0x8066 75 #define SPR_8323 0x8062 76 #define SPR_834X_FAMILY 0x803 77 #define SPR_8343 0x8036 78 #define SPR_8347_TBGA_ 0x8032 79 #define SPR_8347_PBGA_ 0x8034 80 #define SPR_8349 0x8030 81 #define SPR_836X_FAMILY 0x804 82 #define SPR_8358_TBGA_ 0x804A 83 #define SPR_8358_PBGA_ 0x804E 84 #define SPR_8360 0x8048 85 #define SPR_837X_FAMILY 0x80C 86 #define SPR_8377 0x80C6 87 #define SPR_8378 0x80C4 88 #define SPR_8379 0x80C2 89 90 /* SPCR - System Priority Configuration Register 91 */ 92 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 93 #define SPCR_PCIHPE_SHIFT (31-3) 94 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 95 #define SPCR_PCIPR_SHIFT (31-7) 96 #define SPCR_OPT 0x00800000 /* Optimize */ 97 #define SPCR_OPT_SHIFT (31-8) 98 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 99 #define SPCR_TBEN_SHIFT (31-9) 100 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 101 #define SPCR_COREPR_SHIFT (31-11) 102 103 #if defined(CONFIG_MPC834x) 104 /* SPCR bits - MPC8349 specific */ 105 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 106 #define SPCR_TSEC1DP_SHIFT (31-19) 107 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 108 #define SPCR_TSEC1BDP_SHIFT (31-21) 109 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 110 #define SPCR_TSEC1EP_SHIFT (31-23) 111 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 112 #define SPCR_TSEC2DP_SHIFT (31-27) 113 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 114 #define SPCR_TSEC2BDP_SHIFT (31-29) 115 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 116 #define SPCR_TSEC2EP_SHIFT (31-31) 117 118 #elif defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) 119 /* SPCR bits - MPC831x and MPC837x specific */ 120 #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 121 #define SPCR_TSECDP_SHIFT (31-19) 122 #define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */ 123 #define SPCR_TSECBDP_SHIFT (31-21) 124 #define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */ 125 #define SPCR_TSECEP_SHIFT (31-23) 126 #endif 127 128 /* SICRL/H - System I/O Configuration Register Low/High 129 */ 130 #if defined(CONFIG_MPC834x) 131 /* SICRL bits - MPC8349 specific */ 132 #define SICRL_LDP_A 0x80000000 133 #define SICRL_USB1 0x40000000 134 #define SICRL_USB0 0x20000000 135 #define SICRL_UART 0x0C000000 136 #define SICRL_GPIO1_A 0x02000000 137 #define SICRL_GPIO1_B 0x01000000 138 #define SICRL_GPIO1_C 0x00800000 139 #define SICRL_GPIO1_D 0x00400000 140 #define SICRL_GPIO1_E 0x00200000 141 #define SICRL_GPIO1_F 0x00180000 142 #define SICRL_GPIO1_G 0x00040000 143 #define SICRL_GPIO1_H 0x00020000 144 #define SICRL_GPIO1_I 0x00010000 145 #define SICRL_GPIO1_J 0x00008000 146 #define SICRL_GPIO1_K 0x00004000 147 #define SICRL_GPIO1_L 0x00003000 148 149 /* SICRH bits - MPC8349 specific */ 150 #define SICRH_DDR 0x80000000 151 #define SICRH_TSEC1_A 0x10000000 152 #define SICRH_TSEC1_B 0x08000000 153 #define SICRH_TSEC1_C 0x04000000 154 #define SICRH_TSEC1_D 0x02000000 155 #define SICRH_TSEC1_E 0x01000000 156 #define SICRH_TSEC1_F 0x00800000 157 #define SICRH_TSEC2_A 0x00400000 158 #define SICRH_TSEC2_B 0x00200000 159 #define SICRH_TSEC2_C 0x00100000 160 #define SICRH_TSEC2_D 0x00080000 161 #define SICRH_TSEC2_E 0x00040000 162 #define SICRH_TSEC2_F 0x00020000 163 #define SICRH_TSEC2_G 0x00010000 164 #define SICRH_TSEC2_H 0x00008000 165 #define SICRH_GPIO2_A 0x00004000 166 #define SICRH_GPIO2_B 0x00002000 167 #define SICRH_GPIO2_C 0x00001000 168 #define SICRH_GPIO2_D 0x00000800 169 #define SICRH_GPIO2_E 0x00000400 170 #define SICRH_GPIO2_F 0x00000200 171 #define SICRH_GPIO2_G 0x00000180 172 #define SICRH_GPIO2_H 0x00000060 173 #define SICRH_TSOBI1 0x00000002 174 #define SICRH_TSOBI2 0x00000001 175 176 #elif defined(CONFIG_MPC8360) 177 /* SICRL bits - MPC8360 specific */ 178 #define SICRL_LDP_A 0xC0000000 179 #define SICRL_LCLK_1 0x10000000 180 #define SICRL_LCLK_2 0x08000000 181 #define SICRL_SRCID_A 0x03000000 182 #define SICRL_IRQ_CKSTP_A 0x00C00000 183 184 /* SICRH bits - MPC8360 specific */ 185 #define SICRH_DDR 0x80000000 186 #define SICRH_SECONDARY_DDR 0x40000000 187 #define SICRH_SDDROE 0x20000000 188 #define SICRH_IRQ3 0x10000000 189 #define SICRH_UC1EOBI 0x00000004 190 #define SICRH_UC2E1OBI 0x00000002 191 #define SICRH_UC2E2OBI 0x00000001 192 193 #elif defined(CONFIG_MPC832x) 194 /* SICRL bits - MPC832x specific */ 195 #define SICRL_LDP_LCS_A 0x80000000 196 #define SICRL_IRQ_CKS 0x20000000 197 #define SICRL_PCI_MSRC 0x10000000 198 #define SICRL_URT_CTPR 0x06000000 199 #define SICRL_IRQ_CTPR 0x00C00000 200 201 #elif defined(CONFIG_MPC8313) 202 /* SICRL bits - MPC8313 specific */ 203 #define SICRL_LBC 0x30000000 204 #define SICRL_UART 0x0C000000 205 #define SICRL_SPI_A 0x03000000 206 #define SICRL_SPI_B 0x00C00000 207 #define SICRL_SPI_C 0x00300000 208 #define SICRL_SPI_D 0x000C0000 209 #define SICRL_USBDR_11 0x00000C00 210 #define SICRL_USBDR_10 0x00000800 211 #define SICRL_USBDR_01 0x00000400 212 #define SICRL_USBDR_00 0x00000000 213 #define SICRL_ETSEC1_A 0x0000000C 214 #define SICRL_ETSEC2_A 0x00000003 215 216 /* SICRH bits - MPC8313 specific */ 217 #define SICRH_INTR_A 0x02000000 218 #define SICRH_INTR_B 0x00C00000 219 #define SICRH_IIC 0x00300000 220 #define SICRH_ETSEC2_B 0x000C0000 221 #define SICRH_ETSEC2_C 0x00030000 222 #define SICRH_ETSEC2_D 0x0000C000 223 #define SICRH_ETSEC2_E 0x00003000 224 #define SICRH_ETSEC2_F 0x00000C00 225 #define SICRH_ETSEC2_G 0x00000300 226 #define SICRH_ETSEC1_B 0x00000080 227 #define SICRH_ETSEC1_C 0x00000060 228 #define SICRH_GTX1_DLY 0x00000008 229 #define SICRH_GTX2_DLY 0x00000004 230 #define SICRH_TSOBI1 0x00000002 231 #define SICRH_TSOBI2 0x00000001 232 233 #elif defined(CONFIG_MPC8315) 234 /* SICRL bits - MPC8315 specific */ 235 #define SICRL_DMA_CH0 0xc0000000 236 #define SICRL_DMA_SPI 0x30000000 237 #define SICRL_UART 0x0c000000 238 #define SICRL_IRQ4 0x02000000 239 #define SICRL_IRQ5 0x01800000 240 #define SICRL_IRQ6_7 0x00400000 241 #define SICRL_IIC1 0x00300000 242 #define SICRL_TDM 0x000c0000 243 #define SICRL_TDM_SHARED 0x00030000 244 #define SICRL_PCI_A 0x0000c000 245 #define SICRL_ELBC_A 0x00003000 246 #define SICRL_ETSEC1_A 0x000000c0 247 #define SICRL_ETSEC1_B 0x00000030 248 #define SICRL_ETSEC1_C 0x0000000c 249 #define SICRL_TSEXPOBI 0x00000001 250 251 /* SICRH bits - MPC8315 specific */ 252 #define SICRH_GPIO_0 0xc0000000 253 #define SICRH_GPIO_1 0x30000000 254 #define SICRH_GPIO_2 0x0c000000 255 #define SICRH_GPIO_3 0x03000000 256 #define SICRH_GPIO_4 0x00c00000 257 #define SICRH_GPIO_5 0x00300000 258 #define SICRH_GPIO_6 0x000c0000 259 #define SICRH_GPIO_7 0x00030000 260 #define SICRH_GPIO_8 0x0000c000 261 #define SICRH_GPIO_9 0x00003000 262 #define SICRH_GPIO_10 0x00000c00 263 #define SICRH_GPIO_11 0x00000300 264 #define SICRH_ETSEC2_A 0x000000c0 265 #define SICRH_TSOBI1 0x00000002 266 #define SICRH_TSOBI2 0x00000001 267 268 #elif defined(CONFIG_MPC837x) 269 /* SICRL bits - MPC837x specific */ 270 #define SICRL_USB_A 0xC0000000 271 #define SICRL_USB_B 0x30000000 272 #define SICRL_USB_B_SD 0x20000000 273 #define SICRL_UART 0x0C000000 274 #define SICRL_GPIO_A 0x02000000 275 #define SICRL_GPIO_B 0x01000000 276 #define SICRL_GPIO_C 0x00800000 277 #define SICRL_GPIO_D 0x00400000 278 #define SICRL_GPIO_E 0x00200000 279 #define SICRL_GPIO_F 0x00180000 280 #define SICRL_GPIO_G 0x00040000 281 #define SICRL_GPIO_H 0x00020000 282 #define SICRL_GPIO_I 0x00010000 283 #define SICRL_GPIO_J 0x00008000 284 #define SICRL_GPIO_K 0x00004000 285 #define SICRL_GPIO_L 0x00003000 286 #define SICRL_DMA_A 0x00000800 287 #define SICRL_DMA_B 0x00000400 288 #define SICRL_DMA_C 0x00000200 289 #define SICRL_DMA_D 0x00000100 290 #define SICRL_DMA_E 0x00000080 291 #define SICRL_DMA_F 0x00000040 292 #define SICRL_DMA_G 0x00000020 293 #define SICRL_DMA_H 0x00000010 294 #define SICRL_DMA_I 0x00000008 295 #define SICRL_DMA_J 0x00000004 296 #define SICRL_LDP_A 0x00000002 297 #define SICRL_LDP_B 0x00000001 298 299 /* SICRH bits - MPC837x specific */ 300 #define SICRH_DDR 0x80000000 301 #define SICRH_TSEC1_A 0x10000000 302 #define SICRH_TSEC1_B 0x08000000 303 #define SICRH_TSEC2_A 0x00400000 304 #define SICRH_TSEC2_B 0x00200000 305 #define SICRH_TSEC2_C 0x00100000 306 #define SICRH_TSEC2_D 0x00080000 307 #define SICRH_TSEC2_E 0x00040000 308 #define SICRH_TMR 0x00010000 309 #define SICRH_GPIO2_A 0x00008000 310 #define SICRH_GPIO2_B 0x00004000 311 #define SICRH_GPIO2_C 0x00002000 312 #define SICRH_GPIO2_D 0x00001000 313 #define SICRH_GPIO2_E 0x00000C00 314 #define SICRH_GPIO2_E_SD 0x00000800 315 #define SICRH_GPIO2_F 0x00000300 316 #define SICRH_GPIO2_G 0x000000C0 317 #define SICRH_GPIO2_H 0x00000030 318 #define SICRH_SPI 0x00000003 319 #define SICRH_SPI_SD 0x00000001 320 #endif 321 322 /* SWCRR - System Watchdog Control Register 323 */ 324 #define SWCRR 0x0204 /* Register offset to immr */ 325 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 326 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 327 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 328 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 329 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 330 331 /* SWCNR - System Watchdog Counter Register 332 */ 333 #define SWCNR 0x0208 /* Register offset to immr */ 334 #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 335 #define SWCNR_RES ~(SWCNR_SWCN) 336 337 /* SWSRR - System Watchdog Service Register 338 */ 339 #define SWSRR 0x020E /* Register offset to immr */ 340 341 /* ACR - Arbiter Configuration Register 342 */ 343 #define ACR_COREDIS 0x10000000 /* Core disable */ 344 #define ACR_COREDIS_SHIFT (31-7) 345 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 346 #define ACR_PIPE_DEP_SHIFT (31-15) 347 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 348 #define ACR_PCI_RPTCNT_SHIFT (31-19) 349 #define ACR_RPTCNT 0x00000700 /* Repeat count */ 350 #define ACR_RPTCNT_SHIFT (31-23) 351 #define ACR_APARK 0x00000030 /* Address parking */ 352 #define ACR_APARK_SHIFT (31-27) 353 #define ACR_PARKM 0x0000000F /* Parking master */ 354 #define ACR_PARKM_SHIFT (31-31) 355 356 /* ATR - Arbiter Timers Register 357 */ 358 #define ATR_DTO 0x00FF0000 /* Data time out */ 359 #define ATR_DTO_SHIFT 16 360 #define ATR_ATO 0x000000FF /* Address time out */ 361 #define ATR_ATO_SHIFT 0 362 363 /* AER - Arbiter Event Register 364 */ 365 #define AER_ETEA 0x00000020 /* Transfer error */ 366 #define AER_RES 0x00000010 /* Reserved transfer type */ 367 #define AER_ECW 0x00000008 /* External control word transfer type */ 368 #define AER_AO 0x00000004 /* Address Only transfer type */ 369 #define AER_DTO 0x00000002 /* Data time out */ 370 #define AER_ATO 0x00000001 /* Address time out */ 371 372 /* AEATR - Arbiter Event Address Register 373 */ 374 #define AEATR_EVENT 0x07000000 /* Event type */ 375 #define AEATR_EVENT_SHIFT 24 376 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 377 #define AEATR_MSTR_ID_SHIFT 16 378 #define AEATR_TBST 0x00000800 /* Transfer burst */ 379 #define AEATR_TBST_SHIFT 11 380 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 381 #define AEATR_TSIZE_SHIFT 8 382 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 383 #define AEATR_TTYPE_SHIFT 0 384 385 /* HRCWL - Hard Reset Configuration Word Low 386 */ 387 #define HRCWL_LBIUCM 0x80000000 388 #define HRCWL_LBIUCM_SHIFT 31 389 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 390 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 391 392 #define HRCWL_DDRCM 0x40000000 393 #define HRCWL_DDRCM_SHIFT 30 394 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 395 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 396 397 #define HRCWL_SPMF 0x0f000000 398 #define HRCWL_SPMF_SHIFT 24 399 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 400 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 401 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 402 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 403 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 404 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 405 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 406 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 407 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 408 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 409 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 410 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 411 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 412 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 413 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 414 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 415 416 #define HRCWL_VCO_BYPASS 0x00000000 417 #define HRCWL_VCO_1X2 0x00000000 418 #define HRCWL_VCO_1X4 0x00200000 419 #define HRCWL_VCO_1X8 0x00400000 420 421 #define HRCWL_COREPLL 0x007F0000 422 #define HRCWL_COREPLL_SHIFT 16 423 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 424 #define HRCWL_CORE_TO_CSB_1X1 0x00020000 425 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 426 #define HRCWL_CORE_TO_CSB_2X1 0x00040000 427 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 428 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 429 430 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 431 #define HRCWL_CEVCOD 0x000000C0 432 #define HRCWL_CEVCOD_SHIFT 6 433 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 434 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 435 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 436 437 #define HRCWL_CEPDF 0x00000020 438 #define HRCWL_CEPDF_SHIFT 5 439 #define HRCWL_CE_PLL_DIV_1X1 0x00000000 440 #define HRCWL_CE_PLL_DIV_2X1 0x00000020 441 442 #define HRCWL_CEPMF 0x0000001F 443 #define HRCWL_CEPMF_SHIFT 0 444 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 445 #define HRCWL_CE_TO_PLL_1X2 0x00000002 446 #define HRCWL_CE_TO_PLL_1X3 0x00000003 447 #define HRCWL_CE_TO_PLL_1X4 0x00000004 448 #define HRCWL_CE_TO_PLL_1X5 0x00000005 449 #define HRCWL_CE_TO_PLL_1X6 0x00000006 450 #define HRCWL_CE_TO_PLL_1X7 0x00000007 451 #define HRCWL_CE_TO_PLL_1X8 0x00000008 452 #define HRCWL_CE_TO_PLL_1X9 0x00000009 453 #define HRCWL_CE_TO_PLL_1X10 0x0000000A 454 #define HRCWL_CE_TO_PLL_1X11 0x0000000B 455 #define HRCWL_CE_TO_PLL_1X12 0x0000000C 456 #define HRCWL_CE_TO_PLL_1X13 0x0000000D 457 #define HRCWL_CE_TO_PLL_1X14 0x0000000E 458 #define HRCWL_CE_TO_PLL_1X15 0x0000000F 459 #define HRCWL_CE_TO_PLL_1X16 0x00000010 460 #define HRCWL_CE_TO_PLL_1X17 0x00000011 461 #define HRCWL_CE_TO_PLL_1X18 0x00000012 462 #define HRCWL_CE_TO_PLL_1X19 0x00000013 463 #define HRCWL_CE_TO_PLL_1X20 0x00000014 464 #define HRCWL_CE_TO_PLL_1X21 0x00000015 465 #define HRCWL_CE_TO_PLL_1X22 0x00000016 466 #define HRCWL_CE_TO_PLL_1X23 0x00000017 467 #define HRCWL_CE_TO_PLL_1X24 0x00000018 468 #define HRCWL_CE_TO_PLL_1X25 0x00000019 469 #define HRCWL_CE_TO_PLL_1X26 0x0000001A 470 #define HRCWL_CE_TO_PLL_1X27 0x0000001B 471 #define HRCWL_CE_TO_PLL_1X28 0x0000001C 472 #define HRCWL_CE_TO_PLL_1X29 0x0000001D 473 #define HRCWL_CE_TO_PLL_1X30 0x0000001E 474 #define HRCWL_CE_TO_PLL_1X31 0x0000001F 475 476 #elif defined(CONFIG_MPC8315) 477 #define HRCWL_SVCOD 0x30000000 478 #define HRCWL_SVCOD_SHIFT 28 479 #define HRCWL_SVCOD_DIV_2 0x00000000 480 #define HRCWL_SVCOD_DIV_4 0x10000000 481 #define HRCWL_SVCOD_DIV_8 0x20000000 482 #define HRCWL_SVCOD_DIV_1 0x30000000 483 484 #elif defined(CONFIG_MPC837x) 485 #define HRCWL_SVCOD 0x30000000 486 #define HRCWL_SVCOD_SHIFT 28 487 #define HRCWL_SVCOD_DIV_4 0x00000000 488 #define HRCWL_SVCOD_DIV_8 0x10000000 489 #define HRCWL_SVCOD_DIV_2 0x20000000 490 #define HRCWL_SVCOD_DIV_1 0x30000000 491 #endif 492 493 /* HRCWH - Hardware Reset Configuration Word High 494 */ 495 #define HRCWH_PCI_HOST 0x80000000 496 #define HRCWH_PCI_HOST_SHIFT 31 497 #define HRCWH_PCI_AGENT 0x00000000 498 499 #if defined(CONFIG_MPC834x) 500 #define HRCWH_32_BIT_PCI 0x00000000 501 #define HRCWH_64_BIT_PCI 0x40000000 502 #endif 503 504 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 505 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 506 507 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 508 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 509 510 #if defined(CONFIG_MPC834x) 511 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 512 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 513 514 #elif defined(CONFIG_MPC8360) 515 #define HRCWH_PCICKDRV_DISABLE 0x00000000 516 #define HRCWH_PCICKDRV_ENABLE 0x10000000 517 #endif 518 519 #define HRCWH_CORE_DISABLE 0x08000000 520 #define HRCWH_CORE_ENABLE 0x00000000 521 522 #define HRCWH_FROM_0X00000100 0x00000000 523 #define HRCWH_FROM_0XFFF00100 0x04000000 524 525 #define HRCWH_BOOTSEQ_DISABLE 0x00000000 526 #define HRCWH_BOOTSEQ_NORMAL 0x01000000 527 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 528 529 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 530 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 531 532 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 533 #define HRCWH_ROM_LOC_PCI1 0x00100000 534 #if defined(CONFIG_MPC834x) 535 #define HRCWH_ROM_LOC_PCI2 0x00200000 536 #endif 537 #if defined(CONFIG_MPC837x) 538 #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 539 #endif 540 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 541 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 542 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 543 544 #if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) 545 #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 546 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 547 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 548 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 549 550 #define HRCWH_RL_EXT_LEGACY 0x00000000 551 #define HRCWH_RL_EXT_NAND 0x00040000 552 553 #define HRCWH_TSEC1M_MASK 0x0000E000 554 #define HRCWH_TSEC1M_IN_MII 0x00000000 555 #define HRCWH_TSEC1M_IN_RMII 0x00002000 556 #define HRCWH_TSEC1M_IN_RGMII 0x00006000 557 #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 558 #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 559 560 #define HRCWH_TSEC2M_MASK 0x00001C00 561 #define HRCWH_TSEC2M_IN_MII 0x00000000 562 #define HRCWH_TSEC2M_IN_RMII 0x00000400 563 #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 564 #define HRCWH_TSEC2M_IN_RTBI 0x00001400 565 #define HRCWH_TSEC2M_IN_SGMII 0x00001800 566 #endif 567 568 #if defined(CONFIG_MPC834x) 569 #define HRCWH_TSEC1M_IN_RGMII 0x00000000 570 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 571 #define HRCWH_TSEC1M_IN_GMII 0x00008000 572 #define HRCWH_TSEC1M_IN_TBI 0x0000C000 573 #define HRCWH_TSEC2M_IN_RGMII 0x00000000 574 #define HRCWH_TSEC2M_IN_RTBI 0x00001000 575 #define HRCWH_TSEC2M_IN_GMII 0x00002000 576 #define HRCWH_TSEC2M_IN_TBI 0x00003000 577 #endif 578 579 #if defined(CONFIG_MPC8360) 580 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 581 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 582 #endif 583 584 #define HRCWH_BIG_ENDIAN 0x00000000 585 #define HRCWH_LITTLE_ENDIAN 0x00000008 586 587 #define HRCWH_LALE_NORMAL 0x00000000 588 #define HRCWH_LALE_EARLY 0x00000004 589 590 #define HRCWH_LDP_SET 0x00000000 591 #define HRCWH_LDP_CLEAR 0x00000002 592 593 /* RSR - Reset Status Register 594 */ 595 #if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x) 596 #define RSR_RSTSRC 0xF0000000 /* Reset source */ 597 #define RSR_RSTSRC_SHIFT 28 598 #else 599 #define RSR_RSTSRC 0xE0000000 /* Reset source */ 600 #define RSR_RSTSRC_SHIFT 29 601 #endif 602 #define RSR_BSF 0x00010000 /* Boot seq. fail */ 603 #define RSR_BSF_SHIFT 16 604 #define RSR_SWSR 0x00002000 /* software soft reset */ 605 #define RSR_SWSR_SHIFT 13 606 #define RSR_SWHR 0x00001000 /* software hard reset */ 607 #define RSR_SWHR_SHIFT 12 608 #define RSR_JHRS 0x00000200 /* jtag hreset */ 609 #define RSR_JHRS_SHIFT 9 610 #define RSR_JSRS 0x00000100 /* jtag sreset status */ 611 #define RSR_JSRS_SHIFT 8 612 #define RSR_CSHR 0x00000010 /* checkstop reset status */ 613 #define RSR_CSHR_SHIFT 4 614 #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 615 #define RSR_SWRS_SHIFT 3 616 #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 617 #define RSR_BMRS_SHIFT 2 618 #define RSR_SRS 0x00000002 /* soft reset status */ 619 #define RSR_SRS_SHIFT 1 620 #define RSR_HRS 0x00000001 /* hard reset status */ 621 #define RSR_HRS_SHIFT 0 622 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 623 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 624 RSR_BMRS | RSR_SRS | RSR_HRS) 625 /* RMR - Reset Mode Register 626 */ 627 #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 628 #define RMR_CSRE_SHIFT 0 629 #define RMR_RES ~(RMR_CSRE) 630 631 /* RCR - Reset Control Register 632 */ 633 #define RCR_SWHR 0x00000002 /* software hard reset */ 634 #define RCR_SWSR 0x00000001 /* software soft reset */ 635 #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 636 637 /* RCER - Reset Control Enable Register 638 */ 639 #define RCER_CRE 0x00000001 /* software hard reset */ 640 #define RCER_RES ~(RCER_CRE) 641 642 /* SPMR - System PLL Mode Register 643 */ 644 #define SPMR_LBIUCM 0x80000000 645 #define SPMR_DDRCM 0x40000000 646 #define SPMR_SPMF 0x0F000000 647 #define SPMR_CKID 0x00800000 648 #define SPMR_CKID_SHIFT 23 649 #define SPMR_COREPLL 0x007F0000 650 #define SPMR_CEVCOD 0x000000C0 651 #define SPMR_CEPDF 0x00000020 652 #define SPMR_CEPMF 0x0000001F 653 654 /* OCCR - Output Clock Control Register 655 */ 656 #define OCCR_PCICOE0 0x80000000 657 #define OCCR_PCICOE1 0x40000000 658 #define OCCR_PCICOE2 0x20000000 659 #define OCCR_PCICOE3 0x10000000 660 #define OCCR_PCICOE4 0x08000000 661 #define OCCR_PCICOE5 0x04000000 662 #define OCCR_PCICOE6 0x02000000 663 #define OCCR_PCICOE7 0x01000000 664 #define OCCR_PCICD0 0x00800000 665 #define OCCR_PCICD1 0x00400000 666 #define OCCR_PCICD2 0x00200000 667 #define OCCR_PCICD3 0x00100000 668 #define OCCR_PCICD4 0x00080000 669 #define OCCR_PCICD5 0x00040000 670 #define OCCR_PCICD6 0x00020000 671 #define OCCR_PCICD7 0x00010000 672 #define OCCR_PCI1CR 0x00000002 673 #define OCCR_PCI2CR 0x00000001 674 #define OCCR_PCICR OCCR_PCI1CR 675 676 /* SCCR - System Clock Control Register 677 */ 678 #define SCCR_ENCCM 0x03000000 679 #define SCCR_ENCCM_SHIFT 24 680 #define SCCR_ENCCM_0 0x00000000 681 #define SCCR_ENCCM_1 0x01000000 682 #define SCCR_ENCCM_2 0x02000000 683 #define SCCR_ENCCM_3 0x03000000 684 685 #define SCCR_PCICM 0x00010000 686 #define SCCR_PCICM_SHIFT 16 687 688 #if defined(CONFIG_MPC834x) 689 /* SCCR bits - MPC834x specific */ 690 #define SCCR_TSEC1CM 0xc0000000 691 #define SCCR_TSEC1CM_SHIFT 30 692 #define SCCR_TSEC1CM_0 0x00000000 693 #define SCCR_TSEC1CM_1 0x40000000 694 #define SCCR_TSEC1CM_2 0x80000000 695 #define SCCR_TSEC1CM_3 0xC0000000 696 697 #define SCCR_TSEC2CM 0x30000000 698 #define SCCR_TSEC2CM_SHIFT 28 699 #define SCCR_TSEC2CM_0 0x00000000 700 #define SCCR_TSEC2CM_1 0x10000000 701 #define SCCR_TSEC2CM_2 0x20000000 702 #define SCCR_TSEC2CM_3 0x30000000 703 704 /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 705 #define SCCR_USBMPHCM 0x00c00000 706 #define SCCR_USBMPHCM_SHIFT 22 707 #define SCCR_USBDRCM 0x00300000 708 #define SCCR_USBDRCM_SHIFT 20 709 #define SCCR_USBCM 0x00f00000 710 #define SCCR_USBCM_SHIFT 20 711 #define SCCR_USBCM_0 0x00000000 712 #define SCCR_USBCM_1 0x00500000 713 #define SCCR_USBCM_2 0x00A00000 714 #define SCCR_USBCM_3 0x00F00000 715 716 #elif defined(CONFIG_MPC8313) 717 /* TSEC1 bits are for TSEC2 as well */ 718 #define SCCR_TSEC1CM 0xc0000000 719 #define SCCR_TSEC1CM_SHIFT 30 720 #define SCCR_TSEC1CM_0 0x00000000 721 #define SCCR_TSEC1CM_1 0x40000000 722 #define SCCR_TSEC1CM_2 0x80000000 723 #define SCCR_TSEC1CM_3 0xC0000000 724 725 #define SCCR_TSEC1ON 0x20000000 726 #define SCCR_TSEC1ON_SHIFT 29 727 #define SCCR_TSEC2ON 0x10000000 728 #define SCCR_TSEC2ON_SHIFT 28 729 730 #define SCCR_USBDRCM 0x00300000 731 #define SCCR_USBDRCM_SHIFT 20 732 #define SCCR_USBDRCM_0 0x00000000 733 #define SCCR_USBDRCM_1 0x00100000 734 #define SCCR_USBDRCM_2 0x00200000 735 #define SCCR_USBDRCM_3 0x00300000 736 737 #elif defined(CONFIG_MPC8315) 738 /* SCCR bits - MPC8315 specific */ 739 #define SCCR_TSEC1CM 0xc0000000 740 #define SCCR_TSEC1CM_SHIFT 30 741 #define SCCR_TSEC1CM_0 0x00000000 742 #define SCCR_TSEC1CM_1 0x40000000 743 #define SCCR_TSEC1CM_2 0x80000000 744 #define SCCR_TSEC1CM_3 0xC0000000 745 746 #define SCCR_TSEC2CM 0x30000000 747 #define SCCR_TSEC2CM_SHIFT 28 748 #define SCCR_TSEC2CM_0 0x00000000 749 #define SCCR_TSEC2CM_1 0x10000000 750 #define SCCR_TSEC2CM_2 0x20000000 751 #define SCCR_TSEC2CM_3 0x30000000 752 753 #define SCCR_USBDRCM 0x00c00000 754 #define SCCR_USBDRCM_SHIFT 22 755 #define SCCR_USBDRCM_0 0x00000000 756 #define SCCR_USBDRCM_1 0x00400000 757 #define SCCR_USBDRCM_2 0x00800000 758 #define SCCR_USBDRCM_3 0x00c00000 759 760 #define SCCR_SATA1CM 0x00003000 761 #define SCCR_SATA1CM_SHIFT 12 762 #define SCCR_SATACM 0x00003c00 763 #define SCCR_SATACM_SHIFT 10 764 #define SCCR_SATACM_0 0x00000000 765 #define SCCR_SATACM_1 0x00001400 766 #define SCCR_SATACM_2 0x00002800 767 #define SCCR_SATACM_3 0x00003c00 768 769 #define SCCR_TDMCM 0x00000030 770 #define SCCR_TDMCM_SHIFT 4 771 #define SCCR_TDMCM_0 0x00000000 772 #define SCCR_TDMCM_1 0x00000010 773 #define SCCR_TDMCM_2 0x00000020 774 #define SCCR_TDMCM_3 0x00000030 775 776 #elif defined(CONFIG_MPC837x) 777 /* SCCR bits - MPC837x specific */ 778 #define SCCR_TSEC1CM 0xc0000000 779 #define SCCR_TSEC1CM_SHIFT 30 780 #define SCCR_TSEC1CM_0 0x00000000 781 #define SCCR_TSEC1CM_1 0x40000000 782 #define SCCR_TSEC1CM_2 0x80000000 783 #define SCCR_TSEC1CM_3 0xC0000000 784 785 #define SCCR_TSEC2CM 0x30000000 786 #define SCCR_TSEC2CM_SHIFT 28 787 #define SCCR_TSEC2CM_0 0x00000000 788 #define SCCR_TSEC2CM_1 0x10000000 789 #define SCCR_TSEC2CM_2 0x20000000 790 #define SCCR_TSEC2CM_3 0x30000000 791 792 #define SCCR_SDHCCM 0x0c000000 793 #define SCCR_SDHCCM_SHIFT 26 794 #define SCCR_SDHCCM_0 0x00000000 795 #define SCCR_SDHCCM_1 0x04000000 796 #define SCCR_SDHCCM_2 0x08000000 797 #define SCCR_SDHCCM_3 0x0c000000 798 799 #define SCCR_USBDRCM 0x00c00000 800 #define SCCR_USBDRCM_SHIFT 22 801 #define SCCR_USBDRCM_0 0x00000000 802 #define SCCR_USBDRCM_1 0x00400000 803 #define SCCR_USBDRCM_2 0x00800000 804 #define SCCR_USBDRCM_3 0x00c00000 805 806 /* All of the four SATA controllers must have the same clock ratio */ 807 #define SCCR_SATA1CM 0x000000c0 808 #define SCCR_SATA1CM_SHIFT 6 809 #define SCCR_SATACM 0x000000ff 810 #define SCCR_SATACM_SHIFT 0 811 #define SCCR_SATACM_0 0x00000000 812 #define SCCR_SATACM_1 0x00000055 813 #define SCCR_SATACM_2 0x000000aa 814 #define SCCR_SATACM_3 0x000000ff 815 #endif 816 817 #define SCCR_PCIEXP1CM 0x00300000 818 #define SCCR_PCIEXP1CM_SHIFT 20 819 #define SCCR_PCIEXP1CM_0 0x00000000 820 #define SCCR_PCIEXP1CM_1 0x00100000 821 #define SCCR_PCIEXP1CM_2 0x00200000 822 #define SCCR_PCIEXP1CM_3 0x00300000 823 824 #define SCCR_PCIEXP2CM 0x000c0000 825 #define SCCR_PCIEXP2CM_SHIFT 18 826 #define SCCR_PCIEXP2CM_0 0x00000000 827 #define SCCR_PCIEXP2CM_1 0x00040000 828 #define SCCR_PCIEXP2CM_2 0x00080000 829 #define SCCR_PCIEXP2CM_3 0x000c0000 830 831 /* CSn_BDNS - Chip Select memory Bounds Register 832 */ 833 #define CSBNDS_SA 0x00FF0000 834 #define CSBNDS_SA_SHIFT 8 835 #define CSBNDS_EA 0x000000FF 836 #define CSBNDS_EA_SHIFT 24 837 838 /* CSn_CONFIG - Chip Select Configuration Register 839 */ 840 #define CSCONFIG_EN 0x80000000 841 #define CSCONFIG_AP 0x00800000 842 #define CSCONFIG_ODT_WR_ACS 0x00010000 843 #if defined(CONFIG_MPC832x) 844 #define CSCONFIG_ODT_WR_CFG 0x00040000 845 #endif 846 #define CSCONFIG_BANK_BIT_3 0x00004000 847 #define CSCONFIG_ROW_BIT 0x00000700 848 #define CSCONFIG_ROW_BIT_12 0x00000000 849 #define CSCONFIG_ROW_BIT_13 0x00000100 850 #define CSCONFIG_ROW_BIT_14 0x00000200 851 #define CSCONFIG_COL_BIT 0x00000007 852 #define CSCONFIG_COL_BIT_8 0x00000000 853 #define CSCONFIG_COL_BIT_9 0x00000001 854 #define CSCONFIG_COL_BIT_10 0x00000002 855 #define CSCONFIG_COL_BIT_11 0x00000003 856 857 /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 858 */ 859 #define TIMING_CFG0_RWT 0xC0000000 860 #define TIMING_CFG0_RWT_SHIFT 30 861 #define TIMING_CFG0_WRT 0x30000000 862 #define TIMING_CFG0_WRT_SHIFT 28 863 #define TIMING_CFG0_RRT 0x0C000000 864 #define TIMING_CFG0_RRT_SHIFT 26 865 #define TIMING_CFG0_WWT 0x03000000 866 #define TIMING_CFG0_WWT_SHIFT 24 867 #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 868 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 869 #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 870 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 871 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 872 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 873 #define TIMING_CFG0_MRS_CYC 0x0000000F 874 #define TIMING_CFG0_MRS_CYC_SHIFT 0 875 876 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 877 */ 878 #define TIMING_CFG1_PRETOACT 0x70000000 879 #define TIMING_CFG1_PRETOACT_SHIFT 28 880 #define TIMING_CFG1_ACTTOPRE 0x0F000000 881 #define TIMING_CFG1_ACTTOPRE_SHIFT 24 882 #define TIMING_CFG1_ACTTORW 0x00700000 883 #define TIMING_CFG1_ACTTORW_SHIFT 20 884 #define TIMING_CFG1_CASLAT 0x00070000 885 #define TIMING_CFG1_CASLAT_SHIFT 16 886 #define TIMING_CFG1_REFREC 0x0000F000 887 #define TIMING_CFG1_REFREC_SHIFT 12 888 #define TIMING_CFG1_WRREC 0x00000700 889 #define TIMING_CFG1_WRREC_SHIFT 8 890 #define TIMING_CFG1_ACTTOACT 0x00000070 891 #define TIMING_CFG1_ACTTOACT_SHIFT 4 892 #define TIMING_CFG1_WRTORD 0x00000007 893 #define TIMING_CFG1_WRTORD_SHIFT 0 894 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 895 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 896 #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ 897 #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ 898 #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ 899 #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ 900 #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ 901 902 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 903 */ 904 #define TIMING_CFG2_CPO 0x0F800000 905 #define TIMING_CFG2_CPO_SHIFT 23 906 #define TIMING_CFG2_ACSM 0x00080000 907 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 908 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 909 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 910 911 #define TIMING_CFG2_ADD_LAT 0x70000000 912 #define TIMING_CFG2_ADD_LAT_SHIFT 28 913 #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 914 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 915 #define TIMING_CFG2_RD_TO_PRE 0x0000E000 916 #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 917 #define TIMING_CFG2_CKE_PLS 0x000001C0 918 #define TIMING_CFG2_CKE_PLS_SHIFT 6 919 #define TIMING_CFG2_FOUR_ACT 0x0000003F 920 #define TIMING_CFG2_FOUR_ACT_SHIFT 0 921 922 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 923 */ 924 #define SDRAM_CFG_MEM_EN 0x80000000 925 #define SDRAM_CFG_SREN 0x40000000 926 #define SDRAM_CFG_ECC_EN 0x20000000 927 #define SDRAM_CFG_RD_EN 0x10000000 928 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 929 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 930 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 931 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 932 #define SDRAM_CFG_DYN_PWR 0x00200000 933 #define SDRAM_CFG_32_BE 0x00080000 934 #define SDRAM_CFG_8_BE 0x00040000 935 #define SDRAM_CFG_NCAP 0x00020000 936 #define SDRAM_CFG_2T_EN 0x00008000 937 #define SDRAM_CFG_BI 0x00000001 938 939 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 940 */ 941 #define SDRAM_MODE_ESD 0xFFFF0000 942 #define SDRAM_MODE_ESD_SHIFT 16 943 #define SDRAM_MODE_SD 0x0000FFFF 944 #define SDRAM_MODE_SD_SHIFT 0 945 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 946 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 947 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 948 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 949 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 950 #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 951 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 952 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 953 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 954 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 955 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 956 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 957 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 958 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 959 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 960 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 961 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 962 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 963 #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 964 965 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 966 */ 967 #define SDRAM_INTERVAL_REFINT 0x3FFF0000 968 #define SDRAM_INTERVAL_REFINT_SHIFT 16 969 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 970 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 971 972 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 973 */ 974 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 975 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 976 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 977 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 978 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 979 980 /* ECC_ERR_INJECT - Memory data path error injection mask ECC 981 */ 982 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 983 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 984 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 985 #define ECC_ERR_INJECT_EEIM_SHIFT 0 986 987 /* CAPTURE_ECC - Memory data path read capture ECC 988 */ 989 #define CAPTURE_ECC_ECE (0xff000000>>24) 990 #define CAPTURE_ECC_ECE_SHIFT 0 991 992 /* ERR_DETECT - Memory error detect 993 */ 994 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 995 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 996 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 997 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 998 999 /* ERR_DISABLE - Memory error disable 1000 */ 1001 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 1002 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 1003 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 1004 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 1005 ECC_ERROR_DISABLE_MBED) 1006 /* ERR_INT_EN - Memory error interrupt enable 1007 */ 1008 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 1009 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 1010 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 1011 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 1012 ECC_ERR_INT_EN_MSEE) 1013 /* CAPTURE_ATTRIBUTES - Memory error attributes capture 1014 */ 1015 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 1016 #define ECC_CAPT_ATTR_BNUM_SHIFT 28 1017 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 1018 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 1019 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 1020 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1021 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1022 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 1023 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 1024 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1025 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1026 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1027 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1028 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1029 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1030 #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1031 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1032 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1033 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1034 #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1035 #define ECC_CAPT_ATTR_TSRC_SHIFT 16 1036 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 1037 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1038 #define ECC_CAPT_ATTR_TTYP_READ 0x2 1039 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1040 #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1041 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 1042 1043 /* ERR_SBE - Single bit ECC memory error management 1044 */ 1045 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 1046 #define ECC_ERROR_MAN_SBET_SHIFT 16 1047 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 1048 #define ECC_ERROR_MAN_SBEC_SHIFT 0 1049 1050 /* CONFIG_ADDRESS - PCI Config Address Register 1051 */ 1052 #define PCI_CONFIG_ADDRESS_EN 0x80000000 1053 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1054 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1055 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1056 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1057 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1058 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1059 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1060 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1061 1062 /* POTAR - PCI Outbound Translation Address Register 1063 */ 1064 #define POTAR_TA_MASK 0x000fffff 1065 1066 /* POBAR - PCI Outbound Base Address Register 1067 */ 1068 #define POBAR_BA_MASK 0x000fffff 1069 1070 /* POCMR - PCI Outbound Comparision Mask Register 1071 */ 1072 #define POCMR_EN 0x80000000 1073 #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1074 #define POCMR_SE 0x20000000 /* streaming enable */ 1075 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1076 #define POCMR_CM_MASK 0x000fffff 1077 #define POCMR_CM_4G 0x00000000 1078 #define POCMR_CM_2G 0x00080000 1079 #define POCMR_CM_1G 0x000C0000 1080 #define POCMR_CM_512M 0x000E0000 1081 #define POCMR_CM_256M 0x000F0000 1082 #define POCMR_CM_128M 0x000F8000 1083 #define POCMR_CM_64M 0x000FC000 1084 #define POCMR_CM_32M 0x000FE000 1085 #define POCMR_CM_16M 0x000FF000 1086 #define POCMR_CM_8M 0x000FF800 1087 #define POCMR_CM_4M 0x000FFC00 1088 #define POCMR_CM_2M 0x000FFE00 1089 #define POCMR_CM_1M 0x000FFF00 1090 #define POCMR_CM_512K 0x000FFF80 1091 #define POCMR_CM_256K 0x000FFFC0 1092 #define POCMR_CM_128K 0x000FFFE0 1093 #define POCMR_CM_64K 0x000FFFF0 1094 #define POCMR_CM_32K 0x000FFFF8 1095 #define POCMR_CM_16K 0x000FFFFC 1096 #define POCMR_CM_8K 0x000FFFFE 1097 #define POCMR_CM_4K 0x000FFFFF 1098 1099 /* PITAR - PCI Inbound Translation Address Register 1100 */ 1101 #define PITAR_TA_MASK 0x000fffff 1102 1103 /* PIBAR - PCI Inbound Base/Extended Address Register 1104 */ 1105 #define PIBAR_MASK 0xffffffff 1106 #define PIEBAR_EBA_MASK 0x000fffff 1107 1108 /* PIWAR - PCI Inbound Windows Attributes Register 1109 */ 1110 #define PIWAR_EN 0x80000000 1111 #define PIWAR_PF 0x20000000 1112 #define PIWAR_RTT_MASK 0x000f0000 1113 #define PIWAR_RTT_NO_SNOOP 0x00040000 1114 #define PIWAR_RTT_SNOOP 0x00050000 1115 #define PIWAR_WTT_MASK 0x0000f000 1116 #define PIWAR_WTT_NO_SNOOP 0x00004000 1117 #define PIWAR_WTT_SNOOP 0x00005000 1118 #define PIWAR_IWS_MASK 0x0000003F 1119 #define PIWAR_IWS_4K 0x0000000B 1120 #define PIWAR_IWS_8K 0x0000000C 1121 #define PIWAR_IWS_16K 0x0000000D 1122 #define PIWAR_IWS_32K 0x0000000E 1123 #define PIWAR_IWS_64K 0x0000000F 1124 #define PIWAR_IWS_128K 0x00000010 1125 #define PIWAR_IWS_256K 0x00000011 1126 #define PIWAR_IWS_512K 0x00000012 1127 #define PIWAR_IWS_1M 0x00000013 1128 #define PIWAR_IWS_2M 0x00000014 1129 #define PIWAR_IWS_4M 0x00000015 1130 #define PIWAR_IWS_8M 0x00000016 1131 #define PIWAR_IWS_16M 0x00000017 1132 #define PIWAR_IWS_32M 0x00000018 1133 #define PIWAR_IWS_64M 0x00000019 1134 #define PIWAR_IWS_128M 0x0000001A 1135 #define PIWAR_IWS_256M 0x0000001B 1136 #define PIWAR_IWS_512M 0x0000001C 1137 #define PIWAR_IWS_1G 0x0000001D 1138 #define PIWAR_IWS_2G 0x0000001E 1139 1140 /* PMCCR1 - PCI Configuration Register 1 1141 */ 1142 #define PMCCR1_POWER_OFF 0x00000020 1143 1144 /* DDRCDR - DDR Control Driver Register 1145 */ 1146 #define DDRCDR_DHC_EN 0x80000000 1147 #define DDRCDR_EN 0x40000000 1148 #define DDRCDR_PZ 0x3C000000 1149 #define DDRCDR_PZ_MAXZ 0x00000000 1150 #define DDRCDR_PZ_HIZ 0x20000000 1151 #define DDRCDR_PZ_NOMZ 0x30000000 1152 #define DDRCDR_PZ_LOZ 0x38000000 1153 #define DDRCDR_PZ_MINZ 0x3C000000 1154 #define DDRCDR_NZ 0x3C000000 1155 #define DDRCDR_NZ_MAXZ 0x00000000 1156 #define DDRCDR_NZ_HIZ 0x02000000 1157 #define DDRCDR_NZ_NOMZ 0x03000000 1158 #define DDRCDR_NZ_LOZ 0x03800000 1159 #define DDRCDR_NZ_MINZ 0x03C00000 1160 #define DDRCDR_ODT 0x00080000 1161 #define DDRCDR_DDR_CFG 0x00040000 1162 #define DDRCDR_M_ODR 0x00000002 1163 #define DDRCDR_Q_DRN 0x00000001 1164 1165 /* PCIE Bridge Register 1166 */ 1167 #define PEX_CSB_CTRL_OBPIOE 0x00000001 1168 #define PEX_CSB_CTRL_IBPIOE 0x00000002 1169 #define PEX_CSB_CTRL_WDMAE 0x00000004 1170 #define PEX_CSB_CTRL_RDMAE 0x00000008 1171 1172 #define PEX_CSB_OBCTRL_PIOE 0x00000001 1173 #define PEX_CSB_OBCTRL_MEMWE 0x00000002 1174 #define PEX_CSB_OBCTRL_IOWE 0x00000004 1175 #define PEX_CSB_OBCTRL_CFGWE 0x00000008 1176 1177 #define PEX_CSB_IBCTRL_PIOE 0x00000001 1178 1179 #define PEX_OWAR_EN 0x00000001 1180 #define PEX_OWAR_TYPE_CFG 0x00000000 1181 #define PEX_OWAR_TYPE_IO 0x00000002 1182 #define PEX_OWAR_TYPE_MEM 0x00000004 1183 #define PEX_OWAR_RLXO 0x00000008 1184 #define PEX_OWAR_NANP 0x00000010 1185 #define PEX_OWAR_SIZE 0xFFFFF000 1186 1187 #define PEX_IWAR_EN 0x00000001 1188 #define PEX_IWAR_TYPE_INT 0x00000000 1189 #define PEX_IWAR_TYPE_PF 0x00000004 1190 #define PEX_IWAR_TYPE_NO_PF 0x00000006 1191 #define PEX_IWAR_NSOV 0x00000008 1192 #define PEX_IWAR_NSNP 0x00000010 1193 #define PEX_IWAR_SIZE 0xFFFFF000 1194 #define PEX_IWAR_SIZE_1M 0x000FF000 1195 #define PEX_IWAR_SIZE_2M 0x001FF000 1196 #define PEX_IWAR_SIZE_4M 0x003FF000 1197 #define PEX_IWAR_SIZE_8M 0x007FF000 1198 #define PEX_IWAR_SIZE_16M 0x00FFF000 1199 #define PEX_IWAR_SIZE_32M 0x01FFF000 1200 #define PEX_IWAR_SIZE_64M 0x03FFF000 1201 #define PEX_IWAR_SIZE_128M 0x07FFF000 1202 #define PEX_IWAR_SIZE_256M 0x0FFFF000 1203 1204 #define PEX_GCLK_RATIO 0x440 1205 1206 #ifndef __ASSEMBLY__ 1207 struct pci_region; 1208 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 1209 void mpc83xx_pcislave_unlock(int bus); 1210 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot); 1211 #endif 1212 1213 #endif /* __MPC83XX_H__ */ 1214