xref: /openbmc/u-boot/include/mpc83xx.h (revision 53677ef1)
1 /*
2  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12 
13 #ifndef __MPC83XX_H__
14 #define __MPC83XX_H__
15 
16 #include <config.h>
17 #if defined(CONFIG_E300)
18 #include <asm/e300.h>
19 #endif
20 
21 /* MPC83xx cpu provide RCR register to do reset thing specially
22  */
23 #define MPC83xx_RESET
24 
25 /* System reset offset (PowerPC standard)
26  */
27 #define EXC_OFF_SYS_RESET		0x0100
28 #define	_START_OFFSET			EXC_OFF_SYS_RESET
29 
30 /* IMMRBAR - Internal Memory Register Base Address
31  */
32 #define CONFIG_DEFAULT_IMMR		0xFF400000	/* Default IMMR base address */
33 #define IMMRBAR				0x0000		/* Register offset to immr */
34 #define IMMRBAR_BASE_ADDR		0xFFF00000	/* Base address mask */
35 #define IMMRBAR_RES			~(IMMRBAR_BASE_ADDR)
36 
37 /* LAWBAR - Local Access Window Base Address Register
38  */
39 #define LBLAWBAR0			0x0020		/* Register offset to immr */
40 #define LBLAWAR0			0x0024
41 #define LBLAWBAR1			0x0028
42 #define LBLAWAR1			0x002C
43 #define LBLAWBAR2			0x0030
44 #define LBLAWAR2			0x0034
45 #define LBLAWBAR3			0x0038
46 #define LBLAWAR3			0x003C
47 #define LAWBAR_BAR			0xFFFFF000	/* Base address mask */
48 
49 /* SPRIDR - System Part and Revision ID Register
50  */
51 #define SPRIDR_PARTID			0xFFFF0000	/* Part Id */
52 #define SPRIDR_REVID			0x0000FFFF	/* Revision Id */
53 
54 #if defined(CONFIG_MPC834X)
55 #define REVID_MAJOR(spridr)		((spridr & 0x0000FF00) >> 8)
56 #define REVID_MINOR(spridr)		(spridr & 0x000000FF)
57 #else
58 #define REVID_MAJOR(spridr)		((spridr & 0x000000F0) >> 4)
59 #define REVID_MINOR(spridr)		(spridr & 0x0000000F)
60 #endif
61 
62 #define PARTID_NO_E(spridr)		((spridr & 0xFFFE0000) >> 16)
63 #define IS_E_PROCESSOR(spridr)		(!(spridr & 0x00010000)) /* has SEC */
64 
65 #define SPR_8311			0x80B2
66 #define SPR_8313			0x80B0
67 #define SPR_8314			0x80B6
68 #define SPR_8315			0x80B4
69 #define SPR_8321			0x8066
70 #define SPR_8323			0x8062
71 #define SPR_8343			0x8036
72 #define SPR_8347_TBGA_			0x8032
73 #define SPR_8347_PBGA_			0x8034
74 #define SPR_8349			0x8030
75 #define SPR_8358_TBGA_			0x804A
76 #define SPR_8358_PBGA_			0x804E
77 #define SPR_8360			0x8048
78 #define SPR_8377			0x80C6
79 #define SPR_8378			0x80C4
80 #define SPR_8379			0x80C2
81 
82 /* SPCR - System Priority Configuration Register
83  */
84 #define SPCR_PCIHPE			0x10000000	/* PCI Highest Priority Enable */
85 #define SPCR_PCIHPE_SHIFT		(31-3)
86 #define SPCR_PCIPR			0x03000000	/* PCI bridge system bus request priority */
87 #define SPCR_PCIPR_SHIFT		(31-7)
88 #define SPCR_OPT			0x00800000	/* Optimize */
89 #define SPCR_OPT_SHIFT			(31-8)
90 #define SPCR_TBEN			0x00400000	/* E300 PowerPC core time base unit enable */
91 #define SPCR_TBEN_SHIFT			(31-9)
92 #define SPCR_COREPR			0x00300000	/* E300 PowerPC Core system bus request priority */
93 #define SPCR_COREPR_SHIFT		(31-11)
94 
95 #if defined(CONFIG_MPC834X)
96 /* SPCR bits - MPC8349 specific */
97 #define SPCR_TSEC1DP			0x00003000	/* TSEC1 data priority */
98 #define SPCR_TSEC1DP_SHIFT		(31-19)
99 #define SPCR_TSEC1BDP			0x00000C00	/* TSEC1 buffer descriptor priority */
100 #define SPCR_TSEC1BDP_SHIFT		(31-21)
101 #define SPCR_TSEC1EP			0x00000300	/* TSEC1 emergency priority */
102 #define SPCR_TSEC1EP_SHIFT		(31-23)
103 #define SPCR_TSEC2DP			0x00000030	/* TSEC2 data priority */
104 #define SPCR_TSEC2DP_SHIFT		(31-27)
105 #define SPCR_TSEC2BDP			0x0000000C	/* TSEC2 buffer descriptor priority */
106 #define SPCR_TSEC2BDP_SHIFT		(31-29)
107 #define SPCR_TSEC2EP			0x00000003	/* TSEC2 emergency priority */
108 #define SPCR_TSEC2EP_SHIFT		(31-31)
109 
110 #elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
111 /* SPCR bits - MPC831x and MPC837x specific */
112 #define SPCR_TSECDP			0x00003000	/* TSEC data priority */
113 #define SPCR_TSECDP_SHIFT		(31-19)
114 #define SPCR_TSECBDP			0x00000C00	/* TSEC buffer descriptor priority */
115 #define SPCR_TSECBDP_SHIFT		(31-21)
116 #define SPCR_TSECEP			0x00000300	/* TSEC emergency priority */
117 #define SPCR_TSECEP_SHIFT		(31-23)
118 #endif
119 
120 /* SICRL/H - System I/O Configuration Register Low/High
121  */
122 #if defined(CONFIG_MPC834X)
123 /* SICRL bits - MPC8349 specific */
124 #define SICRL_LDP_A			0x80000000
125 #define SICRL_USB1			0x40000000
126 #define SICRL_USB0			0x20000000
127 #define SICRL_UART			0x0C000000
128 #define SICRL_GPIO1_A			0x02000000
129 #define SICRL_GPIO1_B			0x01000000
130 #define SICRL_GPIO1_C			0x00800000
131 #define SICRL_GPIO1_D			0x00400000
132 #define SICRL_GPIO1_E			0x00200000
133 #define SICRL_GPIO1_F			0x00180000
134 #define SICRL_GPIO1_G			0x00040000
135 #define SICRL_GPIO1_H			0x00020000
136 #define SICRL_GPIO1_I			0x00010000
137 #define SICRL_GPIO1_J			0x00008000
138 #define SICRL_GPIO1_K			0x00004000
139 #define SICRL_GPIO1_L			0x00003000
140 
141 /* SICRH bits - MPC8349 specific */
142 #define SICRH_DDR			0x80000000
143 #define SICRH_TSEC1_A			0x10000000
144 #define SICRH_TSEC1_B			0x08000000
145 #define SICRH_TSEC1_C			0x04000000
146 #define SICRH_TSEC1_D			0x02000000
147 #define SICRH_TSEC1_E			0x01000000
148 #define SICRH_TSEC1_F			0x00800000
149 #define SICRH_TSEC2_A			0x00400000
150 #define SICRH_TSEC2_B			0x00200000
151 #define SICRH_TSEC2_C			0x00100000
152 #define SICRH_TSEC2_D			0x00080000
153 #define SICRH_TSEC2_E			0x00040000
154 #define SICRH_TSEC2_F			0x00020000
155 #define SICRH_TSEC2_G			0x00010000
156 #define SICRH_TSEC2_H			0x00008000
157 #define SICRH_GPIO2_A			0x00004000
158 #define SICRH_GPIO2_B			0x00002000
159 #define SICRH_GPIO2_C			0x00001000
160 #define SICRH_GPIO2_D			0x00000800
161 #define SICRH_GPIO2_E			0x00000400
162 #define SICRH_GPIO2_F			0x00000200
163 #define SICRH_GPIO2_G			0x00000180
164 #define SICRH_GPIO2_H			0x00000060
165 #define SICRH_TSOBI1			0x00000002
166 #define SICRH_TSOBI2			0x00000001
167 
168 #elif defined(CONFIG_MPC8360)
169 /* SICRL bits - MPC8360 specific */
170 #define SICRL_LDP_A			0xC0000000
171 #define SICRL_LCLK_1			0x10000000
172 #define SICRL_LCLK_2			0x08000000
173 #define SICRL_SRCID_A			0x03000000
174 #define SICRL_IRQ_CKSTP_A		0x00C00000
175 
176 /* SICRH bits - MPC8360 specific */
177 #define SICRH_DDR			0x80000000
178 #define SICRH_SECONDARY_DDR		0x40000000
179 #define SICRH_SDDROE			0x20000000
180 #define SICRH_IRQ3			0x10000000
181 #define SICRH_UC1EOBI			0x00000004
182 #define SICRH_UC2E1OBI			0x00000002
183 #define SICRH_UC2E2OBI			0x00000001
184 
185 #elif defined(CONFIG_MPC832X)
186 /* SICRL bits - MPC832X specific */
187 #define SICRL_LDP_LCS_A			0x80000000
188 #define SICRL_IRQ_CKS			0x20000000
189 #define SICRL_PCI_MSRC			0x10000000
190 #define SICRL_URT_CTPR			0x06000000
191 #define SICRL_IRQ_CTPR			0x00C00000
192 
193 #elif defined(CONFIG_MPC8313)
194 /* SICRL bits - MPC8313 specific */
195 #define SICRL_LBC			0x30000000
196 #define SICRL_UART			0x0C000000
197 #define SICRL_SPI_A			0x03000000
198 #define SICRL_SPI_B			0x00C00000
199 #define SICRL_SPI_C			0x00300000
200 #define SICRL_SPI_D			0x000C0000
201 #define SICRL_USBDR			0x00000C00
202 #define SICRL_ETSEC1_A			0x0000000C
203 #define SICRL_ETSEC2_A			0x00000003
204 
205 /* SICRH bits - MPC8313 specific */
206 #define SICRH_INTR_A			0x02000000
207 #define SICRH_INTR_B			0x00C00000
208 #define SICRH_IIC			0x00300000
209 #define SICRH_ETSEC2_B			0x000C0000
210 #define SICRH_ETSEC2_C			0x00030000
211 #define SICRH_ETSEC2_D			0x0000C000
212 #define SICRH_ETSEC2_E			0x00003000
213 #define SICRH_ETSEC2_F			0x00000C00
214 #define SICRH_ETSEC2_G			0x00000300
215 #define SICRH_ETSEC1_B			0x00000080
216 #define SICRH_ETSEC1_C			0x00000060
217 #define SICRH_GTX1_DLY			0x00000008
218 #define SICRH_GTX2_DLY			0x00000004
219 #define SICRH_TSOBI1			0x00000002
220 #define SICRH_TSOBI2			0x00000001
221 
222 #elif defined(CONFIG_MPC8315)
223 /* SICRL bits - MPC8315 specific */
224 #define SICRL_DMA_CH0			0xc0000000
225 #define SICRL_DMA_SPI			0x30000000
226 #define SICRL_UART			0x0c000000
227 #define SICRL_IRQ4			0x02000000
228 #define SICRL_IRQ5			0x01800000
229 #define SICRL_IRQ6_7			0x00400000
230 #define SICRL_IIC1			0x00300000
231 #define SICRL_TDM			0x000c0000
232 #define SICRL_TDM_SHARED		0x00030000
233 #define SICRL_PCI_A			0x0000c000
234 #define SICRL_ELBC_A			0x00003000
235 #define SICRL_ETSEC1_A			0x000000c0
236 #define SICRL_ETSEC1_B			0x00000030
237 #define SICRL_ETSEC1_C			0x0000000c
238 #define SICRL_TSEXPOBI			0x00000001
239 
240 /* SICRH bits - MPC8315 specific */
241 #define SICRH_GPIO_0			0xc0000000
242 #define SICRH_GPIO_1			0x30000000
243 #define SICRH_GPIO_2			0x0c000000
244 #define SICRH_GPIO_3			0x03000000
245 #define SICRH_GPIO_4			0x00c00000
246 #define SICRH_GPIO_5			0x00300000
247 #define SICRH_GPIO_6			0x000c0000
248 #define SICRH_GPIO_7			0x00030000
249 #define SICRH_GPIO_8			0x0000c000
250 #define SICRH_GPIO_9			0x00003000
251 #define SICRH_GPIO_10			0x00000c00
252 #define SICRH_GPIO_11			0x00000300
253 #define SICRH_ETSEC2_A			0x000000c0
254 #define SICRH_TSOBI1			0x00000002
255 #define SICRH_TSOBI2			0x00000001
256 
257 #elif defined(CONFIG_MPC837X)
258 /* SICRL bits - MPC837x specific */
259 #define SICRL_USB_A			0xC0000000
260 #define SICRL_USB_B			0x30000000
261 #define SICRL_UART			0x0C000000
262 #define SICRL_GPIO_A			0x02000000
263 #define SICRL_GPIO_B			0x01000000
264 #define SICRL_GPIO_C			0x00800000
265 #define SICRL_GPIO_D			0x00400000
266 #define SICRL_GPIO_E			0x00200000
267 #define SICRL_GPIO_F			0x00180000
268 #define SICRL_GPIO_G			0x00040000
269 #define SICRL_GPIO_H			0x00020000
270 #define SICRL_GPIO_I			0x00010000
271 #define SICRL_GPIO_J			0x00008000
272 #define SICRL_GPIO_K			0x00004000
273 #define SICRL_GPIO_L			0x00003000
274 #define SICRL_DMA_A			0x00000800
275 #define SICRL_DMA_B			0x00000400
276 #define SICRL_DMA_C			0x00000200
277 #define SICRL_DMA_D			0x00000100
278 #define SICRL_DMA_E			0x00000080
279 #define SICRL_DMA_F			0x00000040
280 #define SICRL_DMA_G			0x00000020
281 #define SICRL_DMA_H			0x00000010
282 #define SICRL_DMA_I			0x00000008
283 #define SICRL_DMA_J			0x00000004
284 #define SICRL_LDP_A			0x00000002
285 #define SICRL_LDP_B			0x00000001
286 
287 /* SICRH bits - MPC837x specific */
288 #define SICRH_DDR			0x80000000
289 #define SICRH_TSEC1_A			0x10000000
290 #define SICRH_TSEC1_B			0x08000000
291 #define SICRH_TSEC2_A			0x00400000
292 #define SICRH_TSEC2_B			0x00200000
293 #define SICRH_TSEC2_C			0x00100000
294 #define SICRH_TSEC2_D			0x00080000
295 #define SICRH_TSEC2_E			0x00040000
296 #define SICRH_TMR			0x00010000
297 #define SICRH_GPIO2_A			0x00008000
298 #define SICRH_GPIO2_B			0x00004000
299 #define SICRH_GPIO2_C			0x00002000
300 #define SICRH_GPIO2_D			0x00001000
301 #define SICRH_GPIO2_E			0x00000C00
302 #define SICRH_GPIO2_F			0x00000300
303 #define SICRH_GPIO2_G			0x000000C0
304 #define SICRH_GPIO2_H			0x00000030
305 #define SICRH_SPI			0x00000003
306 #endif
307 
308 /* SWCRR - System Watchdog Control Register
309  */
310 #define SWCRR				0x0204		/* Register offset to immr */
311 #define SWCRR_SWTC			0xFFFF0000	/* Software Watchdog Time Count */
312 #define SWCRR_SWEN			0x00000004	/* Watchdog Enable bit */
313 #define SWCRR_SWRI			0x00000002	/* Software Watchdog Reset/Interrupt Select bit */
314 #define SWCRR_SWPR			0x00000001	/* Software Watchdog Counter Prescale bit */
315 #define SWCRR_RES			~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
316 
317 /* SWCNR - System Watchdog Counter Register
318  */
319 #define SWCNR				0x0208		/* Register offset to immr */
320 #define SWCNR_SWCN			0x0000FFFF	/* Software Watchdog Count mask */
321 #define SWCNR_RES			~(SWCNR_SWCN)
322 
323 /* SWSRR - System Watchdog Service Register
324  */
325 #define SWSRR				0x020E		/* Register offset to immr */
326 
327 /* ACR - Arbiter Configuration Register
328  */
329 #define ACR_COREDIS			0x10000000	/* Core disable */
330 #define ACR_COREDIS_SHIFT		(31-7)
331 #define ACR_PIPE_DEP			0x00070000	/* Pipeline depth */
332 #define ACR_PIPE_DEP_SHIFT		(31-15)
333 #define ACR_PCI_RPTCNT			0x00007000	/* PCI repeat count */
334 #define ACR_PCI_RPTCNT_SHIFT		(31-19)
335 #define ACR_RPTCNT			0x00000700	/* Repeat count */
336 #define ACR_RPTCNT_SHIFT		(31-23)
337 #define ACR_APARK			0x00000030	/* Address parking */
338 #define ACR_APARK_SHIFT			(31-27)
339 #define ACR_PARKM			0x0000000F	/* Parking master */
340 #define ACR_PARKM_SHIFT			(31-31)
341 
342 /* ATR - Arbiter Timers Register
343  */
344 #define ATR_DTO				0x00FF0000	/* Data time out */
345 #define ATR_ATO				0x000000FF	/* Address time out */
346 
347 /* AER - Arbiter Event Register
348  */
349 #define AER_ETEA			0x00000020	/* Transfer error */
350 #define AER_RES				0x00000010	/* Reserved transfer type */
351 #define AER_ECW				0x00000008	/* External control word transfer type */
352 #define AER_AO				0x00000004	/* Address Only transfer type */
353 #define AER_DTO				0x00000002	/* Data time out */
354 #define AER_ATO				0x00000001	/* Address time out */
355 
356 /* AEATR - Arbiter Event Address Register
357  */
358 #define AEATR_EVENT			0x07000000	/* Event type */
359 #define AEATR_MSTR_ID			0x001F0000	/* Master Id */
360 #define AEATR_TBST			0x00000800	/* Transfer burst */
361 #define AEATR_TSIZE			0x00000700	/* Transfer Size */
362 #define AEATR_TTYPE			0x0000001F	/* Transfer Type */
363 
364 /* HRCWL - Hard Reset Configuration Word Low
365  */
366 #define HRCWL_LBIUCM			0x80000000
367 #define HRCWL_LBIUCM_SHIFT		31
368 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1	0x00000000
369 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1	0x80000000
370 
371 #define HRCWL_DDRCM			0x40000000
372 #define HRCWL_DDRCM_SHIFT		30
373 #define HRCWL_DDR_TO_SCB_CLK_1X1	0x00000000
374 #define HRCWL_DDR_TO_SCB_CLK_2X1	0x40000000
375 
376 #define HRCWL_SPMF			0x0f000000
377 #define HRCWL_SPMF_SHIFT		24
378 #define HRCWL_CSB_TO_CLKIN_16X1		0x00000000
379 #define HRCWL_CSB_TO_CLKIN_1X1		0x01000000
380 #define HRCWL_CSB_TO_CLKIN_2X1		0x02000000
381 #define HRCWL_CSB_TO_CLKIN_3X1		0x03000000
382 #define HRCWL_CSB_TO_CLKIN_4X1		0x04000000
383 #define HRCWL_CSB_TO_CLKIN_5X1		0x05000000
384 #define HRCWL_CSB_TO_CLKIN_6X1		0x06000000
385 #define HRCWL_CSB_TO_CLKIN_7X1		0x07000000
386 #define HRCWL_CSB_TO_CLKIN_8X1		0x08000000
387 #define HRCWL_CSB_TO_CLKIN_9X1		0x09000000
388 #define HRCWL_CSB_TO_CLKIN_10X1		0x0A000000
389 #define HRCWL_CSB_TO_CLKIN_11X1		0x0B000000
390 #define HRCWL_CSB_TO_CLKIN_12X1		0x0C000000
391 #define HRCWL_CSB_TO_CLKIN_13X1		0x0D000000
392 #define HRCWL_CSB_TO_CLKIN_14X1		0x0E000000
393 #define HRCWL_CSB_TO_CLKIN_15X1		0x0F000000
394 
395 #define HRCWL_VCO_BYPASS		0x00000000
396 #define HRCWL_VCO_1X2			0x00000000
397 #define HRCWL_VCO_1X4			0x00200000
398 #define HRCWL_VCO_1X8			0x00400000
399 
400 #define HRCWL_COREPLL			0x007F0000
401 #define HRCWL_COREPLL_SHIFT		16
402 #define HRCWL_CORE_TO_CSB_BYPASS	0x00000000
403 #define HRCWL_CORE_TO_CSB_1X1		0x00020000
404 #define HRCWL_CORE_TO_CSB_1_5X1		0x00030000
405 #define HRCWL_CORE_TO_CSB_2X1		0x00040000
406 #define HRCWL_CORE_TO_CSB_2_5X1		0x00050000
407 #define HRCWL_CORE_TO_CSB_3X1		0x00060000
408 
409 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
410 #define HRCWL_CEVCOD			0x000000C0
411 #define HRCWL_CEVCOD_SHIFT		6
412 #define HRCWL_CE_PLL_VCO_DIV_4		0x00000000
413 #define HRCWL_CE_PLL_VCO_DIV_8		0x00000040
414 #define HRCWL_CE_PLL_VCO_DIV_2		0x00000080
415 
416 #define HRCWL_CEPDF			0x00000020
417 #define HRCWL_CEPDF_SHIFT		5
418 #define HRCWL_CE_PLL_DIV_1X1		0x00000000
419 #define HRCWL_CE_PLL_DIV_2X1		0x00000020
420 
421 #define HRCWL_CEPMF			0x0000001F
422 #define HRCWL_CEPMF_SHIFT		0
423 #define HRCWL_CE_TO_PLL_1X16_		0x00000000
424 #define HRCWL_CE_TO_PLL_1X2		0x00000002
425 #define HRCWL_CE_TO_PLL_1X3		0x00000003
426 #define HRCWL_CE_TO_PLL_1X4		0x00000004
427 #define HRCWL_CE_TO_PLL_1X5		0x00000005
428 #define HRCWL_CE_TO_PLL_1X6		0x00000006
429 #define HRCWL_CE_TO_PLL_1X7		0x00000007
430 #define HRCWL_CE_TO_PLL_1X8		0x00000008
431 #define HRCWL_CE_TO_PLL_1X9		0x00000009
432 #define HRCWL_CE_TO_PLL_1X10		0x0000000A
433 #define HRCWL_CE_TO_PLL_1X11		0x0000000B
434 #define HRCWL_CE_TO_PLL_1X12		0x0000000C
435 #define HRCWL_CE_TO_PLL_1X13		0x0000000D
436 #define HRCWL_CE_TO_PLL_1X14		0x0000000E
437 #define HRCWL_CE_TO_PLL_1X15		0x0000000F
438 #define HRCWL_CE_TO_PLL_1X16		0x00000010
439 #define HRCWL_CE_TO_PLL_1X17		0x00000011
440 #define HRCWL_CE_TO_PLL_1X18		0x00000012
441 #define HRCWL_CE_TO_PLL_1X19		0x00000013
442 #define HRCWL_CE_TO_PLL_1X20		0x00000014
443 #define HRCWL_CE_TO_PLL_1X21		0x00000015
444 #define HRCWL_CE_TO_PLL_1X22		0x00000016
445 #define HRCWL_CE_TO_PLL_1X23		0x00000017
446 #define HRCWL_CE_TO_PLL_1X24		0x00000018
447 #define HRCWL_CE_TO_PLL_1X25		0x00000019
448 #define HRCWL_CE_TO_PLL_1X26		0x0000001A
449 #define HRCWL_CE_TO_PLL_1X27		0x0000001B
450 #define HRCWL_CE_TO_PLL_1X28		0x0000001C
451 #define HRCWL_CE_TO_PLL_1X29		0x0000001D
452 #define HRCWL_CE_TO_PLL_1X30		0x0000001E
453 #define HRCWL_CE_TO_PLL_1X31		0x0000001F
454 
455 #elif defined(CONFIG_MPC8315)
456 #define HRCWL_SVCOD			0x30000000
457 #define HRCWL_SVCOD_SHIFT		28
458 #define HRCWL_SVCOD_DIV_2		0x00000000
459 #define HRCWL_SVCOD_DIV_4		0x10000000
460 #define HRCWL_SVCOD_DIV_8		0x20000000
461 #define HRCWL_SVCOD_DIV_1		0x30000000
462 
463 #elif defined(CONFIG_MPC837X)
464 #define HRCWL_SVCOD			0x30000000
465 #define HRCWL_SVCOD_SHIFT		28
466 #define HRCWL_SVCOD_DIV_4		0x00000000
467 #define HRCWL_SVCOD_DIV_8		0x10000000
468 #define HRCWL_SVCOD_DIV_2		0x20000000
469 #define HRCWL_SVCOD_DIV_1		0x30000000
470 #endif
471 
472 /* HRCWH - Hardware Reset Configuration Word High
473  */
474 #define HRCWH_PCI_HOST			0x80000000
475 #define HRCWH_PCI_HOST_SHIFT		31
476 #define HRCWH_PCI_AGENT			0x00000000
477 
478 #if defined(CONFIG_MPC834X)
479 #define HRCWH_32_BIT_PCI		0x00000000
480 #define HRCWH_64_BIT_PCI		0x40000000
481 #endif
482 
483 #define HRCWH_PCI1_ARBITER_DISABLE	0x00000000
484 #define HRCWH_PCI1_ARBITER_ENABLE	0x20000000
485 
486 #define HRCWH_PCI_ARBITER_DISABLE	0x00000000
487 #define HRCWH_PCI_ARBITER_ENABLE	0x20000000
488 
489 #if defined(CONFIG_MPC834X)
490 #define HRCWH_PCI2_ARBITER_DISABLE	0x00000000
491 #define HRCWH_PCI2_ARBITER_ENABLE	0x10000000
492 
493 #elif defined(CONFIG_MPC8360)
494 #define HRCWH_PCICKDRV_DISABLE		0x00000000
495 #define HRCWH_PCICKDRV_ENABLE		0x10000000
496 #endif
497 
498 #define HRCWH_CORE_DISABLE		0x08000000
499 #define HRCWH_CORE_ENABLE		0x00000000
500 
501 #define HRCWH_FROM_0X00000100		0x00000000
502 #define HRCWH_FROM_0XFFF00100		0x04000000
503 
504 #define HRCWH_BOOTSEQ_DISABLE		0x00000000
505 #define HRCWH_BOOTSEQ_NORMAL		0x01000000
506 #define HRCWH_BOOTSEQ_EXTENDED		0x02000000
507 
508 #define HRCWH_SW_WATCHDOG_DISABLE	0x00000000
509 #define HRCWH_SW_WATCHDOG_ENABLE	0x00800000
510 
511 #define HRCWH_ROM_LOC_DDR_SDRAM		0x00000000
512 #define HRCWH_ROM_LOC_PCI1		0x00100000
513 #if defined(CONFIG_MPC834X)
514 #define HRCWH_ROM_LOC_PCI2		0x00200000
515 #endif
516 #if defined(CONIFG_MPC837X)
517 #define HRCWH_ROM_LOC_ON_CHIP_ROM	0x00300000
518 #endif
519 #define HRCWH_ROM_LOC_LOCAL_8BIT	0x00500000
520 #define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
521 #define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
522 
523 #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
524 #define HRCWH_ROM_LOC_NAND_SP_8BIT	0x00100000
525 #define HRCWH_ROM_LOC_NAND_SP_16BIT	0x00200000
526 #define HRCWH_ROM_LOC_NAND_LP_8BIT	0x00500000
527 #define HRCWH_ROM_LOC_NAND_LP_16BIT	0x00600000
528 
529 #define HRCWH_RL_EXT_LEGACY		0x00000000
530 #define HRCWH_RL_EXT_NAND		0x00040000
531 
532 #define HRCWH_TSEC1M_IN_MII		0x00000000
533 #define HRCWH_TSEC1M_IN_RMII		0x00002000
534 #define HRCWH_TSEC1M_IN_RGMII		0x00006000
535 #define HRCWH_TSEC1M_IN_RTBI		0x0000A000
536 #define HRCWH_TSEC1M_IN_SGMII		0x0000C000
537 
538 #define HRCWH_TSEC2M_IN_MII		0x00000000
539 #define HRCWH_TSEC2M_IN_RMII		0x00000400
540 #define HRCWH_TSEC2M_IN_RGMII		0x00000C00
541 #define HRCWH_TSEC2M_IN_RTBI		0x00001400
542 #define HRCWH_TSEC2M_IN_SGMII		0x00001800
543 #endif
544 
545 #if defined(CONFIG_MPC834X)
546 #define HRCWH_TSEC1M_IN_RGMII		0x00000000
547 #define HRCWH_TSEC1M_IN_RTBI		0x00004000
548 #define HRCWH_TSEC1M_IN_GMII		0x00008000
549 #define HRCWH_TSEC1M_IN_TBI		0x0000C000
550 #define HRCWH_TSEC2M_IN_RGMII		0x00000000
551 #define HRCWH_TSEC2M_IN_RTBI		0x00001000
552 #define HRCWH_TSEC2M_IN_GMII		0x00002000
553 #define HRCWH_TSEC2M_IN_TBI		0x00003000
554 #endif
555 
556 #if defined(CONFIG_MPC8360)
557 #define HRCWH_SECONDARY_DDR_DISABLE	0x00000000
558 #define HRCWH_SECONDARY_DDR_ENABLE	0x00000010
559 #endif
560 
561 #define HRCWH_BIG_ENDIAN		0x00000000
562 #define HRCWH_LITTLE_ENDIAN		0x00000008
563 
564 #define HRCWH_LALE_NORMAL		0x00000000
565 #define HRCWH_LALE_EARLY		0x00000004
566 
567 #define HRCWH_LDP_SET			0x00000000
568 #define HRCWH_LDP_CLEAR			0x00000002
569 
570 /* RSR - Reset Status Register
571  */
572 #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
573 #define RSR_RSTSRC			0xF0000000	/* Reset source */
574 #define RSR_RSTSRC_SHIFT		28
575 #else
576 #define RSR_RSTSRC			0xE0000000	/* Reset source */
577 #define RSR_RSTSRC_SHIFT		29
578 #endif
579 #define RSR_BSF				0x00010000	/* Boot seq. fail */
580 #define RSR_BSF_SHIFT			16
581 #define RSR_SWSR			0x00002000	/* software soft reset */
582 #define RSR_SWSR_SHIFT			13
583 #define RSR_SWHR			0x00001000	/* software hard reset */
584 #define RSR_SWHR_SHIFT			12
585 #define RSR_JHRS			0x00000200	/* jtag hreset */
586 #define RSR_JHRS_SHIFT			9
587 #define RSR_JSRS			0x00000100	/* jtag sreset status */
588 #define RSR_JSRS_SHIFT			8
589 #define RSR_CSHR			0x00000010	/* checkstop reset status */
590 #define RSR_CSHR_SHIFT			4
591 #define RSR_SWRS			0x00000008	/* software watchdog reset status */
592 #define RSR_SWRS_SHIFT			3
593 #define RSR_BMRS			0x00000004	/* bus monitop reset status */
594 #define RSR_BMRS_SHIFT			2
595 #define RSR_SRS				0x00000002	/* soft reset status */
596 #define RSR_SRS_SHIFT			1
597 #define RSR_HRS				0x00000001	/* hard reset status */
598 #define RSR_HRS_SHIFT			0
599 #define RSR_RES				~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\
600 					 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
601 					 RSR_BMRS | RSR_SRS | RSR_HRS)
602 /* RMR - Reset Mode Register
603  */
604 #define RMR_CSRE			0x00000001	/* checkstop reset enable */
605 #define RMR_CSRE_SHIFT			0
606 #define RMR_RES				~(RMR_CSRE)
607 
608 /* RCR - Reset Control Register
609  */
610 #define RCR_SWHR			0x00000002	/* software hard reset */
611 #define RCR_SWSR			0x00000001	/* software soft reset */
612 #define RCR_RES				~(RCR_SWHR | RCR_SWSR)
613 
614 /* RCER - Reset Control Enable Register
615  */
616 #define RCER_CRE			0x00000001	/* software hard reset */
617 #define RCER_RES			~(RCER_CRE)
618 
619 /* SPMR - System PLL Mode Register
620  */
621 #define SPMR_LBIUCM			0x80000000
622 #define SPMR_DDRCM			0x40000000
623 #define SPMR_SPMF			0x0F000000
624 #define SPMR_CKID			0x00800000
625 #define SPMR_CKID_SHIFT			23
626 #define SPMR_COREPLL			0x007F0000
627 #define SPMR_CEVCOD			0x000000C0
628 #define SPMR_CEPDF			0x00000020
629 #define SPMR_CEPMF			0x0000001F
630 
631 /* OCCR - Output Clock Control Register
632  */
633 #define OCCR_PCICOE0			0x80000000
634 #define OCCR_PCICOE1			0x40000000
635 #define OCCR_PCICOE2			0x20000000
636 #define OCCR_PCICOE3			0x10000000
637 #define OCCR_PCICOE4			0x08000000
638 #define OCCR_PCICOE5			0x04000000
639 #define OCCR_PCICOE6			0x02000000
640 #define OCCR_PCICOE7			0x01000000
641 #define OCCR_PCICD0			0x00800000
642 #define OCCR_PCICD1			0x00400000
643 #define OCCR_PCICD2			0x00200000
644 #define OCCR_PCICD3			0x00100000
645 #define OCCR_PCICD4			0x00080000
646 #define OCCR_PCICD5			0x00040000
647 #define OCCR_PCICD6			0x00020000
648 #define OCCR_PCICD7			0x00010000
649 #define OCCR_PCI1CR			0x00000002
650 #define OCCR_PCI2CR			0x00000001
651 #define OCCR_PCICR			OCCR_PCI1CR
652 
653 /* SCCR - System Clock Control Register
654  */
655 #define SCCR_ENCCM			0x03000000
656 #define SCCR_ENCCM_SHIFT		24
657 #define SCCR_ENCCM_0			0x00000000
658 #define SCCR_ENCCM_1			0x01000000
659 #define SCCR_ENCCM_2			0x02000000
660 #define SCCR_ENCCM_3			0x03000000
661 
662 #define SCCR_PCICM			0x00010000
663 #define SCCR_PCICM_SHIFT		16
664 
665 #if defined(CONFIG_MPC834X)
666 /* SCCR bits - MPC834x specific */
667 #define SCCR_TSEC1CM			0xc0000000
668 #define SCCR_TSEC1CM_SHIFT		30
669 #define SCCR_TSEC1CM_0			0x00000000
670 #define SCCR_TSEC1CM_1			0x40000000
671 #define SCCR_TSEC1CM_2			0x80000000
672 #define SCCR_TSEC1CM_3			0xC0000000
673 
674 #define SCCR_TSEC2CM			0x30000000
675 #define SCCR_TSEC2CM_SHIFT		28
676 #define SCCR_TSEC2CM_0			0x00000000
677 #define SCCR_TSEC2CM_1			0x10000000
678 #define SCCR_TSEC2CM_2			0x20000000
679 #define SCCR_TSEC2CM_3			0x30000000
680 
681 /* The MPH must have the same clock ratio as DR, unless its clock disabled */
682 #define SCCR_USBMPHCM			0x00c00000
683 #define SCCR_USBMPHCM_SHIFT		22
684 #define SCCR_USBDRCM			0x00300000
685 #define SCCR_USBDRCM_SHIFT		20
686 #define SCCR_USBCM			0x00f00000
687 #define SCCR_USBCM_SHIFT		20
688 #define SCCR_USBCM_0			0x00000000
689 #define SCCR_USBCM_1			0x00500000
690 #define SCCR_USBCM_2			0x00A00000
691 #define SCCR_USBCM_3			0x00F00000
692 
693 #elif defined(CONFIG_MPC8313)
694 /* TSEC1 bits are for TSEC2 as well */
695 #define SCCR_TSEC1CM			0xc0000000
696 #define SCCR_TSEC1CM_SHIFT		30
697 #define SCCR_TSEC1CM_0			0x00000000
698 #define SCCR_TSEC1CM_1			0x40000000
699 #define SCCR_TSEC1CM_2			0x80000000
700 #define SCCR_TSEC1CM_3			0xC0000000
701 
702 #define SCCR_TSEC1ON			0x20000000
703 #define SCCR_TSEC1ON_SHIFT		29
704 #define SCCR_TSEC2ON			0x10000000
705 #define SCCR_TSEC2ON_SHIFT		28
706 
707 #define SCCR_USBDRCM			0x00300000
708 #define SCCR_USBDRCM_SHIFT		20
709 #define SCCR_USBDRCM_0			0x00000000
710 #define SCCR_USBDRCM_1			0x00100000
711 #define SCCR_USBDRCM_2			0x00200000
712 #define SCCR_USBDRCM_3			0x00300000
713 
714 #elif defined(CONFIG_MPC8315)
715 /* SCCR bits - MPC8315 specific */
716 #define SCCR_TSEC1CM			0xc0000000
717 #define SCCR_TSEC1CM_SHIFT		30
718 #define SCCR_TSEC1CM_0			0x00000000
719 #define SCCR_TSEC1CM_1			0x40000000
720 #define SCCR_TSEC1CM_2			0x80000000
721 #define SCCR_TSEC1CM_3			0xC0000000
722 
723 #define SCCR_TSEC2CM			0x30000000
724 #define SCCR_TSEC2CM_SHIFT		28
725 #define SCCR_TSEC2CM_0			0x00000000
726 #define SCCR_TSEC2CM_1			0x10000000
727 #define SCCR_TSEC2CM_2			0x20000000
728 #define SCCR_TSEC2CM_3			0x30000000
729 
730 #define SCCR_USBDRCM			0x00c00000
731 #define SCCR_USBDRCM_SHIFT		22
732 #define SCCR_USBDRCM_0			0x00000000
733 #define SCCR_USBDRCM_1			0x00400000
734 #define SCCR_USBDRCM_2			0x00800000
735 #define SCCR_USBDRCM_3			0x00c00000
736 
737 #define SCCR_PCIEXP1CM			0x00300000
738 #define SCCR_PCIEXP2CM			0x000c0000
739 
740 #define SCCR_SATA1CM			0x00003000
741 #define SCCR_SATA1CM_SHIFT		12
742 #define SCCR_SATACM			0x00003c00
743 #define SCCR_SATACM_SHIFT		10
744 #define SCCR_SATACM_0			0x00000000
745 #define SCCR_SATACM_1			0x00001400
746 #define SCCR_SATACM_2			0x00002800
747 #define SCCR_SATACM_3			0x00003c00
748 
749 #define SCCR_TDMCM			0x00000030
750 #define SCCR_TDMCM_SHIFT		4
751 #define SCCR_TDMCM_0			0x00000000
752 #define SCCR_TDMCM_1			0x00000010
753 #define SCCR_TDMCM_2			0x00000020
754 #define SCCR_TDMCM_3			0x00000030
755 
756 #elif defined(CONFIG_MPC837X)
757 /* SCCR bits - MPC837x specific */
758 #define SCCR_TSEC1CM			0xc0000000
759 #define SCCR_TSEC1CM_SHIFT		30
760 #define SCCR_TSEC1CM_0			0x00000000
761 #define SCCR_TSEC1CM_1			0x40000000
762 #define SCCR_TSEC1CM_2			0x80000000
763 #define SCCR_TSEC1CM_3			0xC0000000
764 
765 #define SCCR_TSEC2CM			0x30000000
766 #define SCCR_TSEC2CM_SHIFT		28
767 #define SCCR_TSEC2CM_0			0x00000000
768 #define SCCR_TSEC2CM_1			0x10000000
769 #define SCCR_TSEC2CM_2			0x20000000
770 #define SCCR_TSEC2CM_3			0x30000000
771 
772 #define SCCR_SDHCCM			0x0c000000
773 #define SCCR_SDHCCM_SHIFT		26
774 #define SCCR_SDHCCM_0			0x00000000
775 #define SCCR_SDHCCM_1			0x04000000
776 #define SCCR_SDHCCM_2			0x08000000
777 #define SCCR_SDHCCM_3			0x0c000000
778 
779 #define SCCR_USBDRCM			0x00c00000
780 #define SCCR_USBDRCM_SHIFT		22
781 #define SCCR_USBDRCM_0			0x00000000
782 #define SCCR_USBDRCM_1			0x00400000
783 #define SCCR_USBDRCM_2			0x00800000
784 #define SCCR_USBDRCM_3			0x00c00000
785 
786 #define SCCR_PCIEXP1CM			0x00300000
787 #define SCCR_PCIEXP1CM_SHIFT		20
788 #define SCCR_PCIEXP1CM_0		0x00000000
789 #define SCCR_PCIEXP1CM_1		0x00100000
790 #define SCCR_PCIEXP1CM_2		0x00200000
791 #define SCCR_PCIEXP1CM_3		0x00300000
792 
793 #define SCCR_PCIEXP2CM			0x000c0000
794 #define SCCR_PCIEXP2CM_SHIFT		18
795 #define SCCR_PCIEXP2CM_0		0x00000000
796 #define SCCR_PCIEXP2CM_1		0x00040000
797 #define SCCR_PCIEXP2CM_2		0x00080000
798 #define SCCR_PCIEXP2CM_3		0x000c0000
799 
800 /* All of the four SATA controllers must have the same clock ratio */
801 #define SCCR_SATA1CM			0x000000c0
802 #define SCCR_SATA1CM_SHIFT		6
803 #define SCCR_SATACM			0x000000ff
804 #define SCCR_SATACM_SHIFT		0
805 #define SCCR_SATACM_0			0x00000000
806 #define SCCR_SATACM_1			0x00000055
807 #define SCCR_SATACM_2			0x000000aa
808 #define SCCR_SATACM_3			0x000000ff
809 #endif
810 
811 /* CSn_BDNS - Chip Select memory Bounds Register
812  */
813 #define CSBNDS_SA			0x00FF0000
814 #define CSBNDS_SA_SHIFT			8
815 #define CSBNDS_EA			0x000000FF
816 #define CSBNDS_EA_SHIFT			24
817 
818 /* CSn_CONFIG - Chip Select Configuration Register
819  */
820 #define CSCONFIG_EN			0x80000000
821 #define CSCONFIG_AP			0x00800000
822 #define CSCONFIG_ODT_WR_ACS		0x00010000
823 #define CSCONFIG_ROW_BIT		0x00000700
824 #define CSCONFIG_ROW_BIT_12		0x00000000
825 #define CSCONFIG_ROW_BIT_13		0x00000100
826 #define CSCONFIG_ROW_BIT_14		0x00000200
827 #define CSCONFIG_COL_BIT		0x00000007
828 #define CSCONFIG_COL_BIT_8		0x00000000
829 #define CSCONFIG_COL_BIT_9		0x00000001
830 #define CSCONFIG_COL_BIT_10		0x00000002
831 #define CSCONFIG_COL_BIT_11		0x00000003
832 
833 /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
834  */
835 #define TIMING_CFG0_RWT			0xC0000000
836 #define TIMING_CFG0_RWT_SHIFT		30
837 #define TIMING_CFG0_WRT			0x30000000
838 #define TIMING_CFG0_WRT_SHIFT		28
839 #define TIMING_CFG0_RRT			0x0C000000
840 #define TIMING_CFG0_RRT_SHIFT		26
841 #define TIMING_CFG0_WWT			0x03000000
842 #define TIMING_CFG0_WWT_SHIFT		24
843 #define TIMING_CFG0_ACT_PD_EXIT		0x00700000
844 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT	20
845 #define TIMING_CFG0_PRE_PD_EXIT		0x00070000
846 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT	16
847 #define TIMING_CFG0_ODT_PD_EXIT		0x00000F00
848 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT	8
849 #define TIMING_CFG0_MRS_CYC		0x0000000F
850 #define TIMING_CFG0_MRS_CYC_SHIFT	0
851 
852 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
853  */
854 #define TIMING_CFG1_PRETOACT		0x70000000
855 #define TIMING_CFG1_PRETOACT_SHIFT	28
856 #define TIMING_CFG1_ACTTOPRE		0x0F000000
857 #define TIMING_CFG1_ACTTOPRE_SHIFT	24
858 #define TIMING_CFG1_ACTTORW		0x00700000
859 #define TIMING_CFG1_ACTTORW_SHIFT	20
860 #define TIMING_CFG1_CASLAT		0x00070000
861 #define TIMING_CFG1_CASLAT_SHIFT	16
862 #define TIMING_CFG1_REFREC		0x0000F000
863 #define TIMING_CFG1_REFREC_SHIFT	12
864 #define TIMING_CFG1_WRREC		0x00000700
865 #define TIMING_CFG1_WRREC_SHIFT		8
866 #define TIMING_CFG1_ACTTOACT		0x00000070
867 #define TIMING_CFG1_ACTTOACT_SHIFT	4
868 #define TIMING_CFG1_WRTORD		0x00000007
869 #define TIMING_CFG1_WRTORD_SHIFT	0
870 #define TIMING_CFG1_CASLAT_20		0x00030000	/* CAS latency = 2.0 */
871 #define TIMING_CFG1_CASLAT_25		0x00040000	/* CAS latency = 2.5 */
872 #define TIMING_CFG1_CASLAT_30		0x00050000	/* CAS latency = 2.5 */
873 
874 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
875  */
876 #define TIMING_CFG2_CPO			0x0F800000
877 #define TIMING_CFG2_CPO_SHIFT		23
878 #define TIMING_CFG2_ACSM		0x00080000
879 #define TIMING_CFG2_WR_DATA_DELAY	0x00001C00
880 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT	10
881 #define TIMING_CFG2_CPO_DEF		0x00000000	/* default (= CASLAT + 1) */
882 
883 #define TIMING_CFG2_ADD_LAT		0x70000000
884 #define TIMING_CFG2_ADD_LAT_SHIFT	28
885 #define TIMING_CFG2_WR_LAT_DELAY	0x00380000
886 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT	19
887 #define TIMING_CFG2_RD_TO_PRE		0x0000E000
888 #define TIMING_CFG2_RD_TO_PRE_SHIFT	13
889 #define TIMING_CFG2_CKE_PLS		0x000001C0
890 #define TIMING_CFG2_CKE_PLS_SHIFT	6
891 #define TIMING_CFG2_FOUR_ACT		0x0000003F
892 #define TIMING_CFG2_FOUR_ACT_SHIFT	0
893 
894 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
895  */
896 #define SDRAM_CFG_MEM_EN		0x80000000
897 #define SDRAM_CFG_SREN			0x40000000
898 #define SDRAM_CFG_ECC_EN		0x20000000
899 #define SDRAM_CFG_RD_EN			0x10000000
900 #define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
901 #define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
902 #define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
903 #define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
904 #define SDRAM_CFG_DYN_PWR		0x00200000
905 #define SDRAM_CFG_32_BE			0x00080000
906 #define SDRAM_CFG_8_BE			0x00040000
907 #define SDRAM_CFG_NCAP			0x00020000
908 #define SDRAM_CFG_2T_EN			0x00008000
909 #define SDRAM_CFG_BI			0x00000001
910 
911 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register
912  */
913 #define SDRAM_MODE_ESD			0xFFFF0000
914 #define SDRAM_MODE_ESD_SHIFT		16
915 #define SDRAM_MODE_SD			0x0000FFFF
916 #define SDRAM_MODE_SD_SHIFT		0
917 #define DDR_MODE_EXT_MODEREG		0x4000		/* select extended mode reg */
918 #define DDR_MODE_EXT_OPMODE		0x3FF8		/* operating mode, mask */
919 #define DDR_MODE_EXT_OP_NORMAL		0x0000		/* normal operation */
920 #define DDR_MODE_QFC			0x0004		/* QFC / compatibility, mask */
921 #define DDR_MODE_QFC_COMP		0x0000		/* compatible to older SDRAMs */
922 #define DDR_MODE_WEAK			0x0002		/* weak drivers */
923 #define DDR_MODE_DLL_DIS		0x0001		/* disable DLL */
924 #define DDR_MODE_CASLAT			0x0070		/* CAS latency, mask */
925 #define DDR_MODE_CASLAT_15		0x0010		/* CAS latency 1.5 */
926 #define DDR_MODE_CASLAT_20		0x0020		/* CAS latency 2 */
927 #define DDR_MODE_CASLAT_25		0x0060		/* CAS latency 2.5 */
928 #define DDR_MODE_CASLAT_30		0x0030		/* CAS latency 3 */
929 #define DDR_MODE_BTYPE_SEQ		0x0000		/* sequential burst */
930 #define DDR_MODE_BTYPE_ILVD		0x0008		/* interleaved burst */
931 #define DDR_MODE_BLEN_2			0x0001		/* burst length 2 */
932 #define DDR_MODE_BLEN_4			0x0002		/* burst length 4 */
933 #define DDR_REFINT_166MHZ_7US		1302		/* exact value for 7.8125us */
934 #define DDR_BSTOPRE			256		/* use 256 cycles as a starting point */
935 #define DDR_MODE_MODEREG		0x0000		/* select mode register */
936 
937 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
938  */
939 #define SDRAM_INTERVAL_REFINT		0x3FFF0000
940 #define SDRAM_INTERVAL_REFINT_SHIFT	16
941 #define SDRAM_INTERVAL_BSTOPRE		0x00003FFF
942 #define SDRAM_INTERVAL_BSTOPRE_SHIFT	0
943 
944 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
945  */
946 #define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
947 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025	0x01000000
948 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
949 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075	0x03000000
950 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1		0x04000000
951 
952 /* ECC_ERR_INJECT - Memory data path error injection mask ECC
953  */
954 #define ECC_ERR_INJECT_EMB		(0x80000000>>22)	/* ECC Mirror Byte */
955 #define ECC_ERR_INJECT_EIEN		(0x80000000>>23)	/* Error Injection Enable */
956 #define ECC_ERR_INJECT_EEIM		(0xff000000>>24)	/* ECC Erroe Injection Enable */
957 #define ECC_ERR_INJECT_EEIM_SHIFT	0
958 
959 /* CAPTURE_ECC - Memory data path read capture ECC
960  */
961 #define CAPTURE_ECC_ECE			(0xff000000>>24)
962 #define CAPTURE_ECC_ECE_SHIFT		0
963 
964 /* ERR_DETECT - Memory error detect
965  */
966 #define ECC_ERROR_DETECT_MME		(0x80000000>>0)		/* Multiple Memory Errors */
967 #define ECC_ERROR_DETECT_MBE		(0x80000000>>28)	/* Multiple-Bit Error */
968 #define ECC_ERROR_DETECT_SBE		(0x80000000>>29)	/* Single-Bit ECC Error Pickup */
969 #define ECC_ERROR_DETECT_MSE		(0x80000000>>31)	/* Memory Select Error */
970 
971 /* ERR_DISABLE - Memory error disable
972  */
973 #define ECC_ERROR_DISABLE_MBED		(0x80000000>>28)	/* Multiple-Bit ECC Error Disable */
974 #define ECC_ERROR_DISABLE_SBED		(0x80000000>>29)	/* Sinle-Bit ECC Error disable */
975 #define ECC_ERROR_DISABLE_MSED		(0x80000000>>31)	/* Memory Select Error Disable */
976 #define ECC_ERROR_ENABLE		~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\
977 					 ECC_ERROR_DISABLE_MBED)
978 /* ERR_INT_EN - Memory error interrupt enable
979  */
980 #define ECC_ERR_INT_EN_MBEE		(0x80000000>>28)	/* Multiple-Bit ECC Error Interrupt Enable */
981 #define ECC_ERR_INT_EN_SBEE		(0x80000000>>29)	/* Single-Bit ECC Error Interrupt Enable */
982 #define ECC_ERR_INT_EN_MSEE		(0x80000000>>31)	/* Memory Select Error Interrupt Enable */
983 #define ECC_ERR_INT_DISABLE		~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\
984 					 ECC_ERR_INT_EN_MSEE)
985 /* CAPTURE_ATTRIBUTES - Memory error attributes capture
986  */
987 #define ECC_CAPT_ATTR_BNUM		(0xe0000000>>1)		/* Data Beat Num */
988 #define ECC_CAPT_ATTR_BNUM_SHIFT	28
989 #define ECC_CAPT_ATTR_TSIZ		(0xc0000000>>6)		/* Transaction Size */
990 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW	0
991 #define ECC_CAPT_ATTR_TSIZ_ONE_DW	1
992 #define ECC_CAPT_ATTR_TSIZ_TWO_DW	2
993 #define ECC_CAPT_ATTR_TSIZ_THREE_DW	3
994 #define ECC_CAPT_ATTR_TSIZ_SHIFT	24
995 #define ECC_CAPT_ATTR_TSRC		(0xf8000000>>11)	/* Transaction Source */
996 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT	0x0
997 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF	0x2
998 #define ECC_CAPT_ATTR_TSRC_TSEC1	0x4
999 #define ECC_CAPT_ATTR_TSRC_TSEC2	0x5
1000 #define ECC_CAPT_ATTR_TSRC_USB		(0x06|0x07)
1001 #define ECC_CAPT_ATTR_TSRC_ENCRYPT	0x8
1002 #define ECC_CAPT_ATTR_TSRC_I2C		0x9
1003 #define ECC_CAPT_ATTR_TSRC_JTAG		0xA
1004 #define ECC_CAPT_ATTR_TSRC_PCI1		0xD
1005 #define ECC_CAPT_ATTR_TSRC_PCI2		0xE
1006 #define ECC_CAPT_ATTR_TSRC_DMA		0xF
1007 #define ECC_CAPT_ATTR_TSRC_SHIFT	16
1008 #define ECC_CAPT_ATTR_TTYP		(0xe0000000>>18)	/* Transaction Type */
1009 #define ECC_CAPT_ATTR_TTYP_WRITE	0x1
1010 #define ECC_CAPT_ATTR_TTYP_READ		0x2
1011 #define ECC_CAPT_ATTR_TTYP_R_M_W	0x3
1012 #define ECC_CAPT_ATTR_TTYP_SHIFT	12
1013 #define ECC_CAPT_ATTR_VLD		(0x80000000>>31)	/* Valid */
1014 
1015 /* ERR_SBE - Single bit ECC memory error management
1016  */
1017 #define ECC_ERROR_MAN_SBET		(0xff000000>>8)		/* Single-Bit Error Threshold 0..255 */
1018 #define ECC_ERROR_MAN_SBET_SHIFT	16
1019 #define ECC_ERROR_MAN_SBEC		(0xff000000>>24)	/* Single Bit Error Counter 0..255 */
1020 #define ECC_ERROR_MAN_SBEC_SHIFT	0
1021 
1022 /* BR - Base Registers
1023  */
1024 #define BR0				0x5000		/* Register offset to immr */
1025 #define BR1				0x5008
1026 #define BR2				0x5010
1027 #define BR3				0x5018
1028 #define BR4				0x5020
1029 #define BR5				0x5028
1030 #define BR6				0x5030
1031 #define BR7				0x5038
1032 
1033 #define BR_BA				0xFFFF8000
1034 #define BR_BA_SHIFT			15
1035 #define BR_PS				0x00001800
1036 #define BR_PS_SHIFT			11
1037 #define BR_PS_8				0x00000800	/* Port Size 8 bit */
1038 #define BR_PS_16			0x00001000	/* Port Size 16 bit */
1039 #define BR_PS_32			0x00001800	/* Port Size 32 bit */
1040 #define BR_DECC				0x00000600
1041 #define BR_DECC_SHIFT			9
1042 #define BR_DECC_OFF			0x00000000
1043 #define BR_DECC_CHK			0x00000200
1044 #define BR_DECC_CHK_GEN			0x00000400
1045 #define BR_WP				0x00000100
1046 #define BR_WP_SHIFT			8
1047 #define BR_MSEL				0x000000E0
1048 #define BR_MSEL_SHIFT			5
1049 #define BR_MS_GPCM			0x00000000	/* GPCM */
1050 #define BR_MS_FCM			0x00000020	/* FCM */
1051 #define BR_MS_SDRAM			0x00000060	/* SDRAM */
1052 #define BR_MS_UPMA			0x00000080	/* UPMA */
1053 #define BR_MS_UPMB			0x000000A0	/* UPMB */
1054 #define BR_MS_UPMC			0x000000C0	/* UPMC */
1055 #if !defined(CONFIG_MPC834X)
1056 #define BR_ATOM				0x0000000C
1057 #define BR_ATOM_SHIFT			2
1058 #endif
1059 #define BR_V				0x00000001
1060 #define BR_V_SHIFT			0
1061 
1062 #if defined(CONFIG_MPC834X)
1063 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
1064 #else
1065 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
1066 #endif
1067 
1068 /* OR - Option Registers
1069  */
1070 #define OR0				0x5004		/* Register offset to immr */
1071 #define OR1				0x500C
1072 #define OR2				0x5014
1073 #define OR3				0x501C
1074 #define OR4				0x5024
1075 #define OR5				0x502C
1076 #define OR6				0x5034
1077 #define OR7				0x503C
1078 
1079 #define OR_GPCM_AM			0xFFFF8000
1080 #define OR_GPCM_AM_SHIFT		15
1081 #define OR_GPCM_BCTLD			0x00001000
1082 #define OR_GPCM_BCTLD_SHIFT		12
1083 #define OR_GPCM_CSNT			0x00000800
1084 #define OR_GPCM_CSNT_SHIFT		11
1085 #define OR_GPCM_ACS			0x00000600
1086 #define OR_GPCM_ACS_SHIFT		9
1087 #define OR_GPCM_ACS_0b10		0x00000400
1088 #define OR_GPCM_ACS_0b11		0x00000600
1089 #define OR_GPCM_XACS			0x00000100
1090 #define OR_GPCM_XACS_SHIFT		8
1091 #define OR_GPCM_SCY			0x000000F0
1092 #define OR_GPCM_SCY_SHIFT		4
1093 #define OR_GPCM_SCY_1			0x00000010
1094 #define OR_GPCM_SCY_2			0x00000020
1095 #define OR_GPCM_SCY_3			0x00000030
1096 #define OR_GPCM_SCY_4			0x00000040
1097 #define OR_GPCM_SCY_5			0x00000050
1098 #define OR_GPCM_SCY_6			0x00000060
1099 #define OR_GPCM_SCY_7			0x00000070
1100 #define OR_GPCM_SCY_8			0x00000080
1101 #define OR_GPCM_SCY_9			0x00000090
1102 #define OR_GPCM_SCY_10			0x000000a0
1103 #define OR_GPCM_SCY_11			0x000000b0
1104 #define OR_GPCM_SCY_12			0x000000c0
1105 #define OR_GPCM_SCY_13			0x000000d0
1106 #define OR_GPCM_SCY_14			0x000000e0
1107 #define OR_GPCM_SCY_15			0x000000f0
1108 #define OR_GPCM_SETA			0x00000008
1109 #define OR_GPCM_SETA_SHIFT		3
1110 #define OR_GPCM_TRLX			0x00000004
1111 #define OR_GPCM_TRLX_SHIFT		2
1112 #define OR_GPCM_EHTR			0x00000002
1113 #define OR_GPCM_EHTR_SHIFT		1
1114 #define OR_GPCM_EAD			0x00000001
1115 #define OR_GPCM_EAD_SHIFT		0
1116 
1117 #define OR_FCM_AM			0xFFFF8000
1118 #define OR_FCM_AM_SHIFT				15
1119 #define OR_FCM_BCTLD			0x00001000
1120 #define OR_FCM_BCTLD_SHIFT			12
1121 #define OR_FCM_PGS			0x00000400
1122 #define OR_FCM_PGS_SHIFT			10
1123 #define OR_FCM_CSCT			0x00000200
1124 #define OR_FCM_CSCT_SHIFT			 9
1125 #define OR_FCM_CST			0x00000100
1126 #define OR_FCM_CST_SHIFT			 8
1127 #define OR_FCM_CHT			0x00000080
1128 #define OR_FCM_CHT_SHIFT			 7
1129 #define OR_FCM_SCY			0x00000070
1130 #define OR_FCM_SCY_SHIFT			 4
1131 #define OR_FCM_SCY_1			0x00000010
1132 #define OR_FCM_SCY_2			0x00000020
1133 #define OR_FCM_SCY_3			0x00000030
1134 #define OR_FCM_SCY_4			0x00000040
1135 #define OR_FCM_SCY_5			0x00000050
1136 #define OR_FCM_SCY_6			0x00000060
1137 #define OR_FCM_SCY_7			0x00000070
1138 #define OR_FCM_RST			0x00000008
1139 #define OR_FCM_RST_SHIFT			 3
1140 #define OR_FCM_TRLX			0x00000004
1141 #define OR_FCM_TRLX_SHIFT			 2
1142 #define OR_FCM_EHTR			0x00000002
1143 #define OR_FCM_EHTR_SHIFT			 1
1144 
1145 #define OR_UPM_AM			0xFFFF8000
1146 #define OR_UPM_AM_SHIFT			15
1147 #define OR_UPM_XAM			0x00006000
1148 #define OR_UPM_XAM_SHIFT		13
1149 #define OR_UPM_BCTLD			0x00001000
1150 #define OR_UPM_BCTLD_SHIFT		12
1151 #define OR_UPM_BI			0x00000100
1152 #define OR_UPM_BI_SHIFT			8
1153 #define OR_UPM_TRLX			0x00000004
1154 #define OR_UPM_TRLX_SHIFT		2
1155 #define OR_UPM_EHTR			0x00000002
1156 #define OR_UPM_EHTR_SHIFT		1
1157 #define OR_UPM_EAD			0x00000001
1158 #define OR_UPM_EAD_SHIFT		0
1159 
1160 #define OR_SDRAM_AM			0xFFFF8000
1161 #define OR_SDRAM_AM_SHIFT		15
1162 #define OR_SDRAM_XAM			0x00006000
1163 #define OR_SDRAM_XAM_SHIFT		13
1164 #define OR_SDRAM_COLS			0x00001C00
1165 #define OR_SDRAM_COLS_SHIFT		10
1166 #define OR_SDRAM_ROWS			0x000001C0
1167 #define OR_SDRAM_ROWS_SHIFT		6
1168 #define OR_SDRAM_PMSEL			0x00000020
1169 #define OR_SDRAM_PMSEL_SHIFT		5
1170 #define OR_SDRAM_EAD			0x00000001
1171 #define OR_SDRAM_EAD_SHIFT		0
1172 
1173 #define OR_AM_32KB			0xFFFF8000
1174 #define OR_AM_64KB			0xFFFF0000
1175 #define OR_AM_128KB			0xFFFE0000
1176 #define OR_AM_256KB			0xFFFC0000
1177 #define OR_AM_512KB			0xFFF80000
1178 #define OR_AM_1MB			0xFFF00000
1179 #define OR_AM_2MB			0xFFE00000
1180 #define OR_AM_4MB			0xFFC00000
1181 #define OR_AM_8MB			0xFF800000
1182 #define OR_AM_16MB			0xFF000000
1183 #define OR_AM_32MB			0xFE000000
1184 #define OR_AM_64MB			0xFC000000
1185 #define OR_AM_128MB			0xF8000000
1186 #define OR_AM_256MB			0xF0000000
1187 #define OR_AM_512MB			0xE0000000
1188 #define OR_AM_1GB			0xC0000000
1189 #define OR_AM_2GB			0x80000000
1190 #define OR_AM_4GB			0x00000000
1191 
1192 #define LBLAWAR_EN			0x80000000
1193 #define LBLAWAR_4KB			0x0000000B
1194 #define LBLAWAR_8KB			0x0000000C
1195 #define LBLAWAR_16KB			0x0000000D
1196 #define LBLAWAR_32KB			0x0000000E
1197 #define LBLAWAR_64KB			0x0000000F
1198 #define LBLAWAR_128KB			0x00000010
1199 #define LBLAWAR_256KB			0x00000011
1200 #define LBLAWAR_512KB			0x00000012
1201 #define LBLAWAR_1MB			0x00000013
1202 #define LBLAWAR_2MB			0x00000014
1203 #define LBLAWAR_4MB			0x00000015
1204 #define LBLAWAR_8MB			0x00000016
1205 #define LBLAWAR_16MB			0x00000017
1206 #define LBLAWAR_32MB			0x00000018
1207 #define LBLAWAR_64MB			0x00000019
1208 #define LBLAWAR_128MB			0x0000001A
1209 #define LBLAWAR_256MB			0x0000001B
1210 #define LBLAWAR_512MB			0x0000001C
1211 #define LBLAWAR_1GB			0x0000001D
1212 #define LBLAWAR_2GB			0x0000001E
1213 
1214 /* LBCR - Local Bus Configuration Register
1215  */
1216 #define LBCR_LDIS			0x80000000
1217 #define LBCR_LDIS_SHIFT			31
1218 #define LBCR_BCTLC			0x00C00000
1219 #define LBCR_BCTLC_SHIFT		22
1220 #define LBCR_LPBSE			0x00020000
1221 #define LBCR_LPBSE_SHIFT		17
1222 #define LBCR_EPAR			0x00010000
1223 #define LBCR_EPAR_SHIFT			16
1224 #define LBCR_BMT			0x0000FF00
1225 #define LBCR_BMT_SHIFT			8
1226 
1227 /* LCRR - Clock Ratio Register
1228  */
1229 #define LCRR_DBYP			0x80000000
1230 #define LCRR_DBYP_SHIFT			31
1231 #define LCRR_BUFCMDC			0x30000000
1232 #define LCRR_BUFCMDC_SHIFT		28
1233 #define LCRR_BUFCMDC_1			0x10000000
1234 #define LCRR_BUFCMDC_2			0x20000000
1235 #define LCRR_BUFCMDC_3			0x30000000
1236 #define LCRR_BUFCMDC_4			0x00000000
1237 #define LCRR_ECL			0x03000000
1238 #define LCRR_ECL_SHIFT			24
1239 #define LCRR_ECL_4			0x00000000
1240 #define LCRR_ECL_5			0x01000000
1241 #define LCRR_ECL_6			0x02000000
1242 #define LCRR_ECL_7			0x03000000
1243 #define LCRR_EADC			0x00030000
1244 #define LCRR_EADC_SHIFT			16
1245 #define LCRR_EADC_1			0x00010000
1246 #define LCRR_EADC_2			0x00020000
1247 #define LCRR_EADC_3			0x00030000
1248 #define LCRR_EADC_4			0x00000000
1249 #define LCRR_CLKDIV			0x0000000F
1250 #define LCRR_CLKDIV_SHIFT		0
1251 #define LCRR_CLKDIV_2			0x00000002
1252 #define LCRR_CLKDIV_4			0x00000004
1253 #define LCRR_CLKDIV_8			0x00000008
1254 
1255 /* DMAMR - DMA Mode Register
1256  */
1257 #define DMA_CHANNEL_START			0x00000001	/* Bit - DMAMRn CS */
1258 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT	0x00000004	/* Bit - DMAMRn CTM */
1259 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN	0x00001000	/* Bit - DMAMRn SAHE */
1260 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B	0x00000000	/* 2Bit- DMAMRn SAHTS 1byte */
1261 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B	0x00004000	/* 2Bit- DMAMRn SAHTS 2bytes */
1262 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B	0x00008000	/* 2Bit- DMAMRn SAHTS 4bytes */
1263 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B	0x0000c000	/* 2Bit- DMAMRn SAHTS 8bytes */
1264 #define DMA_CHANNEL_SNOOP			0x00010000	/* Bit - DMAMRn DMSEN */
1265 
1266 /* DMASR - DMA Status Register
1267  */
1268 #define DMA_CHANNEL_BUSY			0x00000004	/* Bit - DMASRn CB */
1269 #define DMA_CHANNEL_TRANSFER_ERROR		0x00000080	/* Bit - DMASRn TE */
1270 
1271 /* CONFIG_ADDRESS - PCI Config Address Register
1272  */
1273 #define PCI_CONFIG_ADDRESS_EN		0x80000000
1274 #define PCI_CONFIG_ADDRESS_BN_SHIFT	16
1275 #define PCI_CONFIG_ADDRESS_BN_MASK	0x00ff0000
1276 #define PCI_CONFIG_ADDRESS_DN_SHIFT	11
1277 #define PCI_CONFIG_ADDRESS_DN_MASK	0x0000f800
1278 #define PCI_CONFIG_ADDRESS_FN_SHIFT	8
1279 #define PCI_CONFIG_ADDRESS_FN_MASK	0x00000700
1280 #define PCI_CONFIG_ADDRESS_RN_SHIFT	0
1281 #define PCI_CONFIG_ADDRESS_RN_MASK	0x000000fc
1282 
1283 /* POTAR - PCI Outbound Translation Address Register
1284  */
1285 #define POTAR_TA_MASK			0x000fffff
1286 
1287 /* POBAR - PCI Outbound Base Address Register
1288  */
1289 #define POBAR_BA_MASK			0x000fffff
1290 
1291 /* POCMR - PCI Outbound Comparision Mask Register
1292  */
1293 #define POCMR_EN			0x80000000
1294 #define POCMR_IO			0x40000000	/* 0-memory space 1-I/O space */
1295 #define POCMR_SE			0x20000000	/* streaming enable */
1296 #define POCMR_DST			0x10000000	/* 0-PCI1 1-PCI2 */
1297 #define POCMR_CM_MASK			0x000fffff
1298 #define POCMR_CM_4G			0x00000000
1299 #define POCMR_CM_2G			0x00080000
1300 #define POCMR_CM_1G			0x000C0000
1301 #define POCMR_CM_512M			0x000E0000
1302 #define POCMR_CM_256M			0x000F0000
1303 #define POCMR_CM_128M			0x000F8000
1304 #define POCMR_CM_64M			0x000FC000
1305 #define POCMR_CM_32M			0x000FE000
1306 #define POCMR_CM_16M			0x000FF000
1307 #define POCMR_CM_8M			0x000FF800
1308 #define POCMR_CM_4M			0x000FFC00
1309 #define POCMR_CM_2M			0x000FFE00
1310 #define POCMR_CM_1M			0x000FFF00
1311 #define POCMR_CM_512K			0x000FFF80
1312 #define POCMR_CM_256K			0x000FFFC0
1313 #define POCMR_CM_128K			0x000FFFE0
1314 #define POCMR_CM_64K			0x000FFFF0
1315 #define POCMR_CM_32K			0x000FFFF8
1316 #define POCMR_CM_16K			0x000FFFFC
1317 #define POCMR_CM_8K			0x000FFFFE
1318 #define POCMR_CM_4K			0x000FFFFF
1319 
1320 /* PITAR - PCI Inbound Translation Address Register
1321  */
1322 #define PITAR_TA_MASK			0x000fffff
1323 
1324 /* PIBAR - PCI Inbound Base/Extended Address Register
1325  */
1326 #define PIBAR_MASK			0xffffffff
1327 #define PIEBAR_EBA_MASK			0x000fffff
1328 
1329 /* PIWAR - PCI Inbound Windows Attributes Register
1330  */
1331 #define PIWAR_EN			0x80000000
1332 #define PIWAR_PF			0x20000000
1333 #define PIWAR_RTT_MASK			0x000f0000
1334 #define PIWAR_RTT_NO_SNOOP		0x00040000
1335 #define PIWAR_RTT_SNOOP			0x00050000
1336 #define PIWAR_WTT_MASK			0x0000f000
1337 #define PIWAR_WTT_NO_SNOOP		0x00004000
1338 #define PIWAR_WTT_SNOOP			0x00005000
1339 #define PIWAR_IWS_MASK			0x0000003F
1340 #define PIWAR_IWS_4K			0x0000000B
1341 #define PIWAR_IWS_8K			0x0000000C
1342 #define PIWAR_IWS_16K			0x0000000D
1343 #define PIWAR_IWS_32K			0x0000000E
1344 #define PIWAR_IWS_64K			0x0000000F
1345 #define PIWAR_IWS_128K			0x00000010
1346 #define PIWAR_IWS_256K			0x00000011
1347 #define PIWAR_IWS_512K			0x00000012
1348 #define PIWAR_IWS_1M			0x00000013
1349 #define PIWAR_IWS_2M			0x00000014
1350 #define PIWAR_IWS_4M			0x00000015
1351 #define PIWAR_IWS_8M			0x00000016
1352 #define PIWAR_IWS_16M			0x00000017
1353 #define PIWAR_IWS_32M			0x00000018
1354 #define PIWAR_IWS_64M			0x00000019
1355 #define PIWAR_IWS_128M			0x0000001A
1356 #define PIWAR_IWS_256M			0x0000001B
1357 #define PIWAR_IWS_512M			0x0000001C
1358 #define PIWAR_IWS_1G			0x0000001D
1359 #define PIWAR_IWS_2G			0x0000001E
1360 
1361 /* PMCCR1 - PCI Configuration Register 1
1362  */
1363 #define PMCCR1_POWER_OFF		0x00000020
1364 
1365 /* FMR - Flash Mode Register
1366  */
1367 #define FMR_CWTO		0x0000F000
1368 #define FMR_CWTO_SHIFT		12
1369 #define FMR_BOOT		0x00000800
1370 #define FMR_ECCM		0x00000100
1371 #define FMR_AL			0x00000030
1372 #define FMR_AL_SHIFT		4
1373 #define FMR_OP			0x00000003
1374 #define FMR_OP_SHIFT		0
1375 
1376 /* FIR - Flash Instruction Register
1377  */
1378 #define FIR_OP0			0xF0000000
1379 #define FIR_OP0_SHIFT		28
1380 #define FIR_OP1			0x0F000000
1381 #define FIR_OP1_SHIFT		24
1382 #define FIR_OP2			0x00F00000
1383 #define FIR_OP2_SHIFT		20
1384 #define FIR_OP3			0x000F0000
1385 #define FIR_OP3_SHIFT		16
1386 #define FIR_OP4			0x0000F000
1387 #define FIR_OP4_SHIFT		12
1388 #define FIR_OP5			0x00000F00
1389 #define FIR_OP5_SHIFT		8
1390 #define FIR_OP6			0x000000F0
1391 #define FIR_OP6_SHIFT		4
1392 #define FIR_OP7			0x0000000F
1393 #define FIR_OP7_SHIFT		0
1394 #define FIR_OP_NOP		0x0 /* No operation and end of sequence */
1395 #define FIR_OP_CA		0x1 /* Issue current column address */
1396 #define FIR_OP_PA		0x2 /* Issue current block+page address */
1397 #define FIR_OP_UA		0x3 /* Issue user defined address */
1398 #define FIR_OP_CM0		0x4 /* Issue command from FCR[CMD0] */
1399 #define FIR_OP_CM1		0x5 /* Issue command from FCR[CMD1] */
1400 #define FIR_OP_CM2		0x6 /* Issue command from FCR[CMD2] */
1401 #define FIR_OP_CM3		0x7 /* Issue command from FCR[CMD3] */
1402 #define FIR_OP_WB		0x8 /* Write FBCR bytes from FCM buffer */
1403 #define FIR_OP_WS		0x9 /* Write 1 or 2 bytes from MDR[AS] */
1404 #define FIR_OP_RB		0xA /* Read FBCR bytes to FCM buffer */
1405 #define FIR_OP_RS		0xB /* Read 1 or 2 bytes to MDR[AS] */
1406 #define FIR_OP_CW0		0xC /* Wait then issue FCR[CMD0] */
1407 #define FIR_OP_CW1		0xD /* Wait then issue FCR[CMD1] */
1408 #define FIR_OP_RBW		0xE /* Wait then read FBCR bytes */
1409 #define FIR_OP_RSW		0xF /* Wait then read 1 or 2 bytes */
1410 
1411 /* FCR - Flash Command Register
1412  */
1413 #define FCR_CMD0		0xFF000000
1414 #define FCR_CMD0_SHIFT		24
1415 #define FCR_CMD1		0x00FF0000
1416 #define FCR_CMD1_SHIFT		16
1417 #define FCR_CMD2		0x0000FF00
1418 #define FCR_CMD2_SHIFT		8
1419 #define FCR_CMD3		0x000000FF
1420 #define FCR_CMD3_SHIFT		0
1421 
1422 /* FBAR - Flash Block Address Register
1423  */
1424 #define FBAR_BLK		0x00FFFFFF
1425 
1426 /* FPAR - Flash Page Address Register
1427  */
1428 #define FPAR_SP_PI		0x00007C00
1429 #define FPAR_SP_PI_SHIFT	10
1430 #define FPAR_SP_MS		0x00000200
1431 #define FPAR_SP_CI		0x000001FF
1432 #define FPAR_SP_CI_SHIFT	0
1433 #define FPAR_LP_PI		0x0003F000
1434 #define FPAR_LP_PI_SHIFT	12
1435 #define FPAR_LP_MS		0x00000800
1436 #define FPAR_LP_CI		0x000007FF
1437 #define FPAR_LP_CI_SHIFT	0
1438 
1439 /* LTESR - Transfer Error Status Register
1440  */
1441 #define LTESR_BM		0x80000000
1442 #define LTESR_FCT		0x40000000
1443 #define LTESR_PAR		0x20000000
1444 #define LTESR_WP		0x04000000
1445 #define LTESR_ATMW		0x00800000
1446 #define LTESR_ATMR		0x00400000
1447 #define LTESR_CS		0x00080000
1448 #define LTESR_CC		0x00000001
1449 
1450 /* DDRCDR - DDR Control Driver Register
1451  */
1452 #define DDRCDR_DHC_EN		0x80000000
1453 #define DDRCDR_EN		0x40000000
1454 #define DDRCDR_PZ		0x3C000000
1455 #define DDRCDR_PZ_MAXZ		0x00000000
1456 #define DDRCDR_PZ_HIZ		0x20000000
1457 #define DDRCDR_PZ_NOMZ		0x30000000
1458 #define DDRCDR_PZ_LOZ		0x38000000
1459 #define DDRCDR_PZ_MINZ		0x3C000000
1460 #define DDRCDR_NZ		0x3C000000
1461 #define DDRCDR_NZ_MAXZ		0x00000000
1462 #define DDRCDR_NZ_HIZ		0x02000000
1463 #define DDRCDR_NZ_NOMZ		0x03000000
1464 #define DDRCDR_NZ_LOZ		0x03800000
1465 #define DDRCDR_NZ_MINZ		0x03C00000
1466 #define DDRCDR_ODT		0x00080000
1467 #define DDRCDR_DDR_CFG		0x00040000
1468 #define DDRCDR_M_ODR		0x00000002
1469 #define DDRCDR_Q_DRN		0x00000001
1470 
1471 #ifndef __ASSEMBLY__
1472 struct pci_region;
1473 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot);
1474 #endif
1475 
1476 #endif	/* __MPC83XX_H__ */
1477