1 /* 2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #ifndef __MPC83XX_H__ 14 #define __MPC83XX_H__ 15 16 #include <config.h> 17 #if defined(CONFIG_E300) 18 #include <asm/e300.h> 19 #endif 20 21 /* MPC83xx cpu provide RCR register to do reset thing specially 22 */ 23 #define MPC83xx_RESET 24 25 /* System reset offset (PowerPC standard) 26 */ 27 #define EXC_OFF_SYS_RESET 0x0100 28 #define _START_OFFSET EXC_OFF_SYS_RESET 29 30 /* IMMRBAR - Internal Memory Register Base Address 31 */ 32 #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 33 #define IMMRBAR 0x0000 /* Register offset to immr */ 34 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 35 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 36 37 /* LAWBAR - Local Access Window Base Address Register 38 */ 39 #define LBLAWBAR0 0x0020 /* Register offset to immr */ 40 #define LBLAWAR0 0x0024 41 #define LBLAWBAR1 0x0028 42 #define LBLAWAR1 0x002C 43 #define LBLAWBAR2 0x0030 44 #define LBLAWAR2 0x0034 45 #define LBLAWBAR3 0x0038 46 #define LBLAWAR3 0x003C 47 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 48 49 /* SPRIDR - System Part and Revision ID Register 50 */ 51 #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ 52 #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ 53 54 #define SPR_8349E_REV10 0x80300100 55 #define SPR_8349_REV10 0x80310100 56 #define SPR_8347E_REV10_TBGA 0x80320100 57 #define SPR_8347_REV10_TBGA 0x80330100 58 #define SPR_8347E_REV10_PBGA 0x80340100 59 #define SPR_8347_REV10_PBGA 0x80350100 60 #define SPR_8343E_REV10 0x80360100 61 #define SPR_8343_REV10 0x80370100 62 63 #define SPR_8349E_REV11 0x80300101 64 #define SPR_8349_REV11 0x80310101 65 #define SPR_8347E_REV11_TBGA 0x80320101 66 #define SPR_8347_REV11_TBGA 0x80330101 67 #define SPR_8347E_REV11_PBGA 0x80340101 68 #define SPR_8347_REV11_PBGA 0x80350101 69 #define SPR_8343E_REV11 0x80360101 70 #define SPR_8343_REV11 0x80370101 71 72 #define SPR_8349E_REV31 0x80300300 73 #define SPR_8349_REV31 0x80310300 74 #define SPR_8347E_REV31_TBGA 0x80320300 75 #define SPR_8347_REV31_TBGA 0x80330300 76 #define SPR_8347E_REV31_PBGA 0x80340300 77 #define SPR_8347_REV31_PBGA 0x80350300 78 #define SPR_8343E_REV31 0x80360300 79 #define SPR_8343_REV31 0x80370300 80 81 #define SPR_8360E_REV10 0x80480010 82 #define SPR_8360_REV10 0x80490010 83 #define SPR_8360E_REV11 0x80480011 84 #define SPR_8360_REV11 0x80490011 85 #define SPR_8360E_REV12 0x80480012 86 #define SPR_8360_REV12 0x80490012 87 #define SPR_8360E_REV20 0x80480020 88 #define SPR_8360_REV20 0x80490020 89 #define SPR_8360E_REV21 0x80480021 90 #define SPR_8360_REV21 0x80490021 91 92 #define SPR_8323E_REV10 0x80620010 93 #define SPR_8323_REV10 0x80630010 94 #define SPR_8321E_REV10 0x80660010 95 #define SPR_8321_REV10 0x80670010 96 #define SPR_8323E_REV11 0x80620011 97 #define SPR_8323_REV11 0x80630011 98 #define SPR_8321E_REV11 0x80660011 99 #define SPR_8321_REV11 0x80670011 100 101 #define SPR_8311_REV10 0x80B30010 102 #define SPR_8311E_REV10 0x80B20010 103 #define SPR_8313_REV10 0x80B10010 104 #define SPR_8313E_REV10 0x80B00010 105 106 /* SPCR - System Priority Configuration Register 107 */ 108 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 109 #define SPCR_PCIHPE_SHIFT (31-3) 110 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 111 #define SPCR_PCIPR_SHIFT (31-7) 112 #define SPCR_OPT 0x00800000 /* Optimize */ 113 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 114 #define SPCR_TBEN_SHIFT (31-9) 115 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 116 #define SPCR_COREPR_SHIFT (31-11) 117 118 #if defined(CONFIG_MPC834X) 119 /* SPCR bits - MPC8349 specific */ 120 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 121 #define SPCR_TSEC1DP_SHIFT (31-19) 122 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 123 #define SPCR_TSEC1BDP_SHIFT (31-21) 124 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 125 #define SPCR_TSEC1EP_SHIFT (31-23) 126 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 127 #define SPCR_TSEC2DP_SHIFT (31-27) 128 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 129 #define SPCR_TSEC2BDP_SHIFT (31-29) 130 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 131 #define SPCR_TSEC2EP_SHIFT (31-31) 132 133 #elif defined(CONFIG_MPC831X) 134 /* SPCR bits - MPC831x specific */ 135 #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 136 #define SPCR_TSECDP_SHIFT (31-19) 137 #define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */ 138 #define SPCR_TSECEP_SHIFT (31-21) 139 #define SPCR_TSECBDP 0x00000300 /* TSEC buffer descriptor priority */ 140 #define SPCR_TSECBDP_SHIFT (31-23) 141 #endif 142 143 /* SICRL/H - System I/O Configuration Register Low/High 144 */ 145 #if defined(CONFIG_MPC834X) 146 /* SICRL bits - MPC8349 specific */ 147 #define SICRL_LDP_A 0x80000000 148 #define SICRL_USB1 0x40000000 149 #define SICRL_USB0 0x20000000 150 #define SICRL_UART 0x0C000000 151 #define SICRL_GPIO1_A 0x02000000 152 #define SICRL_GPIO1_B 0x01000000 153 #define SICRL_GPIO1_C 0x00800000 154 #define SICRL_GPIO1_D 0x00400000 155 #define SICRL_GPIO1_E 0x00200000 156 #define SICRL_GPIO1_F 0x00180000 157 #define SICRL_GPIO1_G 0x00040000 158 #define SICRL_GPIO1_H 0x00020000 159 #define SICRL_GPIO1_I 0x00010000 160 #define SICRL_GPIO1_J 0x00008000 161 #define SICRL_GPIO1_K 0x00004000 162 #define SICRL_GPIO1_L 0x00003000 163 164 /* SICRH bits - MPC8349 specific */ 165 #define SICRH_DDR 0x80000000 166 #define SICRH_TSEC1_A 0x10000000 167 #define SICRH_TSEC1_B 0x08000000 168 #define SICRH_TSEC1_C 0x04000000 169 #define SICRH_TSEC1_D 0x02000000 170 #define SICRH_TSEC1_E 0x01000000 171 #define SICRH_TSEC1_F 0x00800000 172 #define SICRH_TSEC2_A 0x00400000 173 #define SICRH_TSEC2_B 0x00200000 174 #define SICRH_TSEC2_C 0x00100000 175 #define SICRH_TSEC2_D 0x00080000 176 #define SICRH_TSEC2_E 0x00040000 177 #define SICRH_TSEC2_F 0x00020000 178 #define SICRH_TSEC2_G 0x00010000 179 #define SICRH_TSEC2_H 0x00008000 180 #define SICRH_GPIO2_A 0x00004000 181 #define SICRH_GPIO2_B 0x00002000 182 #define SICRH_GPIO2_C 0x00001000 183 #define SICRH_GPIO2_D 0x00000800 184 #define SICRH_GPIO2_E 0x00000400 185 #define SICRH_GPIO2_F 0x00000200 186 #define SICRH_GPIO2_G 0x00000180 187 #define SICRH_GPIO2_H 0x00000060 188 #define SICRH_TSOBI1 0x00000002 189 #define SICRH_TSOBI2 0x00000001 190 191 #elif defined(CONFIG_MPC8360) 192 /* SICRL bits - MPC8360 specific */ 193 #define SICRL_LDP_A 0xC0000000 194 #define SICRL_LCLK_1 0x10000000 195 #define SICRL_LCLK_2 0x08000000 196 #define SICRL_SRCID_A 0x03000000 197 #define SICRL_IRQ_CKSTP_A 0x00C00000 198 199 /* SICRH bits - MPC8360 specific */ 200 #define SICRH_DDR 0x80000000 201 #define SICRH_SECONDARY_DDR 0x40000000 202 #define SICRH_SDDROE 0x20000000 203 #define SICRH_IRQ3 0x10000000 204 #define SICRH_UC1EOBI 0x00000004 205 #define SICRH_UC2E1OBI 0x00000002 206 #define SICRH_UC2E2OBI 0x00000001 207 208 #elif defined(CONFIG_MPC832X) 209 /* SICRL bits - MPC832X specific */ 210 #define SICRL_LDP_LCS_A 0x80000000 211 #define SICRL_IRQ_CKS 0x20000000 212 #define SICRL_PCI_MSRC 0x10000000 213 #define SICRL_URT_CTPR 0x06000000 214 #define SICRL_IRQ_CTPR 0x00C00000 215 216 #elif defined(CONFIG_MPC831X) 217 /* SICRL bits - MPC831x specific */ 218 #define SICRL_LBC 0x30000000 219 #define SICRL_UART 0x0C000000 220 #define SICRL_SPI_A 0x03000000 221 #define SICRL_SPI_B 0x00C00000 222 #define SICRL_SPI_C 0x00300000 223 #define SICRL_SPI_D 0x000C0000 224 #define SICRL_USBDR 0x00000C00 225 #define SICRL_ETSEC1_A 0x0000000C 226 #define SICRL_ETSEC2_A 0x00000003 227 228 /* SICRH bits - MPC831x specific */ 229 #define SICRH_INTR_A 0x02000000 230 #define SICRH_INTR_B 0x00C00000 231 #define SICRH_IIC 0x00300000 232 #define SICRH_ETSEC2_B 0x000C0000 233 #define SICRH_ETSEC2_C 0x00030000 234 #define SICRH_ETSEC2_D 0x0000C000 235 #define SICRH_ETSEC2_E 0x00003000 236 #define SICRH_ETSEC2_F 0x00000C00 237 #define SICRH_ETSEC2_G 0x00000300 238 #define SICRH_ETSEC1_B 0x00000080 239 #define SICRH_ETSEC1_C 0x00000060 240 #define SICRH_GTX1_DLY 0x00000008 241 #define SICRH_GTX2_DLY 0x00000004 242 #define SICRH_TSOBI1 0x00000002 243 #define SICRH_TSOBI2 0x00000001 244 245 #endif 246 247 /* SWCRR - System Watchdog Control Register 248 */ 249 #define SWCRR 0x0204 /* Register offset to immr */ 250 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 251 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 252 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 253 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 254 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 255 256 /* SWCNR - System Watchdog Counter Register 257 */ 258 #define SWCNR 0x0208 /* Register offset to immr */ 259 #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 260 #define SWCNR_RES ~(SWCNR_SWCN) 261 262 /* SWSRR - System Watchdog Service Register 263 */ 264 #define SWSRR 0x020E /* Register offset to immr */ 265 266 /* ACR - Arbiter Configuration Register 267 */ 268 #define ACR_COREDIS 0x10000000 /* Core disable */ 269 #define ACR_COREDIS_SHIFT (31-7) 270 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 271 #define ACR_PIPE_DEP_SHIFT (31-15) 272 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 273 #define ACR_PCI_RPTCNT_SHIFT (31-19) 274 #define ACR_RPTCNT 0x00000700 /* Repeat count */ 275 #define ACR_RPTCNT_SHIFT (31-23) 276 #define ACR_APARK 0x00000030 /* Address parking */ 277 #define ACR_APARK_SHIFT (31-27) 278 #define ACR_PARKM 0x0000000F /* Parking master */ 279 #define ACR_PARKM_SHIFT (31-31) 280 281 /* ATR - Arbiter Timers Register 282 */ 283 #define ATR_DTO 0x00FF0000 /* Data time out */ 284 #define ATR_ATO 0x000000FF /* Address time out */ 285 286 /* AER - Arbiter Event Register 287 */ 288 #define AER_ETEA 0x00000020 /* Transfer error */ 289 #define AER_RES 0x00000010 /* Reserved transfer type */ 290 #define AER_ECW 0x00000008 /* External control word transfer type */ 291 #define AER_AO 0x00000004 /* Address Only transfer type */ 292 #define AER_DTO 0x00000002 /* Data time out */ 293 #define AER_ATO 0x00000001 /* Address time out */ 294 295 /* AEATR - Arbiter Event Address Register 296 */ 297 #define AEATR_EVENT 0x07000000 /* Event type */ 298 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 299 #define AEATR_TBST 0x00000800 /* Transfer burst */ 300 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 301 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 302 303 /* HRCWL - Hard Reset Configuration Word Low 304 */ 305 #define HRCWL_LBIUCM 0x80000000 306 #define HRCWL_LBIUCM_SHIFT 31 307 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 308 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 309 310 #define HRCWL_DDRCM 0x40000000 311 #define HRCWL_DDRCM_SHIFT 30 312 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 313 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 314 315 #define HRCWL_SPMF 0x0f000000 316 #define HRCWL_SPMF_SHIFT 24 317 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 318 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 319 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 320 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 321 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 322 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 323 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 324 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 325 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 326 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 327 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 328 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 329 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 330 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 331 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 332 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 333 334 #define HRCWL_VCO_BYPASS 0x00000000 335 #define HRCWL_VCO_1X2 0x00000000 336 #define HRCWL_VCO_1X4 0x00200000 337 #define HRCWL_VCO_1X8 0x00400000 338 339 #define HRCWL_COREPLL 0x007F0000 340 #define HRCWL_COREPLL_SHIFT 16 341 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 342 #define HRCWL_CORE_TO_CSB_1X1 0x00020000 343 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 344 #define HRCWL_CORE_TO_CSB_2X1 0x00040000 345 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 346 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 347 348 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 349 #define HRCWL_CEVCOD 0x000000C0 350 #define HRCWL_CEVCOD_SHIFT 6 351 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 352 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 353 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 354 355 #define HRCWL_CEPDF 0x00000020 356 #define HRCWL_CEPDF_SHIFT 5 357 #define HRCWL_CE_PLL_DIV_1X1 0x00000000 358 #define HRCWL_CE_PLL_DIV_2X1 0x00000020 359 360 #define HRCWL_CEPMF 0x0000001F 361 #define HRCWL_CEPMF_SHIFT 0 362 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 363 #define HRCWL_CE_TO_PLL_1X2 0x00000002 364 #define HRCWL_CE_TO_PLL_1X3 0x00000003 365 #define HRCWL_CE_TO_PLL_1X4 0x00000004 366 #define HRCWL_CE_TO_PLL_1X5 0x00000005 367 #define HRCWL_CE_TO_PLL_1X6 0x00000006 368 #define HRCWL_CE_TO_PLL_1X7 0x00000007 369 #define HRCWL_CE_TO_PLL_1X8 0x00000008 370 #define HRCWL_CE_TO_PLL_1X9 0x00000009 371 #define HRCWL_CE_TO_PLL_1X10 0x0000000A 372 #define HRCWL_CE_TO_PLL_1X11 0x0000000B 373 #define HRCWL_CE_TO_PLL_1X12 0x0000000C 374 #define HRCWL_CE_TO_PLL_1X13 0x0000000D 375 #define HRCWL_CE_TO_PLL_1X14 0x0000000E 376 #define HRCWL_CE_TO_PLL_1X15 0x0000000F 377 #define HRCWL_CE_TO_PLL_1X16 0x00000010 378 #define HRCWL_CE_TO_PLL_1X17 0x00000011 379 #define HRCWL_CE_TO_PLL_1X18 0x00000012 380 #define HRCWL_CE_TO_PLL_1X19 0x00000013 381 #define HRCWL_CE_TO_PLL_1X20 0x00000014 382 #define HRCWL_CE_TO_PLL_1X21 0x00000015 383 #define HRCWL_CE_TO_PLL_1X22 0x00000016 384 #define HRCWL_CE_TO_PLL_1X23 0x00000017 385 #define HRCWL_CE_TO_PLL_1X24 0x00000018 386 #define HRCWL_CE_TO_PLL_1X25 0x00000019 387 #define HRCWL_CE_TO_PLL_1X26 0x0000001A 388 #define HRCWL_CE_TO_PLL_1X27 0x0000001B 389 #define HRCWL_CE_TO_PLL_1X28 0x0000001C 390 #define HRCWL_CE_TO_PLL_1X29 0x0000001D 391 #define HRCWL_CE_TO_PLL_1X30 0x0000001E 392 #define HRCWL_CE_TO_PLL_1X31 0x0000001F 393 #endif 394 395 /* HRCWH - Hardware Reset Configuration Word High 396 */ 397 #define HRCWH_PCI_HOST 0x80000000 398 #define HRCWH_PCI_HOST_SHIFT 31 399 #define HRCWH_PCI_AGENT 0x00000000 400 401 #if defined(CONFIG_MPC834X) 402 #define HRCWH_32_BIT_PCI 0x00000000 403 #define HRCWH_64_BIT_PCI 0x40000000 404 #endif 405 406 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 407 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 408 409 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 410 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 411 412 #if defined(CONFIG_MPC834X) 413 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 414 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 415 416 #elif defined(CONFIG_MPC8360) 417 #define HRCWH_PCICKDRV_DISABLE 0x00000000 418 #define HRCWH_PCICKDRV_ENABLE 0x10000000 419 #endif 420 421 #define HRCWH_CORE_DISABLE 0x08000000 422 #define HRCWH_CORE_ENABLE 0x00000000 423 424 #define HRCWH_FROM_0X00000100 0x00000000 425 #define HRCWH_FROM_0XFFF00100 0x04000000 426 427 #define HRCWH_BOOTSEQ_DISABLE 0x00000000 428 #define HRCWH_BOOTSEQ_NORMAL 0x01000000 429 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 430 431 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 432 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 433 434 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 435 #define HRCWH_ROM_LOC_PCI1 0x00100000 436 #if defined(CONFIG_MPC834X) 437 #define HRCWH_ROM_LOC_PCI2 0x00200000 438 #endif 439 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 440 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 441 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 442 443 #if defined(CONFIG_MPC831X) 444 #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 445 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 446 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 447 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 448 449 #define HRCWH_RL_EXT_LEGACY 0x00000000 450 #define HRCWH_RL_EXT_NAND 0x00040000 451 452 #define HRCWH_TSEC1M_IN_MII 0x00000000 453 #define HRCWH_TSEC1M_IN_RMII 0x00002000 454 #define HRCWH_TSEC1M_IN_RGMII 0x00006000 455 #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 456 #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 457 458 #define HRCWH_TSEC2M_IN_MII 0x00000000 459 #define HRCWH_TSEC2M_IN_RMII 0x00000400 460 #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 461 #define HRCWH_TSEC2M_IN_RTBI 0x00001400 462 #define HRCWH_TSEC2M_IN_SGMII 0x00001800 463 #endif 464 465 #if defined(CONFIG_MPC834X) 466 #define HRCWH_TSEC1M_IN_RGMII 0x00000000 467 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 468 #define HRCWH_TSEC1M_IN_GMII 0x00008000 469 #define HRCWH_TSEC1M_IN_TBI 0x0000C000 470 #define HRCWH_TSEC2M_IN_RGMII 0x00000000 471 #define HRCWH_TSEC2M_IN_RTBI 0x00001000 472 #define HRCWH_TSEC2M_IN_GMII 0x00002000 473 #define HRCWH_TSEC2M_IN_TBI 0x00003000 474 #endif 475 476 #if defined(CONFIG_MPC8360) 477 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 478 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 479 #endif 480 481 #define HRCWH_BIG_ENDIAN 0x00000000 482 #define HRCWH_LITTLE_ENDIAN 0x00000008 483 484 #define HRCWH_LALE_NORMAL 0x00000000 485 #define HRCWH_LALE_EARLY 0x00000004 486 487 #define HRCWH_LDP_SET 0x00000000 488 #define HRCWH_LDP_CLEAR 0x00000002 489 490 /* RSR - Reset Status Register 491 */ 492 #define RSR_RSTSRC 0xE0000000 /* Reset source */ 493 #define RSR_RSTSRC_SHIFT 29 494 #define RSR_BSF 0x00010000 /* Boot seq. fail */ 495 #define RSR_BSF_SHIFT 16 496 #define RSR_SWSR 0x00002000 /* software soft reset */ 497 #define RSR_SWSR_SHIFT 13 498 #define RSR_SWHR 0x00001000 /* software hard reset */ 499 #define RSR_SWHR_SHIFT 12 500 #define RSR_JHRS 0x00000200 /* jtag hreset */ 501 #define RSR_JHRS_SHIFT 9 502 #define RSR_JSRS 0x00000100 /* jtag sreset status */ 503 #define RSR_JSRS_SHIFT 8 504 #define RSR_CSHR 0x00000010 /* checkstop reset status */ 505 #define RSR_CSHR_SHIFT 4 506 #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 507 #define RSR_SWRS_SHIFT 3 508 #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 509 #define RSR_BMRS_SHIFT 2 510 #define RSR_SRS 0x00000002 /* soft reset status */ 511 #define RSR_SRS_SHIFT 1 512 #define RSR_HRS 0x00000001 /* hard reset status */ 513 #define RSR_HRS_SHIFT 0 514 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 515 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 516 RSR_BMRS | RSR_SRS | RSR_HRS) 517 /* RMR - Reset Mode Register 518 */ 519 #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 520 #define RMR_CSRE_SHIFT 0 521 #define RMR_RES ~(RMR_CSRE) 522 523 /* RCR - Reset Control Register 524 */ 525 #define RCR_SWHR 0x00000002 /* software hard reset */ 526 #define RCR_SWSR 0x00000001 /* software soft reset */ 527 #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 528 529 /* RCER - Reset Control Enable Register 530 */ 531 #define RCER_CRE 0x00000001 /* software hard reset */ 532 #define RCER_RES ~(RCER_CRE) 533 534 /* SPMR - System PLL Mode Register 535 */ 536 #define SPMR_LBIUCM 0x80000000 537 #define SPMR_DDRCM 0x40000000 538 #define SPMR_SPMF 0x0F000000 539 #define SPMR_CKID 0x00800000 540 #define SPMR_CKID_SHIFT 23 541 #define SPMR_COREPLL 0x007F0000 542 #define SPMR_CEVCOD 0x000000C0 543 #define SPMR_CEPDF 0x00000020 544 #define SPMR_CEPMF 0x0000001F 545 546 /* OCCR - Output Clock Control Register 547 */ 548 #define OCCR_PCICOE0 0x80000000 549 #define OCCR_PCICOE1 0x40000000 550 #define OCCR_PCICOE2 0x20000000 551 #define OCCR_PCICOE3 0x10000000 552 #define OCCR_PCICOE4 0x08000000 553 #define OCCR_PCICOE5 0x04000000 554 #define OCCR_PCICOE6 0x02000000 555 #define OCCR_PCICOE7 0x01000000 556 #define OCCR_PCICD0 0x00800000 557 #define OCCR_PCICD1 0x00400000 558 #define OCCR_PCICD2 0x00200000 559 #define OCCR_PCICD3 0x00100000 560 #define OCCR_PCICD4 0x00080000 561 #define OCCR_PCICD5 0x00040000 562 #define OCCR_PCICD6 0x00020000 563 #define OCCR_PCICD7 0x00010000 564 #define OCCR_PCI1CR 0x00000002 565 #define OCCR_PCI2CR 0x00000001 566 #define OCCR_PCICR OCCR_PCI1CR 567 568 /* SCCR - System Clock Control Register 569 */ 570 #define SCCR_ENCCM 0x03000000 571 #define SCCR_ENCCM_SHIFT 24 572 #define SCCR_ENCCM_0 0x00000000 573 #define SCCR_ENCCM_1 0x01000000 574 #define SCCR_ENCCM_2 0x02000000 575 #define SCCR_ENCCM_3 0x03000000 576 577 #define SCCR_PCICM 0x00010000 578 #define SCCR_PCICM_SHIFT 16 579 580 /* SCCR bits - MPC8349 specific */ 581 #ifdef CONFIG_MPC834X 582 #define SCCR_TSEC1CM 0xc0000000 583 #define SCCR_TSEC1CM_SHIFT 30 584 #define SCCR_TSEC1CM_0 0x00000000 585 #define SCCR_TSEC1CM_1 0x40000000 586 #define SCCR_TSEC1CM_2 0x80000000 587 #define SCCR_TSEC1CM_3 0xC0000000 588 589 #define SCCR_TSEC2CM 0x30000000 590 #define SCCR_TSEC2CM_SHIFT 28 591 #define SCCR_TSEC2CM_0 0x00000000 592 #define SCCR_TSEC2CM_1 0x10000000 593 #define SCCR_TSEC2CM_2 0x20000000 594 #define SCCR_TSEC2CM_3 0x30000000 595 596 #elif defined(CONFIG_MPC831X) 597 /* TSEC1 bits are for TSEC2 as well */ 598 #define SCCR_TSEC1CM 0xc0000000 599 #define SCCR_TSEC1CM_SHIFT 30 600 #define SCCR_TSEC1CM_1 0x40000000 601 #define SCCR_TSEC1CM_2 0x80000000 602 #define SCCR_TSEC1CM_3 0xC0000000 603 604 #define SCCR_TSEC1ON 0x20000000 605 #define SCCR_TSEC1ON_SHIFT 29 606 #define SCCR_TSEC2ON 0x10000000 607 #define SCCR_TSEC2ON_SHIFT 28 608 609 #endif 610 611 #define SCCR_USBMPHCM 0x00c00000 612 #define SCCR_USBMPHCM_SHIFT 22 613 #define SCCR_USBDRCM 0x00300000 614 #define SCCR_USBDRCM_SHIFT 20 615 616 #define SCCR_USBCM_0 0x00000000 617 #define SCCR_USBCM_1 0x00500000 618 #define SCCR_USBCM_2 0x00A00000 619 #define SCCR_USBCM_3 0x00F00000 620 621 /* CSn_BDNS - Chip Select memory Bounds Register 622 */ 623 #define CSBNDS_SA 0x00FF0000 624 #define CSBNDS_SA_SHIFT 8 625 #define CSBNDS_EA 0x000000FF 626 #define CSBNDS_EA_SHIFT 24 627 628 /* CSn_CONFIG - Chip Select Configuration Register 629 */ 630 #define CSCONFIG_EN 0x80000000 631 #define CSCONFIG_AP 0x00800000 632 #define CSCONFIG_ROW_BIT 0x00000700 633 #define CSCONFIG_ROW_BIT_12 0x00000000 634 #define CSCONFIG_ROW_BIT_13 0x00000100 635 #define CSCONFIG_ROW_BIT_14 0x00000200 636 #define CSCONFIG_COL_BIT 0x00000007 637 #define CSCONFIG_COL_BIT_8 0x00000000 638 #define CSCONFIG_COL_BIT_9 0x00000001 639 #define CSCONFIG_COL_BIT_10 0x00000002 640 #define CSCONFIG_COL_BIT_11 0x00000003 641 642 /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 643 */ 644 #define TIMING_CFG0_RWT 0xC0000000 645 #define TIMING_CFG0_RWT_SHIFT 30 646 #define TIMING_CFG0_WRT 0x30000000 647 #define TIMING_CFG0_WRT_SHIFT 28 648 #define TIMING_CFG0_RRT 0x0C000000 649 #define TIMING_CFG0_RRT_SHIFT 26 650 #define TIMING_CFG0_WWT 0x03000000 651 #define TIMING_CFG0_WWT_SHIFT 24 652 #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 653 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 654 #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 655 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 656 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 657 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 658 #define TIMING_CFG0_MRS_CYC 0x00000F00 659 #define TIMING_CFG0_MRS_CYC_SHIFT 0 660 661 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 662 */ 663 #define TIMING_CFG1_PRETOACT 0x70000000 664 #define TIMING_CFG1_PRETOACT_SHIFT 28 665 #define TIMING_CFG1_ACTTOPRE 0x0F000000 666 #define TIMING_CFG1_ACTTOPRE_SHIFT 24 667 #define TIMING_CFG1_ACTTORW 0x00700000 668 #define TIMING_CFG1_ACTTORW_SHIFT 20 669 #define TIMING_CFG1_CASLAT 0x00070000 670 #define TIMING_CFG1_CASLAT_SHIFT 16 671 #define TIMING_CFG1_REFREC 0x0000F000 672 #define TIMING_CFG1_REFREC_SHIFT 12 673 #define TIMING_CFG1_WRREC 0x00000700 674 #define TIMING_CFG1_WRREC_SHIFT 8 675 #define TIMING_CFG1_ACTTOACT 0x00000070 676 #define TIMING_CFG1_ACTTOACT_SHIFT 4 677 #define TIMING_CFG1_WRTORD 0x00000007 678 #define TIMING_CFG1_WRTORD_SHIFT 0 679 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 680 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 681 682 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 683 */ 684 #define TIMING_CFG2_CPO 0x0F800000 685 #define TIMING_CFG2_CPO_SHIFT 23 686 #define TIMING_CFG2_ACSM 0x00080000 687 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 688 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 689 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 690 691 #define TIMING_CFG2_ADD_LAT 0x70000000 692 #define TIMING_CFG2_ADD_LAT_SHIFT 28 693 #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 694 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 695 #define TIMING_CFG2_RD_TO_PRE 0x0000E000 696 #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 697 #define TIMING_CFG2_CKE_PLS 0x000001C0 698 #define TIMING_CFG2_CKE_PLS_SHIFT 6 699 #define TIMING_CFG2_FOUR_ACT 0x0000003F 700 #define TIMING_CFG2_FOUR_ACT_SHIFT 0 701 702 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 703 */ 704 #define SDRAM_CFG_MEM_EN 0x80000000 705 #define SDRAM_CFG_SREN 0x40000000 706 #define SDRAM_CFG_ECC_EN 0x20000000 707 #define SDRAM_CFG_RD_EN 0x10000000 708 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 709 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 710 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 711 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 712 #define SDRAM_CFG_DYN_PWR 0x00200000 713 #define SDRAM_CFG_32_BE 0x00080000 714 #define SDRAM_CFG_8_BE 0x00040000 715 #define SDRAM_CFG_NCAP 0x00020000 716 #define SDRAM_CFG_2T_EN 0x00008000 717 #define SDRAM_CFG_BI 0x00000001 718 719 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 720 */ 721 #define SDRAM_MODE_ESD 0xFFFF0000 722 #define SDRAM_MODE_ESD_SHIFT 16 723 #define SDRAM_MODE_SD 0x0000FFFF 724 #define SDRAM_MODE_SD_SHIFT 0 725 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 726 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 727 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 728 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 729 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 730 #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 731 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 732 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 733 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 734 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 735 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 736 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 737 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 738 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 739 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 740 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 741 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 742 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 743 #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 744 745 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 746 */ 747 #define SDRAM_INTERVAL_REFINT 0x3FFF0000 748 #define SDRAM_INTERVAL_REFINT_SHIFT 16 749 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 750 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 751 752 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 753 */ 754 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 755 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 756 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 757 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 758 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 759 760 /* ECC_ERR_INJECT - Memory data path error injection mask ECC 761 */ 762 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 763 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 764 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 765 #define ECC_ERR_INJECT_EEIM_SHIFT 0 766 767 /* CAPTURE_ECC - Memory data path read capture ECC 768 */ 769 #define CAPTURE_ECC_ECE (0xff000000>>24) 770 #define CAPTURE_ECC_ECE_SHIFT 0 771 772 /* ERR_DETECT - Memory error detect 773 */ 774 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 775 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 776 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 777 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 778 779 /* ERR_DISABLE - Memory error disable 780 */ 781 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 782 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 783 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 784 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 785 ECC_ERROR_DISABLE_MBED) 786 /* ERR_INT_EN - Memory error interrupt enable 787 */ 788 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 789 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 790 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 791 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 792 ECC_ERR_INT_EN_MSEE) 793 /* CAPTURE_ATTRIBUTES - Memory error attributes capture 794 */ 795 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 796 #define ECC_CAPT_ATTR_BNUM_SHIFT 28 797 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 798 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 799 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 800 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 801 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 802 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 803 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 804 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 805 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 806 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 807 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 808 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 809 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 810 #define ECC_CAPT_ATTR_TSRC_I2C 0x9 811 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 812 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 813 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 814 #define ECC_CAPT_ATTR_TSRC_DMA 0xF 815 #define ECC_CAPT_ATTR_TSRC_SHIFT 16 816 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 817 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 818 #define ECC_CAPT_ATTR_TTYP_READ 0x2 819 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 820 #define ECC_CAPT_ATTR_TTYP_SHIFT 12 821 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 822 823 /* ERR_SBE - Single bit ECC memory error management 824 */ 825 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 826 #define ECC_ERROR_MAN_SBET_SHIFT 16 827 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 828 #define ECC_ERROR_MAN_SBEC_SHIFT 0 829 830 /* BR - Base Registers 831 */ 832 #define BR0 0x5000 /* Register offset to immr */ 833 #define BR1 0x5008 834 #define BR2 0x5010 835 #define BR3 0x5018 836 #define BR4 0x5020 837 #define BR5 0x5028 838 #define BR6 0x5030 839 #define BR7 0x5038 840 841 #define BR_BA 0xFFFF8000 842 #define BR_BA_SHIFT 15 843 #define BR_PS 0x00001800 844 #define BR_PS_SHIFT 11 845 #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 846 #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 847 #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 848 #define BR_DECC 0x00000600 849 #define BR_DECC_SHIFT 9 850 #define BR_DECC_OFF 0x00000000 851 #define BR_DECC_CHK 0x00000200 852 #define BR_DECC_CHK_GEN 0x00000400 853 #define BR_WP 0x00000100 854 #define BR_WP_SHIFT 8 855 #define BR_MSEL 0x000000E0 856 #define BR_MSEL_SHIFT 5 857 #define BR_MS_GPCM 0x00000000 /* GPCM */ 858 #define BR_MS_FCM 0x00000020 /* FCM */ 859 #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 860 #define BR_MS_UPMA 0x00000080 /* UPMA */ 861 #define BR_MS_UPMB 0x000000A0 /* UPMB */ 862 #define BR_MS_UPMC 0x000000C0 /* UPMC */ 863 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 864 #define BR_ATOM 0x0000000C 865 #define BR_ATOM_SHIFT 2 866 #endif 867 #define BR_V 0x00000001 868 #define BR_V_SHIFT 0 869 870 #if defined(CONFIG_MPC834X) 871 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) 872 #elif defined(CONFIG_MPC8360) 873 #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) 874 #endif 875 876 /* OR - Option Registers 877 */ 878 #define OR0 0x5004 /* Register offset to immr */ 879 #define OR1 0x500C 880 #define OR2 0x5014 881 #define OR3 0x501C 882 #define OR4 0x5024 883 #define OR5 0x502C 884 #define OR6 0x5034 885 #define OR7 0x503C 886 887 #define OR_GPCM_AM 0xFFFF8000 888 #define OR_GPCM_AM_SHIFT 15 889 #define OR_GPCM_BCTLD 0x00001000 890 #define OR_GPCM_BCTLD_SHIFT 12 891 #define OR_GPCM_CSNT 0x00000800 892 #define OR_GPCM_CSNT_SHIFT 11 893 #define OR_GPCM_ACS 0x00000600 894 #define OR_GPCM_ACS_SHIFT 9 895 #define OR_GPCM_ACS_0b10 0x00000400 896 #define OR_GPCM_ACS_0b11 0x00000600 897 #define OR_GPCM_XACS 0x00000100 898 #define OR_GPCM_XACS_SHIFT 8 899 #define OR_GPCM_SCY 0x000000F0 900 #define OR_GPCM_SCY_SHIFT 4 901 #define OR_GPCM_SCY_1 0x00000010 902 #define OR_GPCM_SCY_2 0x00000020 903 #define OR_GPCM_SCY_3 0x00000030 904 #define OR_GPCM_SCY_4 0x00000040 905 #define OR_GPCM_SCY_5 0x00000050 906 #define OR_GPCM_SCY_6 0x00000060 907 #define OR_GPCM_SCY_7 0x00000070 908 #define OR_GPCM_SCY_8 0x00000080 909 #define OR_GPCM_SCY_9 0x00000090 910 #define OR_GPCM_SCY_10 0x000000a0 911 #define OR_GPCM_SCY_11 0x000000b0 912 #define OR_GPCM_SCY_12 0x000000c0 913 #define OR_GPCM_SCY_13 0x000000d0 914 #define OR_GPCM_SCY_14 0x000000e0 915 #define OR_GPCM_SCY_15 0x000000f0 916 #define OR_GPCM_SETA 0x00000008 917 #define OR_GPCM_SETA_SHIFT 3 918 #define OR_GPCM_TRLX 0x00000004 919 #define OR_GPCM_TRLX_SHIFT 2 920 #define OR_GPCM_EHTR 0x00000002 921 #define OR_GPCM_EHTR_SHIFT 1 922 #define OR_GPCM_EAD 0x00000001 923 #define OR_GPCM_EAD_SHIFT 0 924 925 #define OR_FCM_AM 0xFFFF8000 926 #define OR_FCM_AM_SHIFT 15 927 #define OR_FCM_BCTLD 0x00001000 928 #define OR_FCM_BCTLD_SHIFT 12 929 #define OR_FCM_PGS 0x00000400 930 #define OR_FCM_PGS_SHIFT 10 931 #define OR_FCM_CSCT 0x00000200 932 #define OR_FCM_CSCT_SHIFT 9 933 #define OR_FCM_CST 0x00000100 934 #define OR_FCM_CST_SHIFT 8 935 #define OR_FCM_CHT 0x00000080 936 #define OR_FCM_CHT_SHIFT 7 937 #define OR_FCM_SCY 0x00000070 938 #define OR_FCM_SCY_SHIFT 4 939 #define OR_FCM_SCY_1 0x00000010 940 #define OR_FCM_SCY_2 0x00000020 941 #define OR_FCM_SCY_3 0x00000030 942 #define OR_FCM_SCY_4 0x00000040 943 #define OR_FCM_SCY_5 0x00000050 944 #define OR_FCM_SCY_6 0x00000060 945 #define OR_FCM_SCY_7 0x00000070 946 #define OR_FCM_RST 0x00000008 947 #define OR_FCM_RST_SHIFT 3 948 #define OR_FCM_TRLX 0x00000004 949 #define OR_FCM_TRLX_SHIFT 2 950 #define OR_FCM_EHTR 0x00000002 951 #define OR_FCM_EHTR_SHIFT 1 952 953 #define OR_UPM_AM 0xFFFF8000 954 #define OR_UPM_AM_SHIFT 15 955 #define OR_UPM_XAM 0x00006000 956 #define OR_UPM_XAM_SHIFT 13 957 #define OR_UPM_BCTLD 0x00001000 958 #define OR_UPM_BCTLD_SHIFT 12 959 #define OR_UPM_BI 0x00000100 960 #define OR_UPM_BI_SHIFT 8 961 #define OR_UPM_TRLX 0x00000004 962 #define OR_UPM_TRLX_SHIFT 2 963 #define OR_UPM_EHTR 0x00000002 964 #define OR_UPM_EHTR_SHIFT 1 965 #define OR_UPM_EAD 0x00000001 966 #define OR_UPM_EAD_SHIFT 0 967 968 #define OR_SDRAM_AM 0xFFFF8000 969 #define OR_SDRAM_AM_SHIFT 15 970 #define OR_SDRAM_XAM 0x00006000 971 #define OR_SDRAM_XAM_SHIFT 13 972 #define OR_SDRAM_COLS 0x00001C00 973 #define OR_SDRAM_COLS_SHIFT 10 974 #define OR_SDRAM_ROWS 0x000001C0 975 #define OR_SDRAM_ROWS_SHIFT 6 976 #define OR_SDRAM_PMSEL 0x00000020 977 #define OR_SDRAM_PMSEL_SHIFT 5 978 #define OR_SDRAM_EAD 0x00000001 979 #define OR_SDRAM_EAD_SHIFT 0 980 981 #define OR_AM_32KB 0xFFFF8000 982 #define OR_AM_64KB 0xFFFF0000 983 #define OR_AM_128KB 0xFFFE0000 984 #define OR_AM_256KB 0xFFFC0000 985 #define OR_AM_512KB 0xFFF80000 986 #define OR_AM_1MB 0xFFF00000 987 #define OR_AM_2MB 0xFFE00000 988 #define OR_AM_4MB 0xFFC00000 989 #define OR_AM_8MB 0xFF800000 990 #define OR_AM_16MB 0xFF000000 991 #define OR_AM_32MB 0xFE000000 992 #define OR_AM_64MB 0xFC000000 993 #define OR_AM_128MB 0xF8000000 994 #define OR_AM_256MB 0xF0000000 995 #define OR_AM_512MB 0xE0000000 996 #define OR_AM_1GB 0xC0000000 997 #define OR_AM_2GB 0x80000000 998 #define OR_AM_4GB 0x00000000 999 1000 #define LBLAWAR_EN 0x80000000 1001 #define LBLAWAR_4KB 0x0000000B 1002 #define LBLAWAR_8KB 0x0000000C 1003 #define LBLAWAR_16KB 0x0000000D 1004 #define LBLAWAR_32KB 0x0000000E 1005 #define LBLAWAR_64KB 0x0000000F 1006 #define LBLAWAR_128KB 0x00000010 1007 #define LBLAWAR_256KB 0x00000011 1008 #define LBLAWAR_512KB 0x00000012 1009 #define LBLAWAR_1MB 0x00000013 1010 #define LBLAWAR_2MB 0x00000014 1011 #define LBLAWAR_4MB 0x00000015 1012 #define LBLAWAR_8MB 0x00000016 1013 #define LBLAWAR_16MB 0x00000017 1014 #define LBLAWAR_32MB 0x00000018 1015 #define LBLAWAR_64MB 0x00000019 1016 #define LBLAWAR_128MB 0x0000001A 1017 #define LBLAWAR_256MB 0x0000001B 1018 #define LBLAWAR_512MB 0x0000001C 1019 #define LBLAWAR_1GB 0x0000001D 1020 #define LBLAWAR_2GB 0x0000001E 1021 1022 /* LBCR - Local Bus Configuration Register 1023 */ 1024 #define LBCR_LDIS 0x80000000 1025 #define LBCR_LDIS_SHIFT 31 1026 #define LBCR_BCTLC 0x00C00000 1027 #define LBCR_BCTLC_SHIFT 22 1028 #define LBCR_LPBSE 0x00020000 1029 #define LBCR_LPBSE_SHIFT 17 1030 #define LBCR_EPAR 0x00010000 1031 #define LBCR_EPAR_SHIFT 16 1032 #define LBCR_BMT 0x0000FF00 1033 #define LBCR_BMT_SHIFT 8 1034 1035 /* LCRR - Clock Ratio Register 1036 */ 1037 #define LCRR_DBYP 0x80000000 1038 #define LCRR_DBYP_SHIFT 31 1039 #define LCRR_BUFCMDC 0x30000000 1040 #define LCRR_BUFCMDC_SHIFT 28 1041 #define LCRR_BUFCMDC_1 0x10000000 1042 #define LCRR_BUFCMDC_2 0x20000000 1043 #define LCRR_BUFCMDC_3 0x30000000 1044 #define LCRR_BUFCMDC_4 0x00000000 1045 #define LCRR_ECL 0x03000000 1046 #define LCRR_ECL_SHIFT 24 1047 #define LCRR_ECL_4 0x00000000 1048 #define LCRR_ECL_5 0x01000000 1049 #define LCRR_ECL_6 0x02000000 1050 #define LCRR_ECL_7 0x03000000 1051 #define LCRR_EADC 0x00030000 1052 #define LCRR_EADC_SHIFT 16 1053 #define LCRR_EADC_1 0x00010000 1054 #define LCRR_EADC_2 0x00020000 1055 #define LCRR_EADC_3 0x00030000 1056 #define LCRR_EADC_4 0x00000000 1057 #define LCRR_CLKDIV 0x0000000F 1058 #define LCRR_CLKDIV_SHIFT 0 1059 #define LCRR_CLKDIV_2 0x00000002 1060 #define LCRR_CLKDIV_4 0x00000004 1061 #define LCRR_CLKDIV_8 0x00000008 1062 1063 /* DMAMR - DMA Mode Register 1064 */ 1065 #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 1066 #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 1067 #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 1068 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 1069 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 1070 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 1071 #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 1072 #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 1073 1074 /* DMASR - DMA Status Register 1075 */ 1076 #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 1077 #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 1078 1079 /* CONFIG_ADDRESS - PCI Config Address Register 1080 */ 1081 #define PCI_CONFIG_ADDRESS_EN 0x80000000 1082 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1083 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1084 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1085 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1086 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1087 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1088 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1089 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1090 1091 /* POTAR - PCI Outbound Translation Address Register 1092 */ 1093 #define POTAR_TA_MASK 0x000fffff 1094 1095 /* POBAR - PCI Outbound Base Address Register 1096 */ 1097 #define POBAR_BA_MASK 0x000fffff 1098 1099 /* POCMR - PCI Outbound Comparision Mask Register 1100 */ 1101 #define POCMR_EN 0x80000000 1102 #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1103 #define POCMR_SE 0x20000000 /* streaming enable */ 1104 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1105 #define POCMR_CM_MASK 0x000fffff 1106 #define POCMR_CM_4G 0x00000000 1107 #define POCMR_CM_2G 0x00080000 1108 #define POCMR_CM_1G 0x000C0000 1109 #define POCMR_CM_512M 0x000E0000 1110 #define POCMR_CM_256M 0x000F0000 1111 #define POCMR_CM_128M 0x000F8000 1112 #define POCMR_CM_64M 0x000FC000 1113 #define POCMR_CM_32M 0x000FE000 1114 #define POCMR_CM_16M 0x000FF000 1115 #define POCMR_CM_8M 0x000FF800 1116 #define POCMR_CM_4M 0x000FFC00 1117 #define POCMR_CM_2M 0x000FFE00 1118 #define POCMR_CM_1M 0x000FFF00 1119 #define POCMR_CM_512K 0x000FFF80 1120 #define POCMR_CM_256K 0x000FFFC0 1121 #define POCMR_CM_128K 0x000FFFE0 1122 #define POCMR_CM_64K 0x000FFFF0 1123 #define POCMR_CM_32K 0x000FFFF8 1124 #define POCMR_CM_16K 0x000FFFFC 1125 #define POCMR_CM_8K 0x000FFFFE 1126 #define POCMR_CM_4K 0x000FFFFF 1127 1128 /* PITAR - PCI Inbound Translation Address Register 1129 */ 1130 #define PITAR_TA_MASK 0x000fffff 1131 1132 /* PIBAR - PCI Inbound Base/Extended Address Register 1133 */ 1134 #define PIBAR_MASK 0xffffffff 1135 #define PIEBAR_EBA_MASK 0x000fffff 1136 1137 /* PIWAR - PCI Inbound Windows Attributes Register 1138 */ 1139 #define PIWAR_EN 0x80000000 1140 #define PIWAR_PF 0x20000000 1141 #define PIWAR_RTT_MASK 0x000f0000 1142 #define PIWAR_RTT_NO_SNOOP 0x00040000 1143 #define PIWAR_RTT_SNOOP 0x00050000 1144 #define PIWAR_WTT_MASK 0x0000f000 1145 #define PIWAR_WTT_NO_SNOOP 0x00004000 1146 #define PIWAR_WTT_SNOOP 0x00005000 1147 #define PIWAR_IWS_MASK 0x0000003F 1148 #define PIWAR_IWS_4K 0x0000000B 1149 #define PIWAR_IWS_8K 0x0000000C 1150 #define PIWAR_IWS_16K 0x0000000D 1151 #define PIWAR_IWS_32K 0x0000000E 1152 #define PIWAR_IWS_64K 0x0000000F 1153 #define PIWAR_IWS_128K 0x00000010 1154 #define PIWAR_IWS_256K 0x00000011 1155 #define PIWAR_IWS_512K 0x00000012 1156 #define PIWAR_IWS_1M 0x00000013 1157 #define PIWAR_IWS_2M 0x00000014 1158 #define PIWAR_IWS_4M 0x00000015 1159 #define PIWAR_IWS_8M 0x00000016 1160 #define PIWAR_IWS_16M 0x00000017 1161 #define PIWAR_IWS_32M 0x00000018 1162 #define PIWAR_IWS_64M 0x00000019 1163 #define PIWAR_IWS_128M 0x0000001A 1164 #define PIWAR_IWS_256M 0x0000001B 1165 #define PIWAR_IWS_512M 0x0000001C 1166 #define PIWAR_IWS_1G 0x0000001D 1167 #define PIWAR_IWS_2G 0x0000001E 1168 1169 /* PMCCR1 - PCI Configuration Register 1 1170 */ 1171 #define PMCCR1_POWER_OFF 0x00000020 1172 1173 /* FMR - Flash Mode Register 1174 */ 1175 #define FMR_CWTO 0x0000F000 1176 #define FMR_CWTO_SHIFT 12 1177 #define FMR_BOOT 0x00000800 1178 #define FMR_ECCM 0x00000100 1179 #define FMR_AL 0x00000030 1180 #define FMR_AL_SHIFT 4 1181 #define FMR_OP 0x00000003 1182 #define FMR_OP_SHIFT 0 1183 1184 /* FIR - Flash Instruction Register 1185 */ 1186 #define FIR_OP0 0xF0000000 1187 #define FIR_OP0_SHIFT 28 1188 #define FIR_OP1 0x0F000000 1189 #define FIR_OP1_SHIFT 24 1190 #define FIR_OP2 0x00F00000 1191 #define FIR_OP2_SHIFT 20 1192 #define FIR_OP3 0x000F0000 1193 #define FIR_OP3_SHIFT 16 1194 #define FIR_OP4 0x0000F000 1195 #define FIR_OP4_SHIFT 12 1196 #define FIR_OP5 0x00000F00 1197 #define FIR_OP5_SHIFT 8 1198 #define FIR_OP6 0x000000F0 1199 #define FIR_OP6_SHIFT 4 1200 #define FIR_OP7 0x0000000F 1201 #define FIR_OP7_SHIFT 0 1202 #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 1203 #define FIR_OP_CA 0x1 /* Issue current column address */ 1204 #define FIR_OP_PA 0x2 /* Issue current block+page address */ 1205 #define FIR_OP_UA 0x3 /* Issue user defined address */ 1206 #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 1207 #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 1208 #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 1209 #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 1210 #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 1211 #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 1212 #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 1213 #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 1214 #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 1215 #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 1216 #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 1217 #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 1218 1219 /* FCR - Flash Command Register 1220 */ 1221 #define FCR_CMD0 0xFF000000 1222 #define FCR_CMD0_SHIFT 24 1223 #define FCR_CMD1 0x00FF0000 1224 #define FCR_CMD1_SHIFT 16 1225 #define FCR_CMD2 0x0000FF00 1226 #define FCR_CMD2_SHIFT 8 1227 #define FCR_CMD3 0x000000FF 1228 #define FCR_CMD3_SHIFT 0 1229 1230 /* FBAR - Flash Block Address Register 1231 */ 1232 #define FBAR_BLK 0x00FFFFFF 1233 1234 /* FPAR - Flash Page Address Register 1235 */ 1236 #define FPAR_SP_PI 0x00007C00 1237 #define FPAR_SP_PI_SHIFT 10 1238 #define FPAR_SP_MS 0x00000200 1239 #define FPAR_SP_CI 0x000001FF 1240 #define FPAR_SP_CI_SHIFT 0 1241 #define FPAR_LP_PI 0x0003F000 1242 #define FPAR_LP_PI_SHIFT 12 1243 #define FPAR_LP_MS 0x00000800 1244 #define FPAR_LP_CI 0x000007FF 1245 #define FPAR_LP_CI_SHIFT 0 1246 1247 /* LTESR - Transfer Error Status Register 1248 */ 1249 #define LTESR_BM 0x80000000 1250 #define LTESR_FCT 0x40000000 1251 #define LTESR_PAR 0x20000000 1252 #define LTESR_WP 0x04000000 1253 #define LTESR_ATMW 0x00800000 1254 #define LTESR_ATMR 0x00400000 1255 #define LTESR_CS 0x00080000 1256 #define LTESR_CC 0x00000001 1257 1258 /* DDR Control Driver Register 1259 */ 1260 #define DDRCDR_EN 0x40000000 1261 #define DDRCDR_PZ 0x3C000000 1262 #define DDRCDR_PZ_MAXZ 0x00000000 1263 #define DDRCDR_PZ_HIZ 0x20000000 1264 #define DDRCDR_PZ_NOMZ 0x30000000 1265 #define DDRCDR_PZ_LOZ 0x38000000 1266 #define DDRCDR_PZ_MINZ 0x3C000000 1267 #define DDRCDR_NZ 0x3C000000 1268 #define DDRCDR_NZ_MAXZ 0x00000000 1269 #define DDRCDR_NZ_HIZ 0x02000000 1270 #define DDRCDR_NZ_NOMZ 0x03000000 1271 #define DDRCDR_NZ_LOZ 0x03800000 1272 #define DDRCDR_NZ_MINZ 0x03C00000 1273 #define DDRCDR_ODT 0x00080000 1274 #define DDRCDR_DDR_CFG 0x00040000 1275 #define DDRCDR_M_ODR 0x00000002 1276 #define DDRCDR_Q_DRN 0x00000001 1277 1278 #ifndef __ASSEMBLY__ 1279 struct pci_region; 1280 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 1281 #endif 1282 1283 #endif /* __MPC83XX_H__ */ 1284