1 /* 2 * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #ifndef __MPC83XX_H__ 14 #define __MPC83XX_H__ 15 16 #include <config.h> 17 #include <asm/fsl_lbc.h> 18 #if defined(CONFIG_E300) 19 #include <asm/e300.h> 20 #endif 21 22 /* MPC83xx cpu provide RCR register to do reset thing specially 23 */ 24 #define MPC83xx_RESET 25 26 /* System reset offset (PowerPC standard) 27 */ 28 #define EXC_OFF_SYS_RESET 0x0100 29 #define _START_OFFSET EXC_OFF_SYS_RESET 30 31 /* IMMRBAR - Internal Memory Register Base Address 32 */ 33 #ifndef CONFIG_DEFAULT_IMMR 34 #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 35 #endif 36 #define IMMRBAR 0x0000 /* Register offset to immr */ 37 #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 38 #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 39 40 /* LAWBAR - Local Access Window Base Address Register 41 */ 42 #define LBLAWBAR0 0x0020 /* Register offset to immr */ 43 #define LBLAWAR0 0x0024 44 #define LBLAWBAR1 0x0028 45 #define LBLAWAR1 0x002C 46 #define LBLAWBAR2 0x0030 47 #define LBLAWAR2 0x0034 48 #define LBLAWBAR3 0x0038 49 #define LBLAWAR3 0x003C 50 #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 51 52 /* SPRIDR - System Part and Revision ID Register 53 */ 54 #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ 55 #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ 56 57 #if defined(CONFIG_MPC834x) 58 #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) 59 #define REVID_MINOR(spridr) (spridr & 0x000000FF) 60 #else 61 #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) 62 #define REVID_MINOR(spridr) (spridr & 0x0000000F) 63 #endif 64 65 #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) 66 #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) 67 68 #define SPR_8308 0x8100 69 #define SPR_831X_FAMILY 0x80B 70 #define SPR_8311 0x80B2 71 #define SPR_8313 0x80B0 72 #define SPR_8314 0x80B6 73 #define SPR_8315 0x80B4 74 #define SPR_832X_FAMILY 0x806 75 #define SPR_8321 0x8066 76 #define SPR_8323 0x8062 77 #define SPR_834X_FAMILY 0x803 78 #define SPR_8343 0x8036 79 #define SPR_8347_TBGA_ 0x8032 80 #define SPR_8347_PBGA_ 0x8034 81 #define SPR_8349 0x8030 82 #define SPR_836X_FAMILY 0x804 83 #define SPR_8358_TBGA_ 0x804A 84 #define SPR_8358_PBGA_ 0x804E 85 #define SPR_8360 0x8048 86 #define SPR_837X_FAMILY 0x80C 87 #define SPR_8377 0x80C6 88 #define SPR_8378 0x80C4 89 #define SPR_8379 0x80C2 90 91 /* SPCR - System Priority Configuration Register 92 */ 93 #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 94 #define SPCR_PCIHPE_SHIFT (31-3) 95 #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 96 #define SPCR_PCIPR_SHIFT (31-7) 97 #define SPCR_OPT 0x00800000 /* Optimize */ 98 #define SPCR_OPT_SHIFT (31-8) 99 #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 100 #define SPCR_TBEN_SHIFT (31-9) 101 #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 102 #define SPCR_COREPR_SHIFT (31-11) 103 104 #if defined(CONFIG_MPC834x) 105 /* SPCR bits - MPC8349 specific */ 106 #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 107 #define SPCR_TSEC1DP_SHIFT (31-19) 108 #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 109 #define SPCR_TSEC1BDP_SHIFT (31-21) 110 #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 111 #define SPCR_TSEC1EP_SHIFT (31-23) 112 #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 113 #define SPCR_TSEC2DP_SHIFT (31-27) 114 #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 115 #define SPCR_TSEC2BDP_SHIFT (31-29) 116 #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 117 #define SPCR_TSEC2EP_SHIFT (31-31) 118 119 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 120 defined(CONFIG_MPC837x) 121 /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ 122 #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 123 #define SPCR_TSECDP_SHIFT (31-19) 124 #define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */ 125 #define SPCR_TSECBDP_SHIFT (31-21) 126 #define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */ 127 #define SPCR_TSECEP_SHIFT (31-23) 128 #endif 129 130 /* SICRL/H - System I/O Configuration Register Low/High 131 */ 132 #if defined(CONFIG_MPC834x) 133 /* SICRL bits - MPC8349 specific */ 134 #define SICRL_LDP_A 0x80000000 135 #define SICRL_USB1 0x40000000 136 #define SICRL_USB0 0x20000000 137 #define SICRL_UART 0x0C000000 138 #define SICRL_GPIO1_A 0x02000000 139 #define SICRL_GPIO1_B 0x01000000 140 #define SICRL_GPIO1_C 0x00800000 141 #define SICRL_GPIO1_D 0x00400000 142 #define SICRL_GPIO1_E 0x00200000 143 #define SICRL_GPIO1_F 0x00180000 144 #define SICRL_GPIO1_G 0x00040000 145 #define SICRL_GPIO1_H 0x00020000 146 #define SICRL_GPIO1_I 0x00010000 147 #define SICRL_GPIO1_J 0x00008000 148 #define SICRL_GPIO1_K 0x00004000 149 #define SICRL_GPIO1_L 0x00003000 150 151 /* SICRH bits - MPC8349 specific */ 152 #define SICRH_DDR 0x80000000 153 #define SICRH_TSEC1_A 0x10000000 154 #define SICRH_TSEC1_B 0x08000000 155 #define SICRH_TSEC1_C 0x04000000 156 #define SICRH_TSEC1_D 0x02000000 157 #define SICRH_TSEC1_E 0x01000000 158 #define SICRH_TSEC1_F 0x00800000 159 #define SICRH_TSEC2_A 0x00400000 160 #define SICRH_TSEC2_B 0x00200000 161 #define SICRH_TSEC2_C 0x00100000 162 #define SICRH_TSEC2_D 0x00080000 163 #define SICRH_TSEC2_E 0x00040000 164 #define SICRH_TSEC2_F 0x00020000 165 #define SICRH_TSEC2_G 0x00010000 166 #define SICRH_TSEC2_H 0x00008000 167 #define SICRH_GPIO2_A 0x00004000 168 #define SICRH_GPIO2_B 0x00002000 169 #define SICRH_GPIO2_C 0x00001000 170 #define SICRH_GPIO2_D 0x00000800 171 #define SICRH_GPIO2_E 0x00000400 172 #define SICRH_GPIO2_F 0x00000200 173 #define SICRH_GPIO2_G 0x00000180 174 #define SICRH_GPIO2_H 0x00000060 175 #define SICRH_TSOBI1 0x00000002 176 #define SICRH_TSOBI2 0x00000001 177 178 #elif defined(CONFIG_MPC8360) 179 /* SICRL bits - MPC8360 specific */ 180 #define SICRL_LDP_A 0xC0000000 181 #define SICRL_LCLK_1 0x10000000 182 #define SICRL_LCLK_2 0x08000000 183 #define SICRL_SRCID_A 0x03000000 184 #define SICRL_IRQ_CKSTP_A 0x00C00000 185 186 /* SICRH bits - MPC8360 specific */ 187 #define SICRH_DDR 0x80000000 188 #define SICRH_SECONDARY_DDR 0x40000000 189 #define SICRH_SDDROE 0x20000000 190 #define SICRH_IRQ3 0x10000000 191 #define SICRH_UC1EOBI 0x00000004 192 #define SICRH_UC2E1OBI 0x00000002 193 #define SICRH_UC2E2OBI 0x00000001 194 195 #elif defined(CONFIG_MPC832x) 196 /* SICRL bits - MPC832x specific */ 197 #define SICRL_LDP_LCS_A 0x80000000 198 #define SICRL_IRQ_CKS 0x20000000 199 #define SICRL_PCI_MSRC 0x10000000 200 #define SICRL_URT_CTPR 0x06000000 201 #define SICRL_IRQ_CTPR 0x00C00000 202 203 #elif defined(CONFIG_MPC8313) 204 /* SICRL bits - MPC8313 specific */ 205 #define SICRL_LBC 0x30000000 206 #define SICRL_UART 0x0C000000 207 #define SICRL_SPI_A 0x03000000 208 #define SICRL_SPI_B 0x00C00000 209 #define SICRL_SPI_C 0x00300000 210 #define SICRL_SPI_D 0x000C0000 211 #define SICRL_USBDR_11 0x00000C00 212 #define SICRL_USBDR_10 0x00000800 213 #define SICRL_USBDR_01 0x00000400 214 #define SICRL_USBDR_00 0x00000000 215 #define SICRL_ETSEC1_A 0x0000000C 216 #define SICRL_ETSEC2_A 0x00000003 217 218 /* SICRH bits - MPC8313 specific */ 219 #define SICRH_INTR_A 0x02000000 220 #define SICRH_INTR_B 0x00C00000 221 #define SICRH_IIC 0x00300000 222 #define SICRH_ETSEC2_B 0x000C0000 223 #define SICRH_ETSEC2_C 0x00030000 224 #define SICRH_ETSEC2_D 0x0000C000 225 #define SICRH_ETSEC2_E 0x00003000 226 #define SICRH_ETSEC2_F 0x00000C00 227 #define SICRH_ETSEC2_G 0x00000300 228 #define SICRH_ETSEC1_B 0x00000080 229 #define SICRH_ETSEC1_C 0x00000060 230 #define SICRH_GTX1_DLY 0x00000008 231 #define SICRH_GTX2_DLY 0x00000004 232 #define SICRH_TSOBI1 0x00000002 233 #define SICRH_TSOBI2 0x00000001 234 235 #elif defined(CONFIG_MPC8315) 236 /* SICRL bits - MPC8315 specific */ 237 #define SICRL_DMA_CH0 0xc0000000 238 #define SICRL_DMA_SPI 0x30000000 239 #define SICRL_UART 0x0c000000 240 #define SICRL_IRQ4 0x02000000 241 #define SICRL_IRQ5 0x01800000 242 #define SICRL_IRQ6_7 0x00400000 243 #define SICRL_IIC1 0x00300000 244 #define SICRL_TDM 0x000c0000 245 #define SICRL_TDM_SHARED 0x00030000 246 #define SICRL_PCI_A 0x0000c000 247 #define SICRL_ELBC_A 0x00003000 248 #define SICRL_ETSEC1_A 0x000000c0 249 #define SICRL_ETSEC1_B 0x00000030 250 #define SICRL_ETSEC1_C 0x0000000c 251 #define SICRL_TSEXPOBI 0x00000001 252 253 /* SICRH bits - MPC8315 specific */ 254 #define SICRH_GPIO_0 0xc0000000 255 #define SICRH_GPIO_1 0x30000000 256 #define SICRH_GPIO_2 0x0c000000 257 #define SICRH_GPIO_3 0x03000000 258 #define SICRH_GPIO_4 0x00c00000 259 #define SICRH_GPIO_5 0x00300000 260 #define SICRH_GPIO_6 0x000c0000 261 #define SICRH_GPIO_7 0x00030000 262 #define SICRH_GPIO_8 0x0000c000 263 #define SICRH_GPIO_9 0x00003000 264 #define SICRH_GPIO_10 0x00000c00 265 #define SICRH_GPIO_11 0x00000300 266 #define SICRH_ETSEC2_A 0x000000c0 267 #define SICRH_TSOBI1 0x00000002 268 #define SICRH_TSOBI2 0x00000001 269 270 #elif defined(CONFIG_MPC837x) 271 /* SICRL bits - MPC837x specific */ 272 #define SICRL_USB_A 0xC0000000 273 #define SICRL_USB_B 0x30000000 274 #define SICRL_USB_B_SD 0x20000000 275 #define SICRL_UART 0x0C000000 276 #define SICRL_GPIO_A 0x02000000 277 #define SICRL_GPIO_B 0x01000000 278 #define SICRL_GPIO_C 0x00800000 279 #define SICRL_GPIO_D 0x00400000 280 #define SICRL_GPIO_E 0x00200000 281 #define SICRL_GPIO_F 0x00180000 282 #define SICRL_GPIO_G 0x00040000 283 #define SICRL_GPIO_H 0x00020000 284 #define SICRL_GPIO_I 0x00010000 285 #define SICRL_GPIO_J 0x00008000 286 #define SICRL_GPIO_K 0x00004000 287 #define SICRL_GPIO_L 0x00003000 288 #define SICRL_DMA_A 0x00000800 289 #define SICRL_DMA_B 0x00000400 290 #define SICRL_DMA_C 0x00000200 291 #define SICRL_DMA_D 0x00000100 292 #define SICRL_DMA_E 0x00000080 293 #define SICRL_DMA_F 0x00000040 294 #define SICRL_DMA_G 0x00000020 295 #define SICRL_DMA_H 0x00000010 296 #define SICRL_DMA_I 0x00000008 297 #define SICRL_DMA_J 0x00000004 298 #define SICRL_LDP_A 0x00000002 299 #define SICRL_LDP_B 0x00000001 300 301 /* SICRH bits - MPC837x specific */ 302 #define SICRH_DDR 0x80000000 303 #define SICRH_TSEC1_A 0x10000000 304 #define SICRH_TSEC1_B 0x08000000 305 #define SICRH_TSEC2_A 0x00400000 306 #define SICRH_TSEC2_B 0x00200000 307 #define SICRH_TSEC2_C 0x00100000 308 #define SICRH_TSEC2_D 0x00080000 309 #define SICRH_TSEC2_E 0x00040000 310 #define SICRH_TMR 0x00010000 311 #define SICRH_GPIO2_A 0x00008000 312 #define SICRH_GPIO2_B 0x00004000 313 #define SICRH_GPIO2_C 0x00002000 314 #define SICRH_GPIO2_D 0x00001000 315 #define SICRH_GPIO2_E 0x00000C00 316 #define SICRH_GPIO2_E_SD 0x00000800 317 #define SICRH_GPIO2_F 0x00000300 318 #define SICRH_GPIO2_G 0x000000C0 319 #define SICRH_GPIO2_H 0x00000030 320 #define SICRH_SPI 0x00000003 321 #define SICRH_SPI_SD 0x00000001 322 #endif 323 324 /* SWCRR - System Watchdog Control Register 325 */ 326 #define SWCRR 0x0204 /* Register offset to immr */ 327 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 328 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 329 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 330 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 331 #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 332 333 /* SWCNR - System Watchdog Counter Register 334 */ 335 #define SWCNR 0x0208 /* Register offset to immr */ 336 #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 337 #define SWCNR_RES ~(SWCNR_SWCN) 338 339 /* SWSRR - System Watchdog Service Register 340 */ 341 #define SWSRR 0x020E /* Register offset to immr */ 342 343 /* ACR - Arbiter Configuration Register 344 */ 345 #define ACR_COREDIS 0x10000000 /* Core disable */ 346 #define ACR_COREDIS_SHIFT (31-7) 347 #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 348 #define ACR_PIPE_DEP_SHIFT (31-15) 349 #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 350 #define ACR_PCI_RPTCNT_SHIFT (31-19) 351 #define ACR_RPTCNT 0x00000700 /* Repeat count */ 352 #define ACR_RPTCNT_SHIFT (31-23) 353 #define ACR_APARK 0x00000030 /* Address parking */ 354 #define ACR_APARK_SHIFT (31-27) 355 #define ACR_PARKM 0x0000000F /* Parking master */ 356 #define ACR_PARKM_SHIFT (31-31) 357 358 /* ATR - Arbiter Timers Register 359 */ 360 #define ATR_DTO 0x00FF0000 /* Data time out */ 361 #define ATR_DTO_SHIFT 16 362 #define ATR_ATO 0x000000FF /* Address time out */ 363 #define ATR_ATO_SHIFT 0 364 365 /* AER - Arbiter Event Register 366 */ 367 #define AER_ETEA 0x00000020 /* Transfer error */ 368 #define AER_RES 0x00000010 /* Reserved transfer type */ 369 #define AER_ECW 0x00000008 /* External control word transfer type */ 370 #define AER_AO 0x00000004 /* Address Only transfer type */ 371 #define AER_DTO 0x00000002 /* Data time out */ 372 #define AER_ATO 0x00000001 /* Address time out */ 373 374 /* AEATR - Arbiter Event Address Register 375 */ 376 #define AEATR_EVENT 0x07000000 /* Event type */ 377 #define AEATR_EVENT_SHIFT 24 378 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 379 #define AEATR_MSTR_ID_SHIFT 16 380 #define AEATR_TBST 0x00000800 /* Transfer burst */ 381 #define AEATR_TBST_SHIFT 11 382 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 383 #define AEATR_TSIZE_SHIFT 8 384 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 385 #define AEATR_TTYPE_SHIFT 0 386 387 /* HRCWL - Hard Reset Configuration Word Low 388 */ 389 #define HRCWL_LBIUCM 0x80000000 390 #define HRCWL_LBIUCM_SHIFT 31 391 #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 392 #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 393 394 #define HRCWL_DDRCM 0x40000000 395 #define HRCWL_DDRCM_SHIFT 30 396 #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 397 #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 398 399 #define HRCWL_SPMF 0x0f000000 400 #define HRCWL_SPMF_SHIFT 24 401 #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 402 #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 403 #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 404 #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 405 #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 406 #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 407 #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 408 #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 409 #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 410 #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 411 #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 412 #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 413 #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 414 #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 415 #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 416 #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 417 418 #define HRCWL_VCO_BYPASS 0x00000000 419 #define HRCWL_VCO_1X2 0x00000000 420 #define HRCWL_VCO_1X4 0x00200000 421 #define HRCWL_VCO_1X8 0x00400000 422 423 #define HRCWL_COREPLL 0x007F0000 424 #define HRCWL_COREPLL_SHIFT 16 425 #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 426 #define HRCWL_CORE_TO_CSB_1X1 0x00020000 427 #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 428 #define HRCWL_CORE_TO_CSB_2X1 0x00040000 429 #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 430 #define HRCWL_CORE_TO_CSB_3X1 0x00060000 431 432 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 433 #define HRCWL_CEVCOD 0x000000C0 434 #define HRCWL_CEVCOD_SHIFT 6 435 #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 436 #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 437 #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 438 439 #define HRCWL_CEPDF 0x00000020 440 #define HRCWL_CEPDF_SHIFT 5 441 #define HRCWL_CE_PLL_DIV_1X1 0x00000000 442 #define HRCWL_CE_PLL_DIV_2X1 0x00000020 443 444 #define HRCWL_CEPMF 0x0000001F 445 #define HRCWL_CEPMF_SHIFT 0 446 #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 447 #define HRCWL_CE_TO_PLL_1X2 0x00000002 448 #define HRCWL_CE_TO_PLL_1X3 0x00000003 449 #define HRCWL_CE_TO_PLL_1X4 0x00000004 450 #define HRCWL_CE_TO_PLL_1X5 0x00000005 451 #define HRCWL_CE_TO_PLL_1X6 0x00000006 452 #define HRCWL_CE_TO_PLL_1X7 0x00000007 453 #define HRCWL_CE_TO_PLL_1X8 0x00000008 454 #define HRCWL_CE_TO_PLL_1X9 0x00000009 455 #define HRCWL_CE_TO_PLL_1X10 0x0000000A 456 #define HRCWL_CE_TO_PLL_1X11 0x0000000B 457 #define HRCWL_CE_TO_PLL_1X12 0x0000000C 458 #define HRCWL_CE_TO_PLL_1X13 0x0000000D 459 #define HRCWL_CE_TO_PLL_1X14 0x0000000E 460 #define HRCWL_CE_TO_PLL_1X15 0x0000000F 461 #define HRCWL_CE_TO_PLL_1X16 0x00000010 462 #define HRCWL_CE_TO_PLL_1X17 0x00000011 463 #define HRCWL_CE_TO_PLL_1X18 0x00000012 464 #define HRCWL_CE_TO_PLL_1X19 0x00000013 465 #define HRCWL_CE_TO_PLL_1X20 0x00000014 466 #define HRCWL_CE_TO_PLL_1X21 0x00000015 467 #define HRCWL_CE_TO_PLL_1X22 0x00000016 468 #define HRCWL_CE_TO_PLL_1X23 0x00000017 469 #define HRCWL_CE_TO_PLL_1X24 0x00000018 470 #define HRCWL_CE_TO_PLL_1X25 0x00000019 471 #define HRCWL_CE_TO_PLL_1X26 0x0000001A 472 #define HRCWL_CE_TO_PLL_1X27 0x0000001B 473 #define HRCWL_CE_TO_PLL_1X28 0x0000001C 474 #define HRCWL_CE_TO_PLL_1X29 0x0000001D 475 #define HRCWL_CE_TO_PLL_1X30 0x0000001E 476 #define HRCWL_CE_TO_PLL_1X31 0x0000001F 477 478 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 479 #define HRCWL_SVCOD 0x30000000 480 #define HRCWL_SVCOD_SHIFT 28 481 #define HRCWL_SVCOD_DIV_2 0x00000000 482 #define HRCWL_SVCOD_DIV_4 0x10000000 483 #define HRCWL_SVCOD_DIV_8 0x20000000 484 #define HRCWL_SVCOD_DIV_1 0x30000000 485 486 #elif defined(CONFIG_MPC837x) 487 #define HRCWL_SVCOD 0x30000000 488 #define HRCWL_SVCOD_SHIFT 28 489 #define HRCWL_SVCOD_DIV_4 0x00000000 490 #define HRCWL_SVCOD_DIV_8 0x10000000 491 #define HRCWL_SVCOD_DIV_2 0x20000000 492 #define HRCWL_SVCOD_DIV_1 0x30000000 493 #endif 494 495 /* HRCWH - Hardware Reset Configuration Word High 496 */ 497 #define HRCWH_PCI_HOST 0x80000000 498 #define HRCWH_PCI_HOST_SHIFT 31 499 #define HRCWH_PCI_AGENT 0x00000000 500 501 #if defined(CONFIG_MPC834x) 502 #define HRCWH_32_BIT_PCI 0x00000000 503 #define HRCWH_64_BIT_PCI 0x40000000 504 #endif 505 506 #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 507 #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 508 509 #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 510 #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 511 512 #if defined(CONFIG_MPC834x) 513 #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 514 #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 515 516 #elif defined(CONFIG_MPC8360) 517 #define HRCWH_PCICKDRV_DISABLE 0x00000000 518 #define HRCWH_PCICKDRV_ENABLE 0x10000000 519 #endif 520 521 #define HRCWH_CORE_DISABLE 0x08000000 522 #define HRCWH_CORE_ENABLE 0x00000000 523 524 #define HRCWH_FROM_0X00000100 0x00000000 525 #define HRCWH_FROM_0XFFF00100 0x04000000 526 527 #define HRCWH_BOOTSEQ_DISABLE 0x00000000 528 #define HRCWH_BOOTSEQ_NORMAL 0x01000000 529 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 530 531 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 532 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 533 534 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 535 #define HRCWH_ROM_LOC_PCI1 0x00100000 536 #if defined(CONFIG_MPC834x) 537 #define HRCWH_ROM_LOC_PCI2 0x00200000 538 #endif 539 #if defined(CONFIG_MPC837x) 540 #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 541 #endif 542 #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 543 #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 544 #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 545 546 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 547 defined(CONFIG_MPC837x) 548 #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 549 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 550 #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 551 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 552 553 #define HRCWH_RL_EXT_LEGACY 0x00000000 554 #define HRCWH_RL_EXT_NAND 0x00040000 555 556 #define HRCWH_TSEC1M_MASK 0x0000E000 557 #define HRCWH_TSEC1M_IN_MII 0x00000000 558 #define HRCWH_TSEC1M_IN_RMII 0x00002000 559 #define HRCWH_TSEC1M_IN_RGMII 0x00006000 560 #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 561 #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 562 563 #define HRCWH_TSEC2M_MASK 0x00001C00 564 #define HRCWH_TSEC2M_IN_MII 0x00000000 565 #define HRCWH_TSEC2M_IN_RMII 0x00000400 566 #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 567 #define HRCWH_TSEC2M_IN_RTBI 0x00001400 568 #define HRCWH_TSEC2M_IN_SGMII 0x00001800 569 #endif 570 571 #if defined(CONFIG_MPC834x) 572 #define HRCWH_TSEC1M_IN_RGMII 0x00000000 573 #define HRCWH_TSEC1M_IN_RTBI 0x00004000 574 #define HRCWH_TSEC1M_IN_GMII 0x00008000 575 #define HRCWH_TSEC1M_IN_TBI 0x0000C000 576 #define HRCWH_TSEC2M_IN_RGMII 0x00000000 577 #define HRCWH_TSEC2M_IN_RTBI 0x00001000 578 #define HRCWH_TSEC2M_IN_GMII 0x00002000 579 #define HRCWH_TSEC2M_IN_TBI 0x00003000 580 #endif 581 582 #if defined(CONFIG_MPC8360) 583 #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 584 #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 585 #endif 586 587 #define HRCWH_BIG_ENDIAN 0x00000000 588 #define HRCWH_LITTLE_ENDIAN 0x00000008 589 590 #define HRCWH_LALE_NORMAL 0x00000000 591 #define HRCWH_LALE_EARLY 0x00000004 592 593 #define HRCWH_LDP_SET 0x00000000 594 #define HRCWH_LDP_CLEAR 0x00000002 595 596 /* RSR - Reset Status Register 597 */ 598 #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 599 defined(CONFIG_MPC837x) 600 #define RSR_RSTSRC 0xF0000000 /* Reset source */ 601 #define RSR_RSTSRC_SHIFT 28 602 #else 603 #define RSR_RSTSRC 0xE0000000 /* Reset source */ 604 #define RSR_RSTSRC_SHIFT 29 605 #endif 606 #define RSR_BSF 0x00010000 /* Boot seq. fail */ 607 #define RSR_BSF_SHIFT 16 608 #define RSR_SWSR 0x00002000 /* software soft reset */ 609 #define RSR_SWSR_SHIFT 13 610 #define RSR_SWHR 0x00001000 /* software hard reset */ 611 #define RSR_SWHR_SHIFT 12 612 #define RSR_JHRS 0x00000200 /* jtag hreset */ 613 #define RSR_JHRS_SHIFT 9 614 #define RSR_JSRS 0x00000100 /* jtag sreset status */ 615 #define RSR_JSRS_SHIFT 8 616 #define RSR_CSHR 0x00000010 /* checkstop reset status */ 617 #define RSR_CSHR_SHIFT 4 618 #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 619 #define RSR_SWRS_SHIFT 3 620 #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 621 #define RSR_BMRS_SHIFT 2 622 #define RSR_SRS 0x00000002 /* soft reset status */ 623 #define RSR_SRS_SHIFT 1 624 #define RSR_HRS 0x00000001 /* hard reset status */ 625 #define RSR_HRS_SHIFT 0 626 #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 627 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 628 RSR_BMRS | RSR_SRS | RSR_HRS) 629 /* RMR - Reset Mode Register 630 */ 631 #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 632 #define RMR_CSRE_SHIFT 0 633 #define RMR_RES ~(RMR_CSRE) 634 635 /* RCR - Reset Control Register 636 */ 637 #define RCR_SWHR 0x00000002 /* software hard reset */ 638 #define RCR_SWSR 0x00000001 /* software soft reset */ 639 #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 640 641 /* RCER - Reset Control Enable Register 642 */ 643 #define RCER_CRE 0x00000001 /* software hard reset */ 644 #define RCER_RES ~(RCER_CRE) 645 646 /* SPMR - System PLL Mode Register 647 */ 648 #define SPMR_LBIUCM 0x80000000 649 #define SPMR_DDRCM 0x40000000 650 #define SPMR_SPMF 0x0F000000 651 #define SPMR_CKID 0x00800000 652 #define SPMR_CKID_SHIFT 23 653 #define SPMR_COREPLL 0x007F0000 654 #define SPMR_CEVCOD 0x000000C0 655 #define SPMR_CEPDF 0x00000020 656 #define SPMR_CEPMF 0x0000001F 657 658 /* OCCR - Output Clock Control Register 659 */ 660 #define OCCR_PCICOE0 0x80000000 661 #define OCCR_PCICOE1 0x40000000 662 #define OCCR_PCICOE2 0x20000000 663 #define OCCR_PCICOE3 0x10000000 664 #define OCCR_PCICOE4 0x08000000 665 #define OCCR_PCICOE5 0x04000000 666 #define OCCR_PCICOE6 0x02000000 667 #define OCCR_PCICOE7 0x01000000 668 #define OCCR_PCICD0 0x00800000 669 #define OCCR_PCICD1 0x00400000 670 #define OCCR_PCICD2 0x00200000 671 #define OCCR_PCICD3 0x00100000 672 #define OCCR_PCICD4 0x00080000 673 #define OCCR_PCICD5 0x00040000 674 #define OCCR_PCICD6 0x00020000 675 #define OCCR_PCICD7 0x00010000 676 #define OCCR_PCI1CR 0x00000002 677 #define OCCR_PCI2CR 0x00000001 678 #define OCCR_PCICR OCCR_PCI1CR 679 680 /* SCCR - System Clock Control Register 681 */ 682 #define SCCR_ENCCM 0x03000000 683 #define SCCR_ENCCM_SHIFT 24 684 #define SCCR_ENCCM_0 0x00000000 685 #define SCCR_ENCCM_1 0x01000000 686 #define SCCR_ENCCM_2 0x02000000 687 #define SCCR_ENCCM_3 0x03000000 688 689 #define SCCR_PCICM 0x00010000 690 #define SCCR_PCICM_SHIFT 16 691 692 #if defined(CONFIG_MPC834x) 693 /* SCCR bits - MPC834x specific */ 694 #define SCCR_TSEC1CM 0xc0000000 695 #define SCCR_TSEC1CM_SHIFT 30 696 #define SCCR_TSEC1CM_0 0x00000000 697 #define SCCR_TSEC1CM_1 0x40000000 698 #define SCCR_TSEC1CM_2 0x80000000 699 #define SCCR_TSEC1CM_3 0xC0000000 700 701 #define SCCR_TSEC2CM 0x30000000 702 #define SCCR_TSEC2CM_SHIFT 28 703 #define SCCR_TSEC2CM_0 0x00000000 704 #define SCCR_TSEC2CM_1 0x10000000 705 #define SCCR_TSEC2CM_2 0x20000000 706 #define SCCR_TSEC2CM_3 0x30000000 707 708 /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 709 #define SCCR_USBMPHCM 0x00c00000 710 #define SCCR_USBMPHCM_SHIFT 22 711 #define SCCR_USBDRCM 0x00300000 712 #define SCCR_USBDRCM_SHIFT 20 713 #define SCCR_USBCM 0x00f00000 714 #define SCCR_USBCM_SHIFT 20 715 #define SCCR_USBCM_0 0x00000000 716 #define SCCR_USBCM_1 0x00500000 717 #define SCCR_USBCM_2 0x00A00000 718 #define SCCR_USBCM_3 0x00F00000 719 720 #elif defined(CONFIG_MPC8313) 721 /* TSEC1 bits are for TSEC2 as well */ 722 #define SCCR_TSEC1CM 0xc0000000 723 #define SCCR_TSEC1CM_SHIFT 30 724 #define SCCR_TSEC1CM_0 0x00000000 725 #define SCCR_TSEC1CM_1 0x40000000 726 #define SCCR_TSEC1CM_2 0x80000000 727 #define SCCR_TSEC1CM_3 0xC0000000 728 729 #define SCCR_TSEC1ON 0x20000000 730 #define SCCR_TSEC1ON_SHIFT 29 731 #define SCCR_TSEC2ON 0x10000000 732 #define SCCR_TSEC2ON_SHIFT 28 733 734 #define SCCR_USBDRCM 0x00300000 735 #define SCCR_USBDRCM_SHIFT 20 736 #define SCCR_USBDRCM_0 0x00000000 737 #define SCCR_USBDRCM_1 0x00100000 738 #define SCCR_USBDRCM_2 0x00200000 739 #define SCCR_USBDRCM_3 0x00300000 740 741 #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 742 /* SCCR bits - MPC8315/MPC8308 specific */ 743 #define SCCR_TSEC1CM 0xc0000000 744 #define SCCR_TSEC1CM_SHIFT 30 745 #define SCCR_TSEC1CM_0 0x00000000 746 #define SCCR_TSEC1CM_1 0x40000000 747 #define SCCR_TSEC1CM_2 0x80000000 748 #define SCCR_TSEC1CM_3 0xC0000000 749 750 #define SCCR_TSEC2CM 0x30000000 751 #define SCCR_TSEC2CM_SHIFT 28 752 #define SCCR_TSEC2CM_0 0x00000000 753 #define SCCR_TSEC2CM_1 0x10000000 754 #define SCCR_TSEC2CM_2 0x20000000 755 #define SCCR_TSEC2CM_3 0x30000000 756 757 #define SCCR_SDHCCM 0x0c000000 758 #define SCCR_SDHCCM_SHIFT 26 759 #define SCCR_SDHCCM_0 0x00000000 760 #define SCCR_SDHCCM_1 0x04000000 761 #define SCCR_SDHCCM_2 0x08000000 762 #define SCCR_SDHCCM_3 0x0c000000 763 764 #define SCCR_USBDRCM 0x00c00000 765 #define SCCR_USBDRCM_SHIFT 22 766 #define SCCR_USBDRCM_0 0x00000000 767 #define SCCR_USBDRCM_1 0x00400000 768 #define SCCR_USBDRCM_2 0x00800000 769 #define SCCR_USBDRCM_3 0x00c00000 770 771 #define SCCR_SATA1CM 0x00003000 772 #define SCCR_SATA1CM_SHIFT 12 773 #define SCCR_SATACM 0x00003c00 774 #define SCCR_SATACM_SHIFT 10 775 #define SCCR_SATACM_0 0x00000000 776 #define SCCR_SATACM_1 0x00001400 777 #define SCCR_SATACM_2 0x00002800 778 #define SCCR_SATACM_3 0x00003c00 779 780 #define SCCR_TDMCM 0x00000030 781 #define SCCR_TDMCM_SHIFT 4 782 #define SCCR_TDMCM_0 0x00000000 783 #define SCCR_TDMCM_1 0x00000010 784 #define SCCR_TDMCM_2 0x00000020 785 #define SCCR_TDMCM_3 0x00000030 786 787 #elif defined(CONFIG_MPC837x) 788 /* SCCR bits - MPC837x specific */ 789 #define SCCR_TSEC1CM 0xc0000000 790 #define SCCR_TSEC1CM_SHIFT 30 791 #define SCCR_TSEC1CM_0 0x00000000 792 #define SCCR_TSEC1CM_1 0x40000000 793 #define SCCR_TSEC1CM_2 0x80000000 794 #define SCCR_TSEC1CM_3 0xC0000000 795 796 #define SCCR_TSEC2CM 0x30000000 797 #define SCCR_TSEC2CM_SHIFT 28 798 #define SCCR_TSEC2CM_0 0x00000000 799 #define SCCR_TSEC2CM_1 0x10000000 800 #define SCCR_TSEC2CM_2 0x20000000 801 #define SCCR_TSEC2CM_3 0x30000000 802 803 #define SCCR_SDHCCM 0x0c000000 804 #define SCCR_SDHCCM_SHIFT 26 805 #define SCCR_SDHCCM_0 0x00000000 806 #define SCCR_SDHCCM_1 0x04000000 807 #define SCCR_SDHCCM_2 0x08000000 808 #define SCCR_SDHCCM_3 0x0c000000 809 810 #define SCCR_USBDRCM 0x00c00000 811 #define SCCR_USBDRCM_SHIFT 22 812 #define SCCR_USBDRCM_0 0x00000000 813 #define SCCR_USBDRCM_1 0x00400000 814 #define SCCR_USBDRCM_2 0x00800000 815 #define SCCR_USBDRCM_3 0x00c00000 816 817 /* All of the four SATA controllers must have the same clock ratio */ 818 #define SCCR_SATA1CM 0x000000c0 819 #define SCCR_SATA1CM_SHIFT 6 820 #define SCCR_SATACM 0x000000ff 821 #define SCCR_SATACM_SHIFT 0 822 #define SCCR_SATACM_0 0x00000000 823 #define SCCR_SATACM_1 0x00000055 824 #define SCCR_SATACM_2 0x000000aa 825 #define SCCR_SATACM_3 0x000000ff 826 #endif 827 828 #define SCCR_PCIEXP1CM 0x00300000 829 #define SCCR_PCIEXP1CM_SHIFT 20 830 #define SCCR_PCIEXP1CM_0 0x00000000 831 #define SCCR_PCIEXP1CM_1 0x00100000 832 #define SCCR_PCIEXP1CM_2 0x00200000 833 #define SCCR_PCIEXP1CM_3 0x00300000 834 835 #define SCCR_PCIEXP2CM 0x000c0000 836 #define SCCR_PCIEXP2CM_SHIFT 18 837 #define SCCR_PCIEXP2CM_0 0x00000000 838 #define SCCR_PCIEXP2CM_1 0x00040000 839 #define SCCR_PCIEXP2CM_2 0x00080000 840 #define SCCR_PCIEXP2CM_3 0x000c0000 841 842 /* CSn_BDNS - Chip Select memory Bounds Register 843 */ 844 #define CSBNDS_SA 0x00FF0000 845 #define CSBNDS_SA_SHIFT 8 846 #define CSBNDS_EA 0x000000FF 847 #define CSBNDS_EA_SHIFT 24 848 849 /* CSn_CONFIG - Chip Select Configuration Register 850 */ 851 #define CSCONFIG_EN 0x80000000 852 #define CSCONFIG_AP 0x00800000 853 #define CSCONFIG_ODT_WR_ACS 0x00010000 854 #if defined(CONFIG_MPC832x) 855 #define CSCONFIG_ODT_WR_CFG 0x00040000 856 #endif 857 #define CSCONFIG_BANK_BIT_3 0x00004000 858 #define CSCONFIG_ROW_BIT 0x00000700 859 #define CSCONFIG_ROW_BIT_12 0x00000000 860 #define CSCONFIG_ROW_BIT_13 0x00000100 861 #define CSCONFIG_ROW_BIT_14 0x00000200 862 #define CSCONFIG_COL_BIT 0x00000007 863 #define CSCONFIG_COL_BIT_8 0x00000000 864 #define CSCONFIG_COL_BIT_9 0x00000001 865 #define CSCONFIG_COL_BIT_10 0x00000002 866 #define CSCONFIG_COL_BIT_11 0x00000003 867 868 /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 869 */ 870 #define TIMING_CFG0_RWT 0xC0000000 871 #define TIMING_CFG0_RWT_SHIFT 30 872 #define TIMING_CFG0_WRT 0x30000000 873 #define TIMING_CFG0_WRT_SHIFT 28 874 #define TIMING_CFG0_RRT 0x0C000000 875 #define TIMING_CFG0_RRT_SHIFT 26 876 #define TIMING_CFG0_WWT 0x03000000 877 #define TIMING_CFG0_WWT_SHIFT 24 878 #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 879 #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 880 #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 881 #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 882 #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 883 #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 884 #define TIMING_CFG0_MRS_CYC 0x0000000F 885 #define TIMING_CFG0_MRS_CYC_SHIFT 0 886 887 /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 888 */ 889 #define TIMING_CFG1_PRETOACT 0x70000000 890 #define TIMING_CFG1_PRETOACT_SHIFT 28 891 #define TIMING_CFG1_ACTTOPRE 0x0F000000 892 #define TIMING_CFG1_ACTTOPRE_SHIFT 24 893 #define TIMING_CFG1_ACTTORW 0x00700000 894 #define TIMING_CFG1_ACTTORW_SHIFT 20 895 #define TIMING_CFG1_CASLAT 0x00070000 896 #define TIMING_CFG1_CASLAT_SHIFT 16 897 #define TIMING_CFG1_REFREC 0x0000F000 898 #define TIMING_CFG1_REFREC_SHIFT 12 899 #define TIMING_CFG1_WRREC 0x00000700 900 #define TIMING_CFG1_WRREC_SHIFT 8 901 #define TIMING_CFG1_ACTTOACT 0x00000070 902 #define TIMING_CFG1_ACTTOACT_SHIFT 4 903 #define TIMING_CFG1_WRTORD 0x00000007 904 #define TIMING_CFG1_WRTORD_SHIFT 0 905 #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 906 #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 907 #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ 908 #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ 909 #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ 910 #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ 911 #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ 912 913 /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 914 */ 915 #define TIMING_CFG2_CPO 0x0F800000 916 #define TIMING_CFG2_CPO_SHIFT 23 917 #define TIMING_CFG2_ACSM 0x00080000 918 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 919 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 920 #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 921 922 #define TIMING_CFG2_ADD_LAT 0x70000000 923 #define TIMING_CFG2_ADD_LAT_SHIFT 28 924 #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 925 #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 926 #define TIMING_CFG2_RD_TO_PRE 0x0000E000 927 #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 928 #define TIMING_CFG2_CKE_PLS 0x000001C0 929 #define TIMING_CFG2_CKE_PLS_SHIFT 6 930 #define TIMING_CFG2_FOUR_ACT 0x0000003F 931 #define TIMING_CFG2_FOUR_ACT_SHIFT 0 932 933 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 934 */ 935 #define SDRAM_CFG_MEM_EN 0x80000000 936 #define SDRAM_CFG_SREN 0x40000000 937 #define SDRAM_CFG_ECC_EN 0x20000000 938 #define SDRAM_CFG_RD_EN 0x10000000 939 #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 940 #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 941 #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 942 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 943 #define SDRAM_CFG_DYN_PWR 0x00200000 944 #define SDRAM_CFG_32_BE 0x00080000 945 #define SDRAM_CFG_8_BE 0x00040000 946 #define SDRAM_CFG_NCAP 0x00020000 947 #define SDRAM_CFG_2T_EN 0x00008000 948 #define SDRAM_CFG_BI 0x00000001 949 950 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 951 */ 952 #define SDRAM_MODE_ESD 0xFFFF0000 953 #define SDRAM_MODE_ESD_SHIFT 16 954 #define SDRAM_MODE_SD 0x0000FFFF 955 #define SDRAM_MODE_SD_SHIFT 0 956 #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 957 #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 958 #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 959 #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 960 #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 961 #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 962 #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 963 #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 964 #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 965 #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 966 #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 967 #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 968 #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 969 #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 970 #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 971 #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 972 #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 973 #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 974 #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 975 976 /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 977 */ 978 #define SDRAM_INTERVAL_REFINT 0x3FFF0000 979 #define SDRAM_INTERVAL_REFINT_SHIFT 16 980 #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 981 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 982 983 /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 984 */ 985 #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 986 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 987 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 988 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 989 #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 990 991 /* ECC_ERR_INJECT - Memory data path error injection mask ECC 992 */ 993 #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 994 #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 995 #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 996 #define ECC_ERR_INJECT_EEIM_SHIFT 0 997 998 /* CAPTURE_ECC - Memory data path read capture ECC 999 */ 1000 #define CAPTURE_ECC_ECE (0xff000000>>24) 1001 #define CAPTURE_ECC_ECE_SHIFT 0 1002 1003 /* ERR_DETECT - Memory error detect 1004 */ 1005 #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 1006 #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 1007 #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 1008 #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 1009 1010 /* ERR_DISABLE - Memory error disable 1011 */ 1012 #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 1013 #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 1014 #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 1015 #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 1016 ECC_ERROR_DISABLE_MBED) 1017 /* ERR_INT_EN - Memory error interrupt enable 1018 */ 1019 #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 1020 #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 1021 #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 1022 #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 1023 ECC_ERR_INT_EN_MSEE) 1024 /* CAPTURE_ATTRIBUTES - Memory error attributes capture 1025 */ 1026 #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 1027 #define ECC_CAPT_ATTR_BNUM_SHIFT 28 1028 #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 1029 #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 1030 #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 1031 #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1032 #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1033 #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 1034 #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 1035 #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1036 #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1037 #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1038 #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1039 #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1040 #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1041 #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1042 #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1043 #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1044 #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1045 #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1046 #define ECC_CAPT_ATTR_TSRC_SHIFT 16 1047 #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 1048 #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1049 #define ECC_CAPT_ATTR_TTYP_READ 0x2 1050 #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1051 #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1052 #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 1053 1054 /* ERR_SBE - Single bit ECC memory error management 1055 */ 1056 #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 1057 #define ECC_ERROR_MAN_SBET_SHIFT 16 1058 #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 1059 #define ECC_ERROR_MAN_SBEC_SHIFT 0 1060 1061 /* CONFIG_ADDRESS - PCI Config Address Register 1062 */ 1063 #define PCI_CONFIG_ADDRESS_EN 0x80000000 1064 #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1065 #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1066 #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1067 #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1068 #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1069 #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1070 #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1071 #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1072 1073 /* POTAR - PCI Outbound Translation Address Register 1074 */ 1075 #define POTAR_TA_MASK 0x000fffff 1076 1077 /* POBAR - PCI Outbound Base Address Register 1078 */ 1079 #define POBAR_BA_MASK 0x000fffff 1080 1081 /* POCMR - PCI Outbound Comparision Mask Register 1082 */ 1083 #define POCMR_EN 0x80000000 1084 #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1085 #define POCMR_SE 0x20000000 /* streaming enable */ 1086 #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1087 #define POCMR_CM_MASK 0x000fffff 1088 #define POCMR_CM_4G 0x00000000 1089 #define POCMR_CM_2G 0x00080000 1090 #define POCMR_CM_1G 0x000C0000 1091 #define POCMR_CM_512M 0x000E0000 1092 #define POCMR_CM_256M 0x000F0000 1093 #define POCMR_CM_128M 0x000F8000 1094 #define POCMR_CM_64M 0x000FC000 1095 #define POCMR_CM_32M 0x000FE000 1096 #define POCMR_CM_16M 0x000FF000 1097 #define POCMR_CM_8M 0x000FF800 1098 #define POCMR_CM_4M 0x000FFC00 1099 #define POCMR_CM_2M 0x000FFE00 1100 #define POCMR_CM_1M 0x000FFF00 1101 #define POCMR_CM_512K 0x000FFF80 1102 #define POCMR_CM_256K 0x000FFFC0 1103 #define POCMR_CM_128K 0x000FFFE0 1104 #define POCMR_CM_64K 0x000FFFF0 1105 #define POCMR_CM_32K 0x000FFFF8 1106 #define POCMR_CM_16K 0x000FFFFC 1107 #define POCMR_CM_8K 0x000FFFFE 1108 #define POCMR_CM_4K 0x000FFFFF 1109 1110 /* PITAR - PCI Inbound Translation Address Register 1111 */ 1112 #define PITAR_TA_MASK 0x000fffff 1113 1114 /* PIBAR - PCI Inbound Base/Extended Address Register 1115 */ 1116 #define PIBAR_MASK 0xffffffff 1117 #define PIEBAR_EBA_MASK 0x000fffff 1118 1119 /* PIWAR - PCI Inbound Windows Attributes Register 1120 */ 1121 #define PIWAR_EN 0x80000000 1122 #define PIWAR_PF 0x20000000 1123 #define PIWAR_RTT_MASK 0x000f0000 1124 #define PIWAR_RTT_NO_SNOOP 0x00040000 1125 #define PIWAR_RTT_SNOOP 0x00050000 1126 #define PIWAR_WTT_MASK 0x0000f000 1127 #define PIWAR_WTT_NO_SNOOP 0x00004000 1128 #define PIWAR_WTT_SNOOP 0x00005000 1129 #define PIWAR_IWS_MASK 0x0000003F 1130 #define PIWAR_IWS_4K 0x0000000B 1131 #define PIWAR_IWS_8K 0x0000000C 1132 #define PIWAR_IWS_16K 0x0000000D 1133 #define PIWAR_IWS_32K 0x0000000E 1134 #define PIWAR_IWS_64K 0x0000000F 1135 #define PIWAR_IWS_128K 0x00000010 1136 #define PIWAR_IWS_256K 0x00000011 1137 #define PIWAR_IWS_512K 0x00000012 1138 #define PIWAR_IWS_1M 0x00000013 1139 #define PIWAR_IWS_2M 0x00000014 1140 #define PIWAR_IWS_4M 0x00000015 1141 #define PIWAR_IWS_8M 0x00000016 1142 #define PIWAR_IWS_16M 0x00000017 1143 #define PIWAR_IWS_32M 0x00000018 1144 #define PIWAR_IWS_64M 0x00000019 1145 #define PIWAR_IWS_128M 0x0000001A 1146 #define PIWAR_IWS_256M 0x0000001B 1147 #define PIWAR_IWS_512M 0x0000001C 1148 #define PIWAR_IWS_1G 0x0000001D 1149 #define PIWAR_IWS_2G 0x0000001E 1150 1151 /* PMCCR1 - PCI Configuration Register 1 1152 */ 1153 #define PMCCR1_POWER_OFF 0x00000020 1154 1155 /* DDRCDR - DDR Control Driver Register 1156 */ 1157 #define DDRCDR_DHC_EN 0x80000000 1158 #define DDRCDR_EN 0x40000000 1159 #define DDRCDR_PZ 0x3C000000 1160 #define DDRCDR_PZ_MAXZ 0x00000000 1161 #define DDRCDR_PZ_HIZ 0x20000000 1162 #define DDRCDR_PZ_NOMZ 0x30000000 1163 #define DDRCDR_PZ_LOZ 0x38000000 1164 #define DDRCDR_PZ_MINZ 0x3C000000 1165 #define DDRCDR_NZ 0x3C000000 1166 #define DDRCDR_NZ_MAXZ 0x00000000 1167 #define DDRCDR_NZ_HIZ 0x02000000 1168 #define DDRCDR_NZ_NOMZ 0x03000000 1169 #define DDRCDR_NZ_LOZ 0x03800000 1170 #define DDRCDR_NZ_MINZ 0x03C00000 1171 #define DDRCDR_ODT 0x00080000 1172 #define DDRCDR_DDR_CFG 0x00040000 1173 #define DDRCDR_M_ODR 0x00000002 1174 #define DDRCDR_Q_DRN 0x00000001 1175 1176 /* PCIE Bridge Register 1177 */ 1178 #define PEX_CSB_CTRL_OBPIOE 0x00000001 1179 #define PEX_CSB_CTRL_IBPIOE 0x00000002 1180 #define PEX_CSB_CTRL_WDMAE 0x00000004 1181 #define PEX_CSB_CTRL_RDMAE 0x00000008 1182 1183 #define PEX_CSB_OBCTRL_PIOE 0x00000001 1184 #define PEX_CSB_OBCTRL_MEMWE 0x00000002 1185 #define PEX_CSB_OBCTRL_IOWE 0x00000004 1186 #define PEX_CSB_OBCTRL_CFGWE 0x00000008 1187 1188 #define PEX_CSB_IBCTRL_PIOE 0x00000001 1189 1190 #define PEX_OWAR_EN 0x00000001 1191 #define PEX_OWAR_TYPE_CFG 0x00000000 1192 #define PEX_OWAR_TYPE_IO 0x00000002 1193 #define PEX_OWAR_TYPE_MEM 0x00000004 1194 #define PEX_OWAR_RLXO 0x00000008 1195 #define PEX_OWAR_NANP 0x00000010 1196 #define PEX_OWAR_SIZE 0xFFFFF000 1197 1198 #define PEX_IWAR_EN 0x00000001 1199 #define PEX_IWAR_TYPE_INT 0x00000000 1200 #define PEX_IWAR_TYPE_PF 0x00000004 1201 #define PEX_IWAR_TYPE_NO_PF 0x00000006 1202 #define PEX_IWAR_NSOV 0x00000008 1203 #define PEX_IWAR_NSNP 0x00000010 1204 #define PEX_IWAR_SIZE 0xFFFFF000 1205 #define PEX_IWAR_SIZE_1M 0x000FF000 1206 #define PEX_IWAR_SIZE_2M 0x001FF000 1207 #define PEX_IWAR_SIZE_4M 0x003FF000 1208 #define PEX_IWAR_SIZE_8M 0x007FF000 1209 #define PEX_IWAR_SIZE_16M 0x00FFF000 1210 #define PEX_IWAR_SIZE_32M 0x01FFF000 1211 #define PEX_IWAR_SIZE_64M 0x03FFF000 1212 #define PEX_IWAR_SIZE_128M 0x07FFF000 1213 #define PEX_IWAR_SIZE_256M 0x0FFFF000 1214 1215 #define PEX_GCLK_RATIO 0x440 1216 1217 #ifndef __ASSEMBLY__ 1218 struct pci_region; 1219 void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 1220 void mpc83xx_pcislave_unlock(int bus); 1221 void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot); 1222 #endif 1223 1224 #endif /* __MPC83XX_H__ */ 1225