1f046ccd1SEran Liberty /* 27c619ddcSIlya Yanok * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty */ 12f046ccd1SEran Liberty 13f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 14f046ccd1SEran Liberty #define __MPC83XX_H__ 15f046ccd1SEran Liberty 16f6eda7f8SDave Liu #include <config.h> 17bf30bb1fSAnton Vorontsov #include <asm/fsl_lbc.h> 18f046ccd1SEran Liberty #if defined(CONFIG_E300) 19f046ccd1SEran Liberty #include <asm/e300.h> 20f046ccd1SEran Liberty #endif 21f046ccd1SEran Liberty 224e8b750cSHeiko Schocher /* 234e8b750cSHeiko Schocher * MPC83xx cpu provide RCR register to do reset thing specially 24f046ccd1SEran Liberty */ 25f046ccd1SEran Liberty #define MPC83xx_RESET 26f046ccd1SEran Liberty 274e8b750cSHeiko Schocher /* 284e8b750cSHeiko Schocher * System reset offset (PowerPC standard) 29f046ccd1SEran Liberty */ 30f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 3102032e8fSRafal Jaworowski #define _START_OFFSET EXC_OFF_SYS_RESET 32f046ccd1SEran Liberty 334e8b750cSHeiko Schocher /* 344e8b750cSHeiko Schocher * IMMRBAR - Internal Memory Register Base Address 35f046ccd1SEran Liberty */ 36e4c09508SScott Wood #ifndef CONFIG_DEFAULT_IMMR 374e8b750cSHeiko Schocher /* Default IMMR base address */ 384e8b750cSHeiko Schocher #define CONFIG_DEFAULT_IMMR 0xFF400000 39e4c09508SScott Wood #endif 404e8b750cSHeiko Schocher /* Register offset to immr */ 414e8b750cSHeiko Schocher #define IMMRBAR 0x0000 424e8b750cSHeiko Schocher #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */ 43f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 44f046ccd1SEran Liberty 454e8b750cSHeiko Schocher /* 464e8b750cSHeiko Schocher * LAWBAR - Local Access Window Base Address Register 47f046ccd1SEran Liberty */ 484e8b750cSHeiko Schocher /* Register offset to immr */ 494e8b750cSHeiko Schocher #define LBLAWBAR0 0x0020 50f046ccd1SEran Liberty #define LBLAWAR0 0x0024 51f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 52f046ccd1SEran Liberty #define LBLAWAR1 0x002C 53f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 54f046ccd1SEran Liberty #define LBLAWAR2 0x0034 55f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 56f046ccd1SEran Liberty #define LBLAWAR3 0x003C 574e8b750cSHeiko Schocher #define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */ 58f046ccd1SEran Liberty 594e8b750cSHeiko Schocher /* 604e8b750cSHeiko Schocher * SPRIDR - System Part and Revision ID Register 61f6eda7f8SDave Liu */ 62e5c4ade4SKim Phillips #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ 63e5c4ade4SKim Phillips #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ 64e080313cSDave Liu 652c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 66e5c4ade4SKim Phillips #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) 67e5c4ade4SKim Phillips #define REVID_MINOR(spridr) (spridr & 0x000000FF) 68e5c4ade4SKim Phillips #else 69e5c4ade4SKim Phillips #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) 70e5c4ade4SKim Phillips #define REVID_MINOR(spridr) (spridr & 0x0000000F) 71e5c4ade4SKim Phillips #endif 725f820439SDave Liu 73e5c4ade4SKim Phillips #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) 746b70ffb9SKim Phillips #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) 755f820439SDave Liu 767c619ddcSIlya Yanok #define SPR_8308 0x8100 776b70ffb9SKim Phillips #define SPR_831X_FAMILY 0x80B 78e5c4ade4SKim Phillips #define SPR_8311 0x80B2 79e5c4ade4SKim Phillips #define SPR_8313 0x80B0 80e5c4ade4SKim Phillips #define SPR_8314 0x80B6 81e5c4ade4SKim Phillips #define SPR_8315 0x80B4 826b70ffb9SKim Phillips #define SPR_832X_FAMILY 0x806 83e5c4ade4SKim Phillips #define SPR_8321 0x8066 84e5c4ade4SKim Phillips #define SPR_8323 0x8062 856b70ffb9SKim Phillips #define SPR_834X_FAMILY 0x803 86e5c4ade4SKim Phillips #define SPR_8343 0x8036 87e5c4ade4SKim Phillips #define SPR_8347_TBGA_ 0x8032 88e5c4ade4SKim Phillips #define SPR_8347_PBGA_ 0x8034 89e5c4ade4SKim Phillips #define SPR_8349 0x8030 906b70ffb9SKim Phillips #define SPR_836X_FAMILY 0x804 91e5c4ade4SKim Phillips #define SPR_8358_TBGA_ 0x804A 92e5c4ade4SKim Phillips #define SPR_8358_PBGA_ 0x804E 93e5c4ade4SKim Phillips #define SPR_8360 0x8048 946b70ffb9SKim Phillips #define SPR_837X_FAMILY 0x80C 95e5c4ade4SKim Phillips #define SPR_8377 0x80C6 96e5c4ade4SKim Phillips #define SPR_8378 0x80C4 97e5c4ade4SKim Phillips #define SPR_8379 0x80C2 98d87c57b2SScott Wood 994e8b750cSHeiko Schocher /* 1004e8b750cSHeiko Schocher * SPCR - System Priority Configuration Register 101f046ccd1SEran Liberty */ 1024e8b750cSHeiko Schocher /* PCI Highest Priority Enable */ 1034e8b750cSHeiko Schocher #define SPCR_PCIHPE 0x10000000 104e080313cSDave Liu #define SPCR_PCIHPE_SHIFT (31-3) 1054e8b750cSHeiko Schocher /* PCI bridge system bus request priority */ 1064e8b750cSHeiko Schocher #define SPCR_PCIPR 0x03000000 107e080313cSDave Liu #define SPCR_PCIPR_SHIFT (31-7) 108e080313cSDave Liu #define SPCR_OPT 0x00800000 /* Optimize */ 1095bbeea86SMichael Barkowski #define SPCR_OPT_SHIFT (31-8) 1104e8b750cSHeiko Schocher /* E300 PowerPC core time base unit enable */ 1114e8b750cSHeiko Schocher #define SPCR_TBEN 0x00400000 112e080313cSDave Liu #define SPCR_TBEN_SHIFT (31-9) 1134e8b750cSHeiko Schocher /* E300 PowerPC Core system bus request priority */ 1144e8b750cSHeiko Schocher #define SPCR_COREPR 0x00300000 115e080313cSDave Liu #define SPCR_COREPR_SHIFT (31-11) 116e080313cSDave Liu 1172c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 118e080313cSDave Liu /* SPCR bits - MPC8349 specific */ 1194e8b750cSHeiko Schocher /* TSEC1 data priority */ 1204e8b750cSHeiko Schocher #define SPCR_TSEC1DP 0x00003000 121e080313cSDave Liu #define SPCR_TSEC1DP_SHIFT (31-19) 1224e8b750cSHeiko Schocher /* TSEC1 buffer descriptor priority */ 1234e8b750cSHeiko Schocher #define SPCR_TSEC1BDP 0x00000C00 124e080313cSDave Liu #define SPCR_TSEC1BDP_SHIFT (31-21) 1254e8b750cSHeiko Schocher /* TSEC1 emergency priority */ 1264e8b750cSHeiko Schocher #define SPCR_TSEC1EP 0x00000300 127e080313cSDave Liu #define SPCR_TSEC1EP_SHIFT (31-23) 1284e8b750cSHeiko Schocher /* TSEC2 data priority */ 1294e8b750cSHeiko Schocher #define SPCR_TSEC2DP 0x00000030 130e080313cSDave Liu #define SPCR_TSEC2DP_SHIFT (31-27) 1314e8b750cSHeiko Schocher /* TSEC2 buffer descriptor priority */ 1324e8b750cSHeiko Schocher #define SPCR_TSEC2BDP 0x0000000C 133e080313cSDave Liu #define SPCR_TSEC2BDP_SHIFT (31-29) 1344e8b750cSHeiko Schocher /* TSEC2 emergency priority */ 1354e8b750cSHeiko Schocher #define SPCR_TSEC2EP 0x00000003 136e080313cSDave Liu #define SPCR_TSEC2EP_SHIFT (31-31) 137d87c57b2SScott Wood 1387c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 1397c619ddcSIlya Yanok defined(CONFIG_MPC837x) 1407c619ddcSIlya Yanok /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ 1414e8b750cSHeiko Schocher /* TSEC data priority */ 1424e8b750cSHeiko Schocher #define SPCR_TSECDP 0x00003000 143d87c57b2SScott Wood #define SPCR_TSECDP_SHIFT (31-19) 1444e8b750cSHeiko Schocher /* TSEC buffer descriptor priority */ 1454e8b750cSHeiko Schocher #define SPCR_TSECBDP 0x00000C00 146ec2638eaSDave Liu #define SPCR_TSECBDP_SHIFT (31-21) 1474e8b750cSHeiko Schocher /* TSEC emergency priority */ 1484e8b750cSHeiko Schocher #define SPCR_TSECEP 0x00000300 149ec2638eaSDave Liu #define SPCR_TSECEP_SHIFT (31-23) 150e080313cSDave Liu #endif 151e080313cSDave Liu 152e080313cSDave Liu /* SICRL/H - System I/O Configuration Register Low/High 153e080313cSDave Liu */ 1542c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 155e080313cSDave Liu /* SICRL bits - MPC8349 specific */ 156e080313cSDave Liu #define SICRL_LDP_A 0x80000000 157e080313cSDave Liu #define SICRL_USB1 0x40000000 158e080313cSDave Liu #define SICRL_USB0 0x20000000 159e080313cSDave Liu #define SICRL_UART 0x0C000000 160e080313cSDave Liu #define SICRL_GPIO1_A 0x02000000 161e080313cSDave Liu #define SICRL_GPIO1_B 0x01000000 162e080313cSDave Liu #define SICRL_GPIO1_C 0x00800000 163e080313cSDave Liu #define SICRL_GPIO1_D 0x00400000 164e080313cSDave Liu #define SICRL_GPIO1_E 0x00200000 165e080313cSDave Liu #define SICRL_GPIO1_F 0x00180000 166e080313cSDave Liu #define SICRL_GPIO1_G 0x00040000 167e080313cSDave Liu #define SICRL_GPIO1_H 0x00020000 168e080313cSDave Liu #define SICRL_GPIO1_I 0x00010000 169e080313cSDave Liu #define SICRL_GPIO1_J 0x00008000 170e080313cSDave Liu #define SICRL_GPIO1_K 0x00004000 171e080313cSDave Liu #define SICRL_GPIO1_L 0x00003000 172e080313cSDave Liu 173e080313cSDave Liu /* SICRH bits - MPC8349 specific */ 174e080313cSDave Liu #define SICRH_DDR 0x80000000 175e080313cSDave Liu #define SICRH_TSEC1_A 0x10000000 176e080313cSDave Liu #define SICRH_TSEC1_B 0x08000000 177e080313cSDave Liu #define SICRH_TSEC1_C 0x04000000 178e080313cSDave Liu #define SICRH_TSEC1_D 0x02000000 179e080313cSDave Liu #define SICRH_TSEC1_E 0x01000000 180e080313cSDave Liu #define SICRH_TSEC1_F 0x00800000 181e080313cSDave Liu #define SICRH_TSEC2_A 0x00400000 182e080313cSDave Liu #define SICRH_TSEC2_B 0x00200000 183e080313cSDave Liu #define SICRH_TSEC2_C 0x00100000 184e080313cSDave Liu #define SICRH_TSEC2_D 0x00080000 185e080313cSDave Liu #define SICRH_TSEC2_E 0x00040000 186e080313cSDave Liu #define SICRH_TSEC2_F 0x00020000 187e080313cSDave Liu #define SICRH_TSEC2_G 0x00010000 188e080313cSDave Liu #define SICRH_TSEC2_H 0x00008000 189e080313cSDave Liu #define SICRH_GPIO2_A 0x00004000 190e080313cSDave Liu #define SICRH_GPIO2_B 0x00002000 191e080313cSDave Liu #define SICRH_GPIO2_C 0x00001000 192e080313cSDave Liu #define SICRH_GPIO2_D 0x00000800 193e080313cSDave Liu #define SICRH_GPIO2_E 0x00000400 194e080313cSDave Liu #define SICRH_GPIO2_F 0x00000200 195e080313cSDave Liu #define SICRH_GPIO2_G 0x00000180 196e080313cSDave Liu #define SICRH_GPIO2_H 0x00000060 197e080313cSDave Liu #define SICRH_TSOBI1 0x00000002 198e080313cSDave Liu #define SICRH_TSOBI2 0x00000001 199e080313cSDave Liu 200e080313cSDave Liu #elif defined(CONFIG_MPC8360) 201e080313cSDave Liu /* SICRL bits - MPC8360 specific */ 202e080313cSDave Liu #define SICRL_LDP_A 0xC0000000 203e080313cSDave Liu #define SICRL_LCLK_1 0x10000000 204e080313cSDave Liu #define SICRL_LCLK_2 0x08000000 205e080313cSDave Liu #define SICRL_SRCID_A 0x03000000 206e080313cSDave Liu #define SICRL_IRQ_CKSTP_A 0x00C00000 207e080313cSDave Liu 208e080313cSDave Liu /* SICRH bits - MPC8360 specific */ 209e080313cSDave Liu #define SICRH_DDR 0x80000000 210e080313cSDave Liu #define SICRH_SECONDARY_DDR 0x40000000 211e080313cSDave Liu #define SICRH_SDDROE 0x20000000 212e080313cSDave Liu #define SICRH_IRQ3 0x10000000 213e080313cSDave Liu #define SICRH_UC1EOBI 0x00000004 214e080313cSDave Liu #define SICRH_UC2E1OBI 0x00000002 215e080313cSDave Liu #define SICRH_UC2E2OBI 0x00000001 21624c3aca3SDave Liu 2172c7920afSPeter Tyser #elif defined(CONFIG_MPC832x) 2182c7920afSPeter Tyser /* SICRL bits - MPC832x specific */ 21924c3aca3SDave Liu #define SICRL_LDP_LCS_A 0x80000000 22024c3aca3SDave Liu #define SICRL_IRQ_CKS 0x20000000 22124c3aca3SDave Liu #define SICRL_PCI_MSRC 0x10000000 22224c3aca3SDave Liu #define SICRL_URT_CTPR 0x06000000 22324c3aca3SDave Liu #define SICRL_IRQ_CTPR 0x00C00000 224d87c57b2SScott Wood 225555da617SDave Liu #elif defined(CONFIG_MPC8313) 226555da617SDave Liu /* SICRL bits - MPC8313 specific */ 227d87c57b2SScott Wood #define SICRL_LBC 0x30000000 228d87c57b2SScott Wood #define SICRL_UART 0x0C000000 229d87c57b2SScott Wood #define SICRL_SPI_A 0x03000000 230d87c57b2SScott Wood #define SICRL_SPI_B 0x00C00000 231d87c57b2SScott Wood #define SICRL_SPI_C 0x00300000 232d87c57b2SScott Wood #define SICRL_SPI_D 0x000C0000 233f986325dSRon Madrid #define SICRL_USBDR_11 0x00000C00 234f986325dSRon Madrid #define SICRL_USBDR_10 0x00000800 235f986325dSRon Madrid #define SICRL_USBDR_01 0x00000400 236f986325dSRon Madrid #define SICRL_USBDR_00 0x00000000 237d87c57b2SScott Wood #define SICRL_ETSEC1_A 0x0000000C 238d87c57b2SScott Wood #define SICRL_ETSEC2_A 0x00000003 239d87c57b2SScott Wood 240555da617SDave Liu /* SICRH bits - MPC8313 specific */ 241d87c57b2SScott Wood #define SICRH_INTR_A 0x02000000 242d87c57b2SScott Wood #define SICRH_INTR_B 0x00C00000 243d87c57b2SScott Wood #define SICRH_IIC 0x00300000 244d87c57b2SScott Wood #define SICRH_ETSEC2_B 0x000C0000 245d87c57b2SScott Wood #define SICRH_ETSEC2_C 0x00030000 246d87c57b2SScott Wood #define SICRH_ETSEC2_D 0x0000C000 247d87c57b2SScott Wood #define SICRH_ETSEC2_E 0x00003000 248d87c57b2SScott Wood #define SICRH_ETSEC2_F 0x00000C00 249d87c57b2SScott Wood #define SICRH_ETSEC2_G 0x00000300 250d87c57b2SScott Wood #define SICRH_ETSEC1_B 0x00000080 251d87c57b2SScott Wood #define SICRH_ETSEC1_C 0x00000060 252d87c57b2SScott Wood #define SICRH_GTX1_DLY 0x00000008 253d87c57b2SScott Wood #define SICRH_GTX2_DLY 0x00000004 254d87c57b2SScott Wood #define SICRH_TSOBI1 0x00000002 255d87c57b2SScott Wood #define SICRH_TSOBI2 0x00000001 256d87c57b2SScott Wood 257555da617SDave Liu #elif defined(CONFIG_MPC8315) 258555da617SDave Liu /* SICRL bits - MPC8315 specific */ 259555da617SDave Liu #define SICRL_DMA_CH0 0xc0000000 260555da617SDave Liu #define SICRL_DMA_SPI 0x30000000 261555da617SDave Liu #define SICRL_UART 0x0c000000 262555da617SDave Liu #define SICRL_IRQ4 0x02000000 263555da617SDave Liu #define SICRL_IRQ5 0x01800000 264555da617SDave Liu #define SICRL_IRQ6_7 0x00400000 265555da617SDave Liu #define SICRL_IIC1 0x00300000 266555da617SDave Liu #define SICRL_TDM 0x000c0000 267555da617SDave Liu #define SICRL_TDM_SHARED 0x00030000 268555da617SDave Liu #define SICRL_PCI_A 0x0000c000 269555da617SDave Liu #define SICRL_ELBC_A 0x00003000 270555da617SDave Liu #define SICRL_ETSEC1_A 0x000000c0 271555da617SDave Liu #define SICRL_ETSEC1_B 0x00000030 272555da617SDave Liu #define SICRL_ETSEC1_C 0x0000000c 273555da617SDave Liu #define SICRL_TSEXPOBI 0x00000001 274555da617SDave Liu 275555da617SDave Liu /* SICRH bits - MPC8315 specific */ 276555da617SDave Liu #define SICRH_GPIO_0 0xc0000000 277555da617SDave Liu #define SICRH_GPIO_1 0x30000000 278555da617SDave Liu #define SICRH_GPIO_2 0x0c000000 279555da617SDave Liu #define SICRH_GPIO_3 0x03000000 280555da617SDave Liu #define SICRH_GPIO_4 0x00c00000 281555da617SDave Liu #define SICRH_GPIO_5 0x00300000 282555da617SDave Liu #define SICRH_GPIO_6 0x000c0000 283555da617SDave Liu #define SICRH_GPIO_7 0x00030000 284555da617SDave Liu #define SICRH_GPIO_8 0x0000c000 285555da617SDave Liu #define SICRH_GPIO_9 0x00003000 286555da617SDave Liu #define SICRH_GPIO_10 0x00000c00 287555da617SDave Liu #define SICRH_GPIO_11 0x00000300 288555da617SDave Liu #define SICRH_ETSEC2_A 0x000000c0 289555da617SDave Liu #define SICRH_TSOBI1 0x00000002 290555da617SDave Liu #define SICRH_TSOBI2 0x00000001 291555da617SDave Liu 2922c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 29303051c3dSDave Liu /* SICRL bits - MPC837x specific */ 29403051c3dSDave Liu #define SICRL_USB_A 0xC0000000 29503051c3dSDave Liu #define SICRL_USB_B 0x30000000 296e1ac387fSAndy Fleming #define SICRL_USB_B_SD 0x20000000 29703051c3dSDave Liu #define SICRL_UART 0x0C000000 29803051c3dSDave Liu #define SICRL_GPIO_A 0x02000000 29903051c3dSDave Liu #define SICRL_GPIO_B 0x01000000 30003051c3dSDave Liu #define SICRL_GPIO_C 0x00800000 30103051c3dSDave Liu #define SICRL_GPIO_D 0x00400000 30203051c3dSDave Liu #define SICRL_GPIO_E 0x00200000 30303051c3dSDave Liu #define SICRL_GPIO_F 0x00180000 30403051c3dSDave Liu #define SICRL_GPIO_G 0x00040000 30503051c3dSDave Liu #define SICRL_GPIO_H 0x00020000 30603051c3dSDave Liu #define SICRL_GPIO_I 0x00010000 30703051c3dSDave Liu #define SICRL_GPIO_J 0x00008000 30803051c3dSDave Liu #define SICRL_GPIO_K 0x00004000 30903051c3dSDave Liu #define SICRL_GPIO_L 0x00003000 31003051c3dSDave Liu #define SICRL_DMA_A 0x00000800 31103051c3dSDave Liu #define SICRL_DMA_B 0x00000400 31203051c3dSDave Liu #define SICRL_DMA_C 0x00000200 31303051c3dSDave Liu #define SICRL_DMA_D 0x00000100 31403051c3dSDave Liu #define SICRL_DMA_E 0x00000080 31503051c3dSDave Liu #define SICRL_DMA_F 0x00000040 31603051c3dSDave Liu #define SICRL_DMA_G 0x00000020 31703051c3dSDave Liu #define SICRL_DMA_H 0x00000010 31803051c3dSDave Liu #define SICRL_DMA_I 0x00000008 31903051c3dSDave Liu #define SICRL_DMA_J 0x00000004 32003051c3dSDave Liu #define SICRL_LDP_A 0x00000002 32103051c3dSDave Liu #define SICRL_LDP_B 0x00000001 32203051c3dSDave Liu 32303051c3dSDave Liu /* SICRH bits - MPC837x specific */ 32403051c3dSDave Liu #define SICRH_DDR 0x80000000 32503051c3dSDave Liu #define SICRH_TSEC1_A 0x10000000 32603051c3dSDave Liu #define SICRH_TSEC1_B 0x08000000 32703051c3dSDave Liu #define SICRH_TSEC2_A 0x00400000 32803051c3dSDave Liu #define SICRH_TSEC2_B 0x00200000 32903051c3dSDave Liu #define SICRH_TSEC2_C 0x00100000 33003051c3dSDave Liu #define SICRH_TSEC2_D 0x00080000 33103051c3dSDave Liu #define SICRH_TSEC2_E 0x00040000 33203051c3dSDave Liu #define SICRH_TMR 0x00010000 33303051c3dSDave Liu #define SICRH_GPIO2_A 0x00008000 33403051c3dSDave Liu #define SICRH_GPIO2_B 0x00004000 33503051c3dSDave Liu #define SICRH_GPIO2_C 0x00002000 33603051c3dSDave Liu #define SICRH_GPIO2_D 0x00001000 33703051c3dSDave Liu #define SICRH_GPIO2_E 0x00000C00 338e1ac387fSAndy Fleming #define SICRH_GPIO2_E_SD 0x00000800 33903051c3dSDave Liu #define SICRH_GPIO2_F 0x00000300 34003051c3dSDave Liu #define SICRH_GPIO2_G 0x000000C0 34103051c3dSDave Liu #define SICRH_GPIO2_H 0x00000030 34203051c3dSDave Liu #define SICRH_SPI 0x00000003 343e1ac387fSAndy Fleming #define SICRH_SPI_SD 0x00000001 344f3ce250dSIlya Yanok 345f3ce250dSIlya Yanok #elif defined(CONFIG_MPC8308) 346f3ce250dSIlya Yanok /* SICRL bits - MPC8308 specific */ 347f3ce250dSIlya Yanok #define SICRL_SPI_PF0 (0 << 28) 348f3ce250dSIlya Yanok #define SICRL_SPI_PF1 (1 << 28) 349f3ce250dSIlya Yanok #define SICRL_SPI_PF3 (3 << 28) 350f3ce250dSIlya Yanok #define SICRL_UART_PF0 (0 << 26) 351f3ce250dSIlya Yanok #define SICRL_UART_PF1 (1 << 26) 352f3ce250dSIlya Yanok #define SICRL_UART_PF3 (3 << 26) 353f3ce250dSIlya Yanok #define SICRL_IRQ_PF0 (0 << 24) 354f3ce250dSIlya Yanok #define SICRL_IRQ_PF1 (1 << 24) 355f3ce250dSIlya Yanok #define SICRL_I2C2_PF0 (0 << 20) 356f3ce250dSIlya Yanok #define SICRL_I2C2_PF1 (1 << 20) 357f3ce250dSIlya Yanok #define SICRL_ETSEC1_TX_CLK (0 << 6) 358f3ce250dSIlya Yanok #define SICRL_ETSEC1_GTX_CLK125 (1 << 6) 359f3ce250dSIlya Yanok 360f3ce250dSIlya Yanok /* SICRH bits - MPC8308 specific */ 361f3ce250dSIlya Yanok #define SICRH_ESDHC_A_SD (0 << 30) 362f3ce250dSIlya Yanok #define SICRH_ESDHC_A_GTM (1 << 30) 363f3ce250dSIlya Yanok #define SICRH_ESDHC_A_GPIO (3 << 30) 364f3ce250dSIlya Yanok #define SICRH_ESDHC_B_SD (0 << 28) 365f3ce250dSIlya Yanok #define SICRH_ESDHC_B_GTM (1 << 28) 366f3ce250dSIlya Yanok #define SICRH_ESDHC_B_GPIO (3 << 28) 367f3ce250dSIlya Yanok #define SICRH_ESDHC_C_SD (0 << 26) 368f3ce250dSIlya Yanok #define SICRH_ESDHC_C_GTM (1 << 26) 369f3ce250dSIlya Yanok #define SICRH_ESDHC_C_GPIO (3 << 26) 370f3ce250dSIlya Yanok #define SICRH_GPIO_A_GPIO (0 << 24) 371f3ce250dSIlya Yanok #define SICRH_GPIO_A_TSEC2 (1 << 24) 372f3ce250dSIlya Yanok #define SICRH_GPIO_B_GPIO (0 << 22) 373f3ce250dSIlya Yanok #define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22) 374f3ce250dSIlya Yanok #define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22) 375f3ce250dSIlya Yanok #define SICRH_IEEE1588_A_TMR (1 << 20) 376f3ce250dSIlya Yanok #define SICRH_IEEE1588_A_GPIO (3 << 20) 377f3ce250dSIlya Yanok #define SICRH_USB (1 << 18) 378f3ce250dSIlya Yanok #define SICRH_GTM_GTM (1 << 16) 379f3ce250dSIlya Yanok #define SICRH_GTM_GPIO (3 << 16) 380f3ce250dSIlya Yanok #define SICRH_IEEE1588_B_TMR (1 << 14) 381f3ce250dSIlya Yanok #define SICRH_IEEE1588_B_GPIO (3 << 14) 382f3ce250dSIlya Yanok #define SICRH_ETSEC2_CRS (1 << 12) 383f3ce250dSIlya Yanok #define SICRH_ETSEC2_GPIO (3 << 12) 384f3ce250dSIlya Yanok #define SICRH_GPIOSEL_0 (0 << 8) 385f3ce250dSIlya Yanok #define SICRH_GPIOSEL_1 (1 << 8) 386f3ce250dSIlya Yanok #define SICRH_TMROBI_V3P3 (0 << 4) 387f3ce250dSIlya Yanok #define SICRH_TMROBI_V2P5 (1 << 4) 388f3ce250dSIlya Yanok #define SICRH_TSOBI1_V3P3 (0 << 1) 389f3ce250dSIlya Yanok #define SICRH_TSOBI1_V2P5 (1 << 1) 390f3ce250dSIlya Yanok #define SICRH_TSOBI2_V3P3 (0 << 0) 391f3ce250dSIlya Yanok #define SICRH_TSOBI2_V2P5 (1 << 0) 392e080313cSDave Liu #endif 393e080313cSDave Liu 3944e8b750cSHeiko Schocher /* 3954e8b750cSHeiko Schocher * SWCRR - System Watchdog Control Register 396e080313cSDave Liu */ 3974e8b750cSHeiko Schocher /* Register offset to immr */ 3984e8b750cSHeiko Schocher #define SWCRR 0x0204 3994e8b750cSHeiko Schocher /* Software Watchdog Time Count */ 4004e8b750cSHeiko Schocher #define SWCRR_SWTC 0xFFFF0000 4014e8b750cSHeiko Schocher /* Watchdog Enable bit */ 4024e8b750cSHeiko Schocher #define SWCRR_SWEN 0x00000004 4034e8b750cSHeiko Schocher /* Software Watchdog Reset/Interrupt Select bit */ 4044e8b750cSHeiko Schocher #define SWCRR_SWRI 0x00000002 4054e8b750cSHeiko Schocher /* Software Watchdog Counter Prescale bit */ 4064e8b750cSHeiko Schocher #define SWCRR_SWPR 0x00000001 4074e8b750cSHeiko Schocher #define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \ 4084e8b750cSHeiko Schocher SWCRR_SWRI | SWCRR_SWPR)) 409e080313cSDave Liu 4104e8b750cSHeiko Schocher /* 4114e8b750cSHeiko Schocher * SWCNR - System Watchdog Counter Register 412e080313cSDave Liu */ 4134e8b750cSHeiko Schocher /* Register offset to immr */ 4144e8b750cSHeiko Schocher #define SWCNR 0x0208 4154e8b750cSHeiko Schocher /* Software Watchdog Count mask */ 4164e8b750cSHeiko Schocher #define SWCNR_SWCN 0x0000FFFF 417e080313cSDave Liu #define SWCNR_RES ~(SWCNR_SWCN) 418e080313cSDave Liu 4194e8b750cSHeiko Schocher /* 4204e8b750cSHeiko Schocher * SWSRR - System Watchdog Service Register 421e080313cSDave Liu */ 4224e8b750cSHeiko Schocher /* Register offset to immr */ 4234e8b750cSHeiko Schocher #define SWSRR 0x020E 424e080313cSDave Liu 4254e8b750cSHeiko Schocher /* 4264e8b750cSHeiko Schocher * ACR - Arbiter Configuration Register 427e080313cSDave Liu */ 428e080313cSDave Liu #define ACR_COREDIS 0x10000000 /* Core disable */ 429e080313cSDave Liu #define ACR_COREDIS_SHIFT (31-7) 430e080313cSDave Liu #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 431e080313cSDave Liu #define ACR_PIPE_DEP_SHIFT (31-15) 432e080313cSDave Liu #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 433e080313cSDave Liu #define ACR_PCI_RPTCNT_SHIFT (31-19) 434e080313cSDave Liu #define ACR_RPTCNT 0x00000700 /* Repeat count */ 435e080313cSDave Liu #define ACR_RPTCNT_SHIFT (31-23) 436e080313cSDave Liu #define ACR_APARK 0x00000030 /* Address parking */ 437e080313cSDave Liu #define ACR_APARK_SHIFT (31-27) 438e080313cSDave Liu #define ACR_PARKM 0x0000000F /* Parking master */ 439e080313cSDave Liu #define ACR_PARKM_SHIFT (31-31) 440e080313cSDave Liu 4414e8b750cSHeiko Schocher /* 4424e8b750cSHeiko Schocher * ATR - Arbiter Timers Register 443e080313cSDave Liu */ 444e080313cSDave Liu #define ATR_DTO 0x00FF0000 /* Data time out */ 445002d27caSNick Spence #define ATR_DTO_SHIFT 16 446e080313cSDave Liu #define ATR_ATO 0x000000FF /* Address time out */ 447002d27caSNick Spence #define ATR_ATO_SHIFT 0 448e080313cSDave Liu 4494e8b750cSHeiko Schocher /* 4504e8b750cSHeiko Schocher * AER - Arbiter Event Register 451e080313cSDave Liu */ 452e080313cSDave Liu #define AER_ETEA 0x00000020 /* Transfer error */ 4534e8b750cSHeiko Schocher /* Reserved transfer type */ 4544e8b750cSHeiko Schocher #define AER_RES 0x00000010 4554e8b750cSHeiko Schocher /* External control word transfer type */ 4564e8b750cSHeiko Schocher #define AER_ECW 0x00000008 4574e8b750cSHeiko Schocher /* Address Only transfer type */ 4584e8b750cSHeiko Schocher #define AER_AO 0x00000004 459e080313cSDave Liu #define AER_DTO 0x00000002 /* Data time out */ 460e080313cSDave Liu #define AER_ATO 0x00000001 /* Address time out */ 461e080313cSDave Liu 4624e8b750cSHeiko Schocher /* 4634e8b750cSHeiko Schocher * AEATR - Arbiter Event Address Register 464e080313cSDave Liu */ 465e080313cSDave Liu #define AEATR_EVENT 0x07000000 /* Event type */ 466002d27caSNick Spence #define AEATR_EVENT_SHIFT 24 467e080313cSDave Liu #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 468002d27caSNick Spence #define AEATR_MSTR_ID_SHIFT 16 469e080313cSDave Liu #define AEATR_TBST 0x00000800 /* Transfer burst */ 470002d27caSNick Spence #define AEATR_TBST_SHIFT 11 471e080313cSDave Liu #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 472002d27caSNick Spence #define AEATR_TSIZE_SHIFT 8 473e080313cSDave Liu #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 474002d27caSNick Spence #define AEATR_TTYPE_SHIFT 0 475e080313cSDave Liu 4764e8b750cSHeiko Schocher /* 4774e8b750cSHeiko Schocher * HRCWL - Hard Reset Configuration Word Low 478e080313cSDave Liu */ 479e080313cSDave Liu #define HRCWL_LBIUCM 0x80000000 480e080313cSDave Liu #define HRCWL_LBIUCM_SHIFT 31 481e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 482e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 483e080313cSDave Liu 484e080313cSDave Liu #define HRCWL_DDRCM 0x40000000 485e080313cSDave Liu #define HRCWL_DDRCM_SHIFT 30 486e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 487e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 488e080313cSDave Liu 489e080313cSDave Liu #define HRCWL_SPMF 0x0f000000 490e080313cSDave Liu #define HRCWL_SPMF_SHIFT 24 491e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 492e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 493e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 494e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 495e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 496e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 497e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 498e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 499e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 500e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 501e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 502e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 503e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 504e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 505e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 506e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 507e080313cSDave Liu 508e080313cSDave Liu #define HRCWL_VCO_BYPASS 0x00000000 509e080313cSDave Liu #define HRCWL_VCO_1X2 0x00000000 510e080313cSDave Liu #define HRCWL_VCO_1X4 0x00200000 511e080313cSDave Liu #define HRCWL_VCO_1X8 0x00400000 512e080313cSDave Liu 513e080313cSDave Liu #define HRCWL_COREPLL 0x007F0000 514e080313cSDave Liu #define HRCWL_COREPLL_SHIFT 16 515e080313cSDave Liu #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 516e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1X1 0x00020000 517e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 518e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2X1 0x00040000 519e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 520e080313cSDave Liu #define HRCWL_CORE_TO_CSB_3X1 0x00060000 521e080313cSDave Liu 5222c7920afSPeter Tyser #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 523e080313cSDave Liu #define HRCWL_CEVCOD 0x000000C0 524e080313cSDave Liu #define HRCWL_CEVCOD_SHIFT 6 525e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 526e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 527e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 528e080313cSDave Liu 529e080313cSDave Liu #define HRCWL_CEPDF 0x00000020 530e080313cSDave Liu #define HRCWL_CEPDF_SHIFT 5 531e080313cSDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 532e080313cSDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 533e080313cSDave Liu 534e080313cSDave Liu #define HRCWL_CEPMF 0x0000001F 535e080313cSDave Liu #define HRCWL_CEPMF_SHIFT 0 536e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 537e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 538e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 539e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 540e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 541e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 542e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 543e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 544e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 545e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 546e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 547e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 548e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 549e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 550e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 551e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 552e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 553e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 554e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 555e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 556e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 557e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 558e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 559e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 560e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 561e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 562e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 563e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 564e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 565e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 566e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 56703051c3dSDave Liu 5687c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 5696f3931a2SDave Liu #define HRCWL_SVCOD 0x30000000 5706f3931a2SDave Liu #define HRCWL_SVCOD_SHIFT 28 5716f3931a2SDave Liu #define HRCWL_SVCOD_DIV_2 0x00000000 5726f3931a2SDave Liu #define HRCWL_SVCOD_DIV_4 0x10000000 5736f3931a2SDave Liu #define HRCWL_SVCOD_DIV_8 0x20000000 5746f3931a2SDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 5756f3931a2SDave Liu 5762c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 57703051c3dSDave Liu #define HRCWL_SVCOD 0x30000000 57803051c3dSDave Liu #define HRCWL_SVCOD_SHIFT 28 57903051c3dSDave Liu #define HRCWL_SVCOD_DIV_4 0x00000000 58003051c3dSDave Liu #define HRCWL_SVCOD_DIV_8 0x10000000 58103051c3dSDave Liu #define HRCWL_SVCOD_DIV_2 0x20000000 58203051c3dSDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 583e080313cSDave Liu #endif 584e080313cSDave Liu 5854e8b750cSHeiko Schocher /* 5864e8b750cSHeiko Schocher * HRCWH - Hardware Reset Configuration Word High 587e080313cSDave Liu */ 588e080313cSDave Liu #define HRCWH_PCI_HOST 0x80000000 589e080313cSDave Liu #define HRCWH_PCI_HOST_SHIFT 31 590e080313cSDave Liu #define HRCWH_PCI_AGENT 0x00000000 591e080313cSDave Liu 5922c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 593e080313cSDave Liu #define HRCWH_32_BIT_PCI 0x00000000 594e080313cSDave Liu #define HRCWH_64_BIT_PCI 0x40000000 595e080313cSDave Liu #endif 596e080313cSDave Liu 597e080313cSDave Liu #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 598e080313cSDave Liu #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 599e080313cSDave Liu 600e080313cSDave Liu #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 601e080313cSDave Liu #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 602e080313cSDave Liu 6032c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 604e080313cSDave Liu #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 605e080313cSDave Liu #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 606e080313cSDave Liu 607e080313cSDave Liu #elif defined(CONFIG_MPC8360) 608e080313cSDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 609e080313cSDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 610e080313cSDave Liu #endif 611e080313cSDave Liu 612e080313cSDave Liu #define HRCWH_CORE_DISABLE 0x08000000 613e080313cSDave Liu #define HRCWH_CORE_ENABLE 0x00000000 614e080313cSDave Liu 615e080313cSDave Liu #define HRCWH_FROM_0X00000100 0x00000000 616e080313cSDave Liu #define HRCWH_FROM_0XFFF00100 0x04000000 617e080313cSDave Liu 618e080313cSDave Liu #define HRCWH_BOOTSEQ_DISABLE 0x00000000 619e080313cSDave Liu #define HRCWH_BOOTSEQ_NORMAL 0x01000000 620e080313cSDave Liu #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 621e080313cSDave Liu 622e080313cSDave Liu #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 623e080313cSDave Liu #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 624e080313cSDave Liu 625e080313cSDave Liu #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 626e080313cSDave Liu #define HRCWH_ROM_LOC_PCI1 0x00100000 6272c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 628e080313cSDave Liu #define HRCWH_ROM_LOC_PCI2 0x00200000 629e080313cSDave Liu #endif 6302c7920afSPeter Tyser #if defined(CONFIG_MPC837x) 63103051c3dSDave Liu #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 63203051c3dSDave Liu #endif 633e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 634e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 635e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 636e080313cSDave Liu 6377c619ddcSIlya Yanok #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 6387c619ddcSIlya Yanok defined(CONFIG_MPC837x) 639d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 640d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 641d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 642d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 643d87c57b2SScott Wood 644d87c57b2SScott Wood #define HRCWH_RL_EXT_LEGACY 0x00000000 645d87c57b2SScott Wood #define HRCWH_RL_EXT_NAND 0x00040000 646d87c57b2SScott Wood 647e6d9c891SAnton Vorontsov #define HRCWH_TSEC1M_MASK 0x0000E000 648d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_MII 0x00000000 649d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RMII 0x00002000 650d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RGMII 0x00006000 651d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 652d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 653d87c57b2SScott Wood 654e6d9c891SAnton Vorontsov #define HRCWH_TSEC2M_MASK 0x00001C00 655d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_MII 0x00000000 656d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RMII 0x00000400 657d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 658d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RTBI 0x00001400 659d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_SGMII 0x00001800 660d87c57b2SScott Wood #endif 661d87c57b2SScott Wood 6622c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 663e080313cSDave Liu #define HRCWH_TSEC1M_IN_RGMII 0x00000000 664e080313cSDave Liu #define HRCWH_TSEC1M_IN_RTBI 0x00004000 665e080313cSDave Liu #define HRCWH_TSEC1M_IN_GMII 0x00008000 666e080313cSDave Liu #define HRCWH_TSEC1M_IN_TBI 0x0000C000 667e080313cSDave Liu #define HRCWH_TSEC2M_IN_RGMII 0x00000000 668e080313cSDave Liu #define HRCWH_TSEC2M_IN_RTBI 0x00001000 669e080313cSDave Liu #define HRCWH_TSEC2M_IN_GMII 0x00002000 670e080313cSDave Liu #define HRCWH_TSEC2M_IN_TBI 0x00003000 671e080313cSDave Liu #endif 672e080313cSDave Liu 673e080313cSDave Liu #if defined(CONFIG_MPC8360) 674e080313cSDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 675e080313cSDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 676e080313cSDave Liu #endif 677e080313cSDave Liu 678e080313cSDave Liu #define HRCWH_BIG_ENDIAN 0x00000000 679e080313cSDave Liu #define HRCWH_LITTLE_ENDIAN 0x00000008 680e080313cSDave Liu 681e080313cSDave Liu #define HRCWH_LALE_NORMAL 0x00000000 682e080313cSDave Liu #define HRCWH_LALE_EARLY 0x00000004 683e080313cSDave Liu 684e080313cSDave Liu #define HRCWH_LDP_SET 0x00000000 685e080313cSDave Liu #define HRCWH_LDP_CLEAR 0x00000002 686e080313cSDave Liu 6874e8b750cSHeiko Schocher /* 6884e8b750cSHeiko Schocher * RSR - Reset Status Register 689e080313cSDave Liu */ 6907c619ddcSIlya Yanok #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 6917c619ddcSIlya Yanok defined(CONFIG_MPC837x) 69203051c3dSDave Liu #define RSR_RSTSRC 0xF0000000 /* Reset source */ 69303051c3dSDave Liu #define RSR_RSTSRC_SHIFT 28 69403051c3dSDave Liu #else 695e080313cSDave Liu #define RSR_RSTSRC 0xE0000000 /* Reset source */ 696e080313cSDave Liu #define RSR_RSTSRC_SHIFT 29 69703051c3dSDave Liu #endif 698e080313cSDave Liu #define RSR_BSF 0x00010000 /* Boot seq. fail */ 699e080313cSDave Liu #define RSR_BSF_SHIFT 16 7004e8b750cSHeiko Schocher /* software soft reset */ 7014e8b750cSHeiko Schocher #define RSR_SWSR 0x00002000 702e080313cSDave Liu #define RSR_SWSR_SHIFT 13 7034e8b750cSHeiko Schocher /* software hard reset */ 7044e8b750cSHeiko Schocher #define RSR_SWHR 0x00001000 705e080313cSDave Liu #define RSR_SWHR_SHIFT 12 706e080313cSDave Liu #define RSR_JHRS 0x00000200 /* jtag hreset */ 707e080313cSDave Liu #define RSR_JHRS_SHIFT 9 7084e8b750cSHeiko Schocher /* jtag sreset status */ 7094e8b750cSHeiko Schocher #define RSR_JSRS 0x00000100 710e080313cSDave Liu #define RSR_JSRS_SHIFT 8 7114e8b750cSHeiko Schocher /* checkstop reset status */ 7124e8b750cSHeiko Schocher #define RSR_CSHR 0x00000010 713e080313cSDave Liu #define RSR_CSHR_SHIFT 4 7144e8b750cSHeiko Schocher /* software watchdog reset status */ 7154e8b750cSHeiko Schocher #define RSR_SWRS 0x00000008 716e080313cSDave Liu #define RSR_SWRS_SHIFT 3 7174e8b750cSHeiko Schocher /* bus monitop reset status */ 7184e8b750cSHeiko Schocher #define RSR_BMRS 0x00000004 719e080313cSDave Liu #define RSR_BMRS_SHIFT 2 720e080313cSDave Liu #define RSR_SRS 0x00000002 /* soft reset status */ 721e080313cSDave Liu #define RSR_SRS_SHIFT 1 722e080313cSDave Liu #define RSR_HRS 0x00000001 /* hard reset status */ 723e080313cSDave Liu #define RSR_HRS_SHIFT 0 7244e8b750cSHeiko Schocher #define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \ 7254e8b750cSHeiko Schocher RSR_SWHR | RSR_JHRS | \ 7264e8b750cSHeiko Schocher RSR_JSRS | RSR_CSHR | \ 7274e8b750cSHeiko Schocher RSR_SWRS | RSR_BMRS | \ 7284e8b750cSHeiko Schocher RSR_SRS | RSR_HRS)) 7294e8b750cSHeiko Schocher /* 7304e8b750cSHeiko Schocher * RMR - Reset Mode Register 731e080313cSDave Liu */ 7324e8b750cSHeiko Schocher /* checkstop reset enable */ 7334e8b750cSHeiko Schocher #define RMR_CSRE 0x00000001 734e080313cSDave Liu #define RMR_CSRE_SHIFT 0 735e080313cSDave Liu #define RMR_RES ~(RMR_CSRE) 736e080313cSDave Liu 7374e8b750cSHeiko Schocher /* 7384e8b750cSHeiko Schocher * RCR - Reset Control Register 739e080313cSDave Liu */ 7404e8b750cSHeiko Schocher /* software hard reset */ 7414e8b750cSHeiko Schocher #define RCR_SWHR 0x00000002 7424e8b750cSHeiko Schocher /* software soft reset */ 7434e8b750cSHeiko Schocher #define RCR_SWSR 0x00000001 744e080313cSDave Liu #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 745e080313cSDave Liu 7464e8b750cSHeiko Schocher /* 7474e8b750cSHeiko Schocher * RCER - Reset Control Enable Register 748e080313cSDave Liu */ 7494e8b750cSHeiko Schocher /* software hard reset */ 7504e8b750cSHeiko Schocher #define RCER_CRE 0x00000001 751e080313cSDave Liu #define RCER_RES ~(RCER_CRE) 752e080313cSDave Liu 7534e8b750cSHeiko Schocher /* 7544e8b750cSHeiko Schocher * SPMR - System PLL Mode Register 755e080313cSDave Liu */ 756e080313cSDave Liu #define SPMR_LBIUCM 0x80000000 75726e5f794SJoakim Tjernlund #define SPMR_LBIUCM_SHIFT 31 758e080313cSDave Liu #define SPMR_DDRCM 0x40000000 75926e5f794SJoakim Tjernlund #define SPMR_DDRCM_SHIFT 30 760e080313cSDave Liu #define SPMR_SPMF 0x0F000000 76126e5f794SJoakim Tjernlund #define SPMR_SPMF_SHIFT 24 762e080313cSDave Liu #define SPMR_CKID 0x00800000 763e080313cSDave Liu #define SPMR_CKID_SHIFT 23 764e080313cSDave Liu #define SPMR_COREPLL 0x007F0000 76526e5f794SJoakim Tjernlund #define SPMR_COREPLL_SHIFT 16 766e080313cSDave Liu #define SPMR_CEVCOD 0x000000C0 76726e5f794SJoakim Tjernlund #define SPMR_CEVCOD_SHIFT 6 768e080313cSDave Liu #define SPMR_CEPDF 0x00000020 76926e5f794SJoakim Tjernlund #define SPMR_CEPDF_SHIFT 5 770e080313cSDave Liu #define SPMR_CEPMF 0x0000001F 77126e5f794SJoakim Tjernlund #define SPMR_CEPMF_SHIFT 0 772e080313cSDave Liu 7734e8b750cSHeiko Schocher /* 7744e8b750cSHeiko Schocher * OCCR - Output Clock Control Register 775e080313cSDave Liu */ 776e080313cSDave Liu #define OCCR_PCICOE0 0x80000000 777e080313cSDave Liu #define OCCR_PCICOE1 0x40000000 778e080313cSDave Liu #define OCCR_PCICOE2 0x20000000 779e080313cSDave Liu #define OCCR_PCICOE3 0x10000000 780e080313cSDave Liu #define OCCR_PCICOE4 0x08000000 781e080313cSDave Liu #define OCCR_PCICOE5 0x04000000 782e080313cSDave Liu #define OCCR_PCICOE6 0x02000000 783e080313cSDave Liu #define OCCR_PCICOE7 0x01000000 784e080313cSDave Liu #define OCCR_PCICD0 0x00800000 785e080313cSDave Liu #define OCCR_PCICD1 0x00400000 786e080313cSDave Liu #define OCCR_PCICD2 0x00200000 787e080313cSDave Liu #define OCCR_PCICD3 0x00100000 788e080313cSDave Liu #define OCCR_PCICD4 0x00080000 789e080313cSDave Liu #define OCCR_PCICD5 0x00040000 790e080313cSDave Liu #define OCCR_PCICD6 0x00020000 791e080313cSDave Liu #define OCCR_PCICD7 0x00010000 792e080313cSDave Liu #define OCCR_PCI1CR 0x00000002 793e080313cSDave Liu #define OCCR_PCI2CR 0x00000001 794e080313cSDave Liu #define OCCR_PCICR OCCR_PCI1CR 795e080313cSDave Liu 7964e8b750cSHeiko Schocher /* 7974e8b750cSHeiko Schocher * SCCR - System Clock Control Register 798e080313cSDave Liu */ 799e080313cSDave Liu #define SCCR_ENCCM 0x03000000 800e080313cSDave Liu #define SCCR_ENCCM_SHIFT 24 801e080313cSDave Liu #define SCCR_ENCCM_0 0x00000000 802e080313cSDave Liu #define SCCR_ENCCM_1 0x01000000 803e080313cSDave Liu #define SCCR_ENCCM_2 0x02000000 804e080313cSDave Liu #define SCCR_ENCCM_3 0x03000000 805e080313cSDave Liu 806e080313cSDave Liu #define SCCR_PCICM 0x00010000 807e080313cSDave Liu #define SCCR_PCICM_SHIFT 16 808e080313cSDave Liu 8092c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 81003051c3dSDave Liu /* SCCR bits - MPC834x specific */ 811e080313cSDave Liu #define SCCR_TSEC1CM 0xc0000000 812e080313cSDave Liu #define SCCR_TSEC1CM_SHIFT 30 813e080313cSDave Liu #define SCCR_TSEC1CM_0 0x00000000 814e080313cSDave Liu #define SCCR_TSEC1CM_1 0x40000000 815e080313cSDave Liu #define SCCR_TSEC1CM_2 0x80000000 816e080313cSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 817e080313cSDave Liu 818e080313cSDave Liu #define SCCR_TSEC2CM 0x30000000 819e080313cSDave Liu #define SCCR_TSEC2CM_SHIFT 28 820e080313cSDave Liu #define SCCR_TSEC2CM_0 0x00000000 821e080313cSDave Liu #define SCCR_TSEC2CM_1 0x10000000 822e080313cSDave Liu #define SCCR_TSEC2CM_2 0x20000000 823e080313cSDave Liu #define SCCR_TSEC2CM_3 0x30000000 824d87c57b2SScott Wood 82503051c3dSDave Liu /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 82603051c3dSDave Liu #define SCCR_USBMPHCM 0x00c00000 82703051c3dSDave Liu #define SCCR_USBMPHCM_SHIFT 22 82803051c3dSDave Liu #define SCCR_USBDRCM 0x00300000 82903051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 20 83003051c3dSDave Liu #define SCCR_USBCM 0x00f00000 83103051c3dSDave Liu #define SCCR_USBCM_SHIFT 20 83203051c3dSDave Liu #define SCCR_USBCM_0 0x00000000 83303051c3dSDave Liu #define SCCR_USBCM_1 0x00500000 83403051c3dSDave Liu #define SCCR_USBCM_2 0x00A00000 83503051c3dSDave Liu #define SCCR_USBCM_3 0x00F00000 83603051c3dSDave Liu 837555da617SDave Liu #elif defined(CONFIG_MPC8313) 838a8cb43a8SDave Liu /* TSEC1 bits are for TSEC2 as well */ 839d87c57b2SScott Wood #define SCCR_TSEC1CM 0xc0000000 840d87c57b2SScott Wood #define SCCR_TSEC1CM_SHIFT 30 8419e896478SKim Phillips #define SCCR_TSEC1CM_0 0x00000000 842d87c57b2SScott Wood #define SCCR_TSEC1CM_1 0x40000000 843d87c57b2SScott Wood #define SCCR_TSEC1CM_2 0x80000000 844d87c57b2SScott Wood #define SCCR_TSEC1CM_3 0xC0000000 845d87c57b2SScott Wood 846d87c57b2SScott Wood #define SCCR_TSEC1ON 0x20000000 847df33f6b4STimur Tabi #define SCCR_TSEC1ON_SHIFT 29 848d87c57b2SScott Wood #define SCCR_TSEC2ON 0x10000000 849df33f6b4STimur Tabi #define SCCR_TSEC2ON_SHIFT 28 850d87c57b2SScott Wood 851e080313cSDave Liu #define SCCR_USBDRCM 0x00300000 852e080313cSDave Liu #define SCCR_USBDRCM_SHIFT 20 85303051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 85403051c3dSDave Liu #define SCCR_USBDRCM_1 0x00100000 85503051c3dSDave Liu #define SCCR_USBDRCM_2 0x00200000 85603051c3dSDave Liu #define SCCR_USBDRCM_3 0x00300000 857e080313cSDave Liu 8587c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 8597c619ddcSIlya Yanok /* SCCR bits - MPC8315/MPC8308 specific */ 860555da617SDave Liu #define SCCR_TSEC1CM 0xc0000000 861555da617SDave Liu #define SCCR_TSEC1CM_SHIFT 30 862555da617SDave Liu #define SCCR_TSEC1CM_0 0x00000000 863555da617SDave Liu #define SCCR_TSEC1CM_1 0x40000000 864555da617SDave Liu #define SCCR_TSEC1CM_2 0x80000000 865555da617SDave Liu #define SCCR_TSEC1CM_3 0xC0000000 866555da617SDave Liu 867555da617SDave Liu #define SCCR_TSEC2CM 0x30000000 868555da617SDave Liu #define SCCR_TSEC2CM_SHIFT 28 869555da617SDave Liu #define SCCR_TSEC2CM_0 0x00000000 870555da617SDave Liu #define SCCR_TSEC2CM_1 0x10000000 871555da617SDave Liu #define SCCR_TSEC2CM_2 0x20000000 872555da617SDave Liu #define SCCR_TSEC2CM_3 0x30000000 873555da617SDave Liu 8747c619ddcSIlya Yanok #define SCCR_SDHCCM 0x0c000000 8757c619ddcSIlya Yanok #define SCCR_SDHCCM_SHIFT 26 8767c619ddcSIlya Yanok #define SCCR_SDHCCM_0 0x00000000 8777c619ddcSIlya Yanok #define SCCR_SDHCCM_1 0x04000000 8787c619ddcSIlya Yanok #define SCCR_SDHCCM_2 0x08000000 8797c619ddcSIlya Yanok #define SCCR_SDHCCM_3 0x0c000000 8807c619ddcSIlya Yanok 8816f3931a2SDave Liu #define SCCR_USBDRCM 0x00c00000 8826f3931a2SDave Liu #define SCCR_USBDRCM_SHIFT 22 883555da617SDave Liu #define SCCR_USBDRCM_0 0x00000000 8846f3931a2SDave Liu #define SCCR_USBDRCM_1 0x00400000 8856f3931a2SDave Liu #define SCCR_USBDRCM_2 0x00800000 8866f3931a2SDave Liu #define SCCR_USBDRCM_3 0x00c00000 887555da617SDave Liu 8886f3931a2SDave Liu #define SCCR_SATA1CM 0x00003000 8896f3931a2SDave Liu #define SCCR_SATA1CM_SHIFT 12 8906f3931a2SDave Liu #define SCCR_SATACM 0x00003c00 8916f3931a2SDave Liu #define SCCR_SATACM_SHIFT 10 892555da617SDave Liu #define SCCR_SATACM_0 0x00000000 8936f3931a2SDave Liu #define SCCR_SATACM_1 0x00001400 8946f3931a2SDave Liu #define SCCR_SATACM_2 0x00002800 8956f3931a2SDave Liu #define SCCR_SATACM_3 0x00003c00 896555da617SDave Liu 8976f3931a2SDave Liu #define SCCR_TDMCM 0x00000030 8986f3931a2SDave Liu #define SCCR_TDMCM_SHIFT 4 899555da617SDave Liu #define SCCR_TDMCM_0 0x00000000 9006f3931a2SDave Liu #define SCCR_TDMCM_1 0x00000010 9016f3931a2SDave Liu #define SCCR_TDMCM_2 0x00000020 9026f3931a2SDave Liu #define SCCR_TDMCM_3 0x00000030 903555da617SDave Liu 9042c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 90503051c3dSDave Liu /* SCCR bits - MPC837x specific */ 90603051c3dSDave Liu #define SCCR_TSEC1CM 0xc0000000 90703051c3dSDave Liu #define SCCR_TSEC1CM_SHIFT 30 90803051c3dSDave Liu #define SCCR_TSEC1CM_0 0x00000000 90903051c3dSDave Liu #define SCCR_TSEC1CM_1 0x40000000 91003051c3dSDave Liu #define SCCR_TSEC1CM_2 0x80000000 91103051c3dSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 91203051c3dSDave Liu 91303051c3dSDave Liu #define SCCR_TSEC2CM 0x30000000 91403051c3dSDave Liu #define SCCR_TSEC2CM_SHIFT 28 91503051c3dSDave Liu #define SCCR_TSEC2CM_0 0x00000000 91603051c3dSDave Liu #define SCCR_TSEC2CM_1 0x10000000 91703051c3dSDave Liu #define SCCR_TSEC2CM_2 0x20000000 91803051c3dSDave Liu #define SCCR_TSEC2CM_3 0x30000000 91903051c3dSDave Liu 92003051c3dSDave Liu #define SCCR_SDHCCM 0x0c000000 92103051c3dSDave Liu #define SCCR_SDHCCM_SHIFT 26 92203051c3dSDave Liu #define SCCR_SDHCCM_0 0x00000000 92303051c3dSDave Liu #define SCCR_SDHCCM_1 0x04000000 92403051c3dSDave Liu #define SCCR_SDHCCM_2 0x08000000 92503051c3dSDave Liu #define SCCR_SDHCCM_3 0x0c000000 92603051c3dSDave Liu 92703051c3dSDave Liu #define SCCR_USBDRCM 0x00c00000 92803051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 22 92903051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 93003051c3dSDave Liu #define SCCR_USBDRCM_1 0x00400000 93103051c3dSDave Liu #define SCCR_USBDRCM_2 0x00800000 93203051c3dSDave Liu #define SCCR_USBDRCM_3 0x00c00000 93303051c3dSDave Liu 934fd6646c0SAnton Vorontsov /* All of the four SATA controllers must have the same clock ratio */ 935fd6646c0SAnton Vorontsov #define SCCR_SATA1CM 0x000000c0 936fd6646c0SAnton Vorontsov #define SCCR_SATA1CM_SHIFT 6 937fd6646c0SAnton Vorontsov #define SCCR_SATACM 0x000000ff 938fd6646c0SAnton Vorontsov #define SCCR_SATACM_SHIFT 0 939fd6646c0SAnton Vorontsov #define SCCR_SATACM_0 0x00000000 940fd6646c0SAnton Vorontsov #define SCCR_SATACM_1 0x00000055 941fd6646c0SAnton Vorontsov #define SCCR_SATACM_2 0x000000aa 942fd6646c0SAnton Vorontsov #define SCCR_SATACM_3 0x000000ff 943fd6646c0SAnton Vorontsov #endif 944fd6646c0SAnton Vorontsov 94503051c3dSDave Liu #define SCCR_PCIEXP1CM 0x00300000 94603051c3dSDave Liu #define SCCR_PCIEXP1CM_SHIFT 20 94703051c3dSDave Liu #define SCCR_PCIEXP1CM_0 0x00000000 94803051c3dSDave Liu #define SCCR_PCIEXP1CM_1 0x00100000 94903051c3dSDave Liu #define SCCR_PCIEXP1CM_2 0x00200000 95003051c3dSDave Liu #define SCCR_PCIEXP1CM_3 0x00300000 95103051c3dSDave Liu 95203051c3dSDave Liu #define SCCR_PCIEXP2CM 0x000c0000 95303051c3dSDave Liu #define SCCR_PCIEXP2CM_SHIFT 18 95403051c3dSDave Liu #define SCCR_PCIEXP2CM_0 0x00000000 95503051c3dSDave Liu #define SCCR_PCIEXP2CM_1 0x00040000 95603051c3dSDave Liu #define SCCR_PCIEXP2CM_2 0x00080000 95703051c3dSDave Liu #define SCCR_PCIEXP2CM_3 0x000c0000 95803051c3dSDave Liu 9594e8b750cSHeiko Schocher /* 9604e8b750cSHeiko Schocher * CSn_BDNS - Chip Select memory Bounds Register 961e080313cSDave Liu */ 962e080313cSDave Liu #define CSBNDS_SA 0x00FF0000 963e080313cSDave Liu #define CSBNDS_SA_SHIFT 8 964e080313cSDave Liu #define CSBNDS_EA 0x000000FF 965e080313cSDave Liu #define CSBNDS_EA_SHIFT 24 966e080313cSDave Liu 9674e8b750cSHeiko Schocher /* 9684e8b750cSHeiko Schocher * CSn_CONFIG - Chip Select Configuration Register 969e080313cSDave Liu */ 970e080313cSDave Liu #define CSCONFIG_EN 0x80000000 971e080313cSDave Liu #define CSCONFIG_AP 0x00800000 9729e896478SKim Phillips #define CSCONFIG_ODT_WR_ACS 0x00010000 9736d2c26acSHeiko Schocher #if defined(CONFIG_MPC832x) 9746d2c26acSHeiko Schocher #define CSCONFIG_ODT_WR_CFG 0x00040000 9756d2c26acSHeiko Schocher #endif 976d82b4fc0STor Krill #define CSCONFIG_BANK_BIT_3 0x00004000 977e080313cSDave Liu #define CSCONFIG_ROW_BIT 0x00000700 978e080313cSDave Liu #define CSCONFIG_ROW_BIT_12 0x00000000 979e080313cSDave Liu #define CSCONFIG_ROW_BIT_13 0x00000100 980e080313cSDave Liu #define CSCONFIG_ROW_BIT_14 0x00000200 981e080313cSDave Liu #define CSCONFIG_COL_BIT 0x00000007 982e080313cSDave Liu #define CSCONFIG_COL_BIT_8 0x00000000 983e080313cSDave Liu #define CSCONFIG_COL_BIT_9 0x00000001 984e080313cSDave Liu #define CSCONFIG_COL_BIT_10 0x00000002 985e080313cSDave Liu #define CSCONFIG_COL_BIT_11 0x00000003 986e080313cSDave Liu 9874e8b750cSHeiko Schocher /* 9884e8b750cSHeiko Schocher * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 989d87c57b2SScott Wood */ 990d87c57b2SScott Wood #define TIMING_CFG0_RWT 0xC0000000 991d87c57b2SScott Wood #define TIMING_CFG0_RWT_SHIFT 30 992d87c57b2SScott Wood #define TIMING_CFG0_WRT 0x30000000 993d87c57b2SScott Wood #define TIMING_CFG0_WRT_SHIFT 28 994d87c57b2SScott Wood #define TIMING_CFG0_RRT 0x0C000000 995d87c57b2SScott Wood #define TIMING_CFG0_RRT_SHIFT 26 996d87c57b2SScott Wood #define TIMING_CFG0_WWT 0x03000000 997d87c57b2SScott Wood #define TIMING_CFG0_WWT_SHIFT 24 998d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 999d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 1000d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 1001d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 1002d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 1003d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 1004d892b2dbSAnton Vorontsov #define TIMING_CFG0_MRS_CYC 0x0000000F 1005d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC_SHIFT 0 1006d87c57b2SScott Wood 10074e8b750cSHeiko Schocher /* 10084e8b750cSHeiko Schocher * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 1009e080313cSDave Liu */ 1010e080313cSDave Liu #define TIMING_CFG1_PRETOACT 0x70000000 1011e080313cSDave Liu #define TIMING_CFG1_PRETOACT_SHIFT 28 1012e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE 0x0F000000 1013e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE_SHIFT 24 1014e080313cSDave Liu #define TIMING_CFG1_ACTTORW 0x00700000 1015e080313cSDave Liu #define TIMING_CFG1_ACTTORW_SHIFT 20 1016e080313cSDave Liu #define TIMING_CFG1_CASLAT 0x00070000 1017e080313cSDave Liu #define TIMING_CFG1_CASLAT_SHIFT 16 1018e080313cSDave Liu #define TIMING_CFG1_REFREC 0x0000F000 1019e080313cSDave Liu #define TIMING_CFG1_REFREC_SHIFT 12 1020e080313cSDave Liu #define TIMING_CFG1_WRREC 0x00000700 1021e080313cSDave Liu #define TIMING_CFG1_WRREC_SHIFT 8 1022e080313cSDave Liu #define TIMING_CFG1_ACTTOACT 0x00000070 1023e080313cSDave Liu #define TIMING_CFG1_ACTTOACT_SHIFT 4 1024e080313cSDave Liu #define TIMING_CFG1_WRTORD 0x00000007 1025e080313cSDave Liu #define TIMING_CFG1_WRTORD_SHIFT 0 1026e080313cSDave Liu #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 1027e080313cSDave Liu #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 1028facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ 1029facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ 1030facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ 10312b68b233SHeiko Schocher #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ 10322b68b233SHeiko Schocher #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ 1033e080313cSDave Liu 10344e8b750cSHeiko Schocher /* 10354e8b750cSHeiko Schocher * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 1036e080313cSDave Liu */ 10378d172c0fSXie Xiaobo #define TIMING_CFG2_CPO 0x0F800000 10388d172c0fSXie Xiaobo #define TIMING_CFG2_CPO_SHIFT 23 1039e080313cSDave Liu #define TIMING_CFG2_ACSM 0x00080000 1040e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 1041e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 10424e8b750cSHeiko Schocher /* default (= CASLAT + 1) */ 10434e8b750cSHeiko Schocher #define TIMING_CFG2_CPO_DEF 0x00000000 1044e080313cSDave Liu 1045d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT 0x70000000 1046d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT_SHIFT 28 1047d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 1048d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 1049d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE 0x0000E000 1050d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 1051d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS 0x000001C0 1052d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS_SHIFT 6 1053d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT 0x0000003F 1054d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT_SHIFT 0 1055d87c57b2SScott Wood 10564e8b750cSHeiko Schocher /* 1057*f1ccd106SHeiko Schocher * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 1058*f1ccd106SHeiko Schocher */ 1059*f1ccd106SHeiko Schocher #define TIMING_CFG3_EXT_REFREC 0x00070000 1060*f1ccd106SHeiko Schocher #define TIMING_CFG3_EXT_REFREC_SHIFT 16 1061*f1ccd106SHeiko Schocher 1062*f1ccd106SHeiko Schocher /* 10634e8b750cSHeiko Schocher * DDR_SDRAM_CFG - DDR SDRAM Control Configuration 1064e080313cSDave Liu */ 1065e080313cSDave Liu #define SDRAM_CFG_MEM_EN 0x80000000 1066e080313cSDave Liu #define SDRAM_CFG_SREN 0x40000000 1067e080313cSDave Liu #define SDRAM_CFG_ECC_EN 0x20000000 1068e080313cSDave Liu #define SDRAM_CFG_RD_EN 0x10000000 1069bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 1070bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 1071bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 1072e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 1073e080313cSDave Liu #define SDRAM_CFG_DYN_PWR 0x00200000 1074e080313cSDave Liu #define SDRAM_CFG_32_BE 0x00080000 1075e080313cSDave Liu #define SDRAM_CFG_8_BE 0x00040000 1076e080313cSDave Liu #define SDRAM_CFG_NCAP 0x00020000 1077e080313cSDave Liu #define SDRAM_CFG_2T_EN 0x00008000 1078a7b8126eSAndre Schwarz #define SDRAM_CFG_HSE 0x00000008 1079d87c57b2SScott Wood #define SDRAM_CFG_BI 0x00000001 1080e080313cSDave Liu 10814e8b750cSHeiko Schocher /* 10824e8b750cSHeiko Schocher * DDR_SDRAM_MODE - DDR SDRAM Mode Register 1083e080313cSDave Liu */ 1084e080313cSDave Liu #define SDRAM_MODE_ESD 0xFFFF0000 1085e080313cSDave Liu #define SDRAM_MODE_ESD_SHIFT 16 1086e080313cSDave Liu #define SDRAM_MODE_SD 0x0000FFFF 1087e080313cSDave Liu #define SDRAM_MODE_SD_SHIFT 0 10884e8b750cSHeiko Schocher /* select extended mode reg */ 10894e8b750cSHeiko Schocher #define DDR_MODE_EXT_MODEREG 0x4000 10904e8b750cSHeiko Schocher /* operating mode, mask */ 10914e8b750cSHeiko Schocher #define DDR_MODE_EXT_OPMODE 0x3FF8 1092e080313cSDave Liu #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 10934e8b750cSHeiko Schocher /* QFC / compatibility, mask */ 10944e8b750cSHeiko Schocher #define DDR_MODE_QFC 0x0004 10954e8b750cSHeiko Schocher /* compatible to older SDRAMs */ 10964e8b750cSHeiko Schocher #define DDR_MODE_QFC_COMP 0x0000 10974e8b750cSHeiko Schocher /* weak drivers */ 10984e8b750cSHeiko Schocher #define DDR_MODE_WEAK 0x0002 10994e8b750cSHeiko Schocher /* disable DLL */ 11004e8b750cSHeiko Schocher #define DDR_MODE_DLL_DIS 0x0001 11014e8b750cSHeiko Schocher /* CAS latency, mask */ 11024e8b750cSHeiko Schocher #define DDR_MODE_CASLAT 0x0070 1103e080313cSDave Liu #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 1104e080313cSDave Liu #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 1105e080313cSDave Liu #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 1106e080313cSDave Liu #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 11074e8b750cSHeiko Schocher /* sequential burst */ 11084e8b750cSHeiko Schocher #define DDR_MODE_BTYPE_SEQ 0x0000 11094e8b750cSHeiko Schocher /* interleaved burst */ 11104e8b750cSHeiko Schocher #define DDR_MODE_BTYPE_ILVD 0x0008 1111e080313cSDave Liu #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 1112e080313cSDave Liu #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 11134e8b750cSHeiko Schocher /* exact value for 7.8125us */ 11144e8b750cSHeiko Schocher #define DDR_REFINT_166MHZ_7US 1302 11154e8b750cSHeiko Schocher /* use 256 cycles as a starting point */ 11164e8b750cSHeiko Schocher #define DDR_BSTOPRE 256 11174e8b750cSHeiko Schocher /* select mode register */ 11184e8b750cSHeiko Schocher #define DDR_MODE_MODEREG 0x0000 1119e080313cSDave Liu 11204e8b750cSHeiko Schocher /* 11214e8b750cSHeiko Schocher * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 1122e080313cSDave Liu */ 1123e080313cSDave Liu #define SDRAM_INTERVAL_REFINT 0x3FFF0000 1124e080313cSDave Liu #define SDRAM_INTERVAL_REFINT_SHIFT 16 1125e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 1126e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 1127e080313cSDave Liu 11284e8b750cSHeiko Schocher /* 11294e8b750cSHeiko Schocher * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 1130e080313cSDave Liu */ 1131e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 1132e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 1133e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 1134e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 1135e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 1136e080313cSDave Liu 11374e8b750cSHeiko Schocher /* 11384e8b750cSHeiko Schocher * ECC_ERR_INJECT - Memory data path error injection mask ECC 1139e080313cSDave Liu */ 11404e8b750cSHeiko Schocher /* ECC Mirror Byte */ 11414e8b750cSHeiko Schocher #define ECC_ERR_INJECT_EMB (0x80000000 >> 22) 11424e8b750cSHeiko Schocher /* Error Injection Enable */ 11434e8b750cSHeiko Schocher #define ECC_ERR_INJECT_EIEN (0x80000000 >> 23) 11444e8b750cSHeiko Schocher /* ECC Erroe Injection Enable */ 11454e8b750cSHeiko Schocher #define ECC_ERR_INJECT_EEIM (0xff000000 >> 24) 1146e080313cSDave Liu #define ECC_ERR_INJECT_EEIM_SHIFT 0 1147e080313cSDave Liu 11484e8b750cSHeiko Schocher /* 11494e8b750cSHeiko Schocher * CAPTURE_ECC - Memory data path read capture ECC 1150e080313cSDave Liu */ 1151e080313cSDave Liu #define CAPTURE_ECC_ECE (0xff000000 >> 24) 1152e080313cSDave Liu #define CAPTURE_ECC_ECE_SHIFT 0 1153e080313cSDave Liu 11544e8b750cSHeiko Schocher /* 11554e8b750cSHeiko Schocher * ERR_DETECT - Memory error detect 1156e080313cSDave Liu */ 11574e8b750cSHeiko Schocher /* Multiple Memory Errors */ 11584e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_MME (0x80000000 >> 0) 11594e8b750cSHeiko Schocher /* Multiple-Bit Error */ 11604e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_MBE (0x80000000 >> 28) 11614e8b750cSHeiko Schocher /* Single-Bit ECC Error Pickup */ 11624e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_SBE (0x80000000 >> 29) 11634e8b750cSHeiko Schocher /* Memory Select Error */ 11644e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_MSE (0x80000000 >> 31) 1165e080313cSDave Liu 11664e8b750cSHeiko Schocher /* 11674e8b750cSHeiko Schocher * ERR_DISABLE - Memory error disable 1168e080313cSDave Liu */ 11694e8b750cSHeiko Schocher /* Multiple-Bit ECC Error Disable */ 11704e8b750cSHeiko Schocher #define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28) 11714e8b750cSHeiko Schocher /* Sinle-Bit ECC Error disable */ 11724e8b750cSHeiko Schocher #define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29) 11734e8b750cSHeiko Schocher /* Memory Select Error Disable */ 11744e8b750cSHeiko Schocher #define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31) 11754e8b750cSHeiko Schocher #define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \ 11764e8b750cSHeiko Schocher ECC_ERROR_DISABLE_SBED | \ 11774e8b750cSHeiko Schocher ECC_ERROR_DISABLE_MBED)) 11784e8b750cSHeiko Schocher 11794e8b750cSHeiko Schocher /* 11804e8b750cSHeiko Schocher * ERR_INT_EN - Memory error interrupt enable 1181e080313cSDave Liu */ 11824e8b750cSHeiko Schocher /* Multiple-Bit ECC Error Interrupt Enable */ 11834e8b750cSHeiko Schocher #define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28) 11844e8b750cSHeiko Schocher /* Single-Bit ECC Error Interrupt Enable */ 11854e8b750cSHeiko Schocher #define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29) 11864e8b750cSHeiko Schocher /* Memory Select Error Interrupt Enable */ 11874e8b750cSHeiko Schocher #define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31) 11884e8b750cSHeiko Schocher #define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \ 11894e8b750cSHeiko Schocher ECC_ERR_INT_EN_SBEE | \ 11904e8b750cSHeiko Schocher ECC_ERR_INT_EN_MSEE)) 11914e8b750cSHeiko Schocher 11924e8b750cSHeiko Schocher /* 11934e8b750cSHeiko Schocher * CAPTURE_ATTRIBUTES - Memory error attributes capture 1194e080313cSDave Liu */ 11954e8b750cSHeiko Schocher /* Data Beat Num */ 11964e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1) 1197e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM_SHIFT 28 11984e8b750cSHeiko Schocher /* Transaction Size */ 11994e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6) 1200e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 1201e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 1202e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1203e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1204e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 12054e8b750cSHeiko Schocher /* Transaction Source */ 12064e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11) 1207e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1208e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1209e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1210e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1211e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1212e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1213e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1214e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1215e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1216e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1217e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1218e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_SHIFT 16 12194e8b750cSHeiko Schocher /* Transaction Type */ 12204e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18) 1221e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1222e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_READ 0x2 1223e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1224e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1225e080313cSDave Liu #define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */ 1226e080313cSDave Liu 12274e8b750cSHeiko Schocher /* 12284e8b750cSHeiko Schocher * ERR_SBE - Single bit ECC memory error management 1229e080313cSDave Liu */ 12304e8b750cSHeiko Schocher /* Single-Bit Error Threshold 0..255 */ 12314e8b750cSHeiko Schocher #define ECC_ERROR_MAN_SBET (0xff000000 >> 8) 1232e080313cSDave Liu #define ECC_ERROR_MAN_SBET_SHIFT 16 12334e8b750cSHeiko Schocher /* Single Bit Error Counter 0..255 */ 12344e8b750cSHeiko Schocher #define ECC_ERROR_MAN_SBEC (0xff000000 >> 24) 1235e080313cSDave Liu #define ECC_ERROR_MAN_SBEC_SHIFT 0 1236e080313cSDave Liu 12374e8b750cSHeiko Schocher /* 12384e8b750cSHeiko Schocher * CONFIG_ADDRESS - PCI Config Address Register 1239e080313cSDave Liu */ 1240e080313cSDave Liu #define PCI_CONFIG_ADDRESS_EN 0x80000000 1241e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1242e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1243e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1244e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1245e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1246e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1247e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1248e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1249e080313cSDave Liu 12504e8b750cSHeiko Schocher /* 12514e8b750cSHeiko Schocher * POTAR - PCI Outbound Translation Address Register 1252e080313cSDave Liu */ 1253e080313cSDave Liu #define POTAR_TA_MASK 0x000fffff 1254e080313cSDave Liu 12554e8b750cSHeiko Schocher /* 12564e8b750cSHeiko Schocher * POBAR - PCI Outbound Base Address Register 1257e080313cSDave Liu */ 1258e080313cSDave Liu #define POBAR_BA_MASK 0x000fffff 1259e080313cSDave Liu 12604e8b750cSHeiko Schocher /* 12614e8b750cSHeiko Schocher * POCMR - PCI Outbound Comparision Mask Register 1262e080313cSDave Liu */ 1263e080313cSDave Liu #define POCMR_EN 0x80000000 12644e8b750cSHeiko Schocher /* 0-memory space 1-I/O space */ 12654e8b750cSHeiko Schocher #define POCMR_IO 0x40000000 1266e080313cSDave Liu #define POCMR_SE 0x20000000 /* streaming enable */ 1267e080313cSDave Liu #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1268e080313cSDave Liu #define POCMR_CM_MASK 0x000fffff 1269e080313cSDave Liu #define POCMR_CM_4G 0x00000000 1270e080313cSDave Liu #define POCMR_CM_2G 0x00080000 1271e080313cSDave Liu #define POCMR_CM_1G 0x000C0000 1272e080313cSDave Liu #define POCMR_CM_512M 0x000E0000 1273e080313cSDave Liu #define POCMR_CM_256M 0x000F0000 1274e080313cSDave Liu #define POCMR_CM_128M 0x000F8000 1275e080313cSDave Liu #define POCMR_CM_64M 0x000FC000 1276e080313cSDave Liu #define POCMR_CM_32M 0x000FE000 1277e080313cSDave Liu #define POCMR_CM_16M 0x000FF000 1278e080313cSDave Liu #define POCMR_CM_8M 0x000FF800 1279e080313cSDave Liu #define POCMR_CM_4M 0x000FFC00 1280e080313cSDave Liu #define POCMR_CM_2M 0x000FFE00 1281e080313cSDave Liu #define POCMR_CM_1M 0x000FFF00 1282e080313cSDave Liu #define POCMR_CM_512K 0x000FFF80 1283e080313cSDave Liu #define POCMR_CM_256K 0x000FFFC0 1284e080313cSDave Liu #define POCMR_CM_128K 0x000FFFE0 1285e080313cSDave Liu #define POCMR_CM_64K 0x000FFFF0 1286e080313cSDave Liu #define POCMR_CM_32K 0x000FFFF8 1287e080313cSDave Liu #define POCMR_CM_16K 0x000FFFFC 1288e080313cSDave Liu #define POCMR_CM_8K 0x000FFFFE 1289e080313cSDave Liu #define POCMR_CM_4K 0x000FFFFF 1290e080313cSDave Liu 12914e8b750cSHeiko Schocher /* 12924e8b750cSHeiko Schocher * PITAR - PCI Inbound Translation Address Register 1293e080313cSDave Liu */ 1294e080313cSDave Liu #define PITAR_TA_MASK 0x000fffff 1295e080313cSDave Liu 12964e8b750cSHeiko Schocher /* 12974e8b750cSHeiko Schocher * PIBAR - PCI Inbound Base/Extended Address Register 1298e080313cSDave Liu */ 1299e080313cSDave Liu #define PIBAR_MASK 0xffffffff 1300e080313cSDave Liu #define PIEBAR_EBA_MASK 0x000fffff 1301e080313cSDave Liu 13024e8b750cSHeiko Schocher /* 13034e8b750cSHeiko Schocher * PIWAR - PCI Inbound Windows Attributes Register 1304e080313cSDave Liu */ 1305e080313cSDave Liu #define PIWAR_EN 0x80000000 1306e080313cSDave Liu #define PIWAR_PF 0x20000000 1307e080313cSDave Liu #define PIWAR_RTT_MASK 0x000f0000 1308e080313cSDave Liu #define PIWAR_RTT_NO_SNOOP 0x00040000 1309e080313cSDave Liu #define PIWAR_RTT_SNOOP 0x00050000 1310e080313cSDave Liu #define PIWAR_WTT_MASK 0x0000f000 1311e080313cSDave Liu #define PIWAR_WTT_NO_SNOOP 0x00004000 1312e080313cSDave Liu #define PIWAR_WTT_SNOOP 0x00005000 1313e080313cSDave Liu #define PIWAR_IWS_MASK 0x0000003F 1314e080313cSDave Liu #define PIWAR_IWS_4K 0x0000000B 1315e080313cSDave Liu #define PIWAR_IWS_8K 0x0000000C 1316e080313cSDave Liu #define PIWAR_IWS_16K 0x0000000D 1317e080313cSDave Liu #define PIWAR_IWS_32K 0x0000000E 1318e080313cSDave Liu #define PIWAR_IWS_64K 0x0000000F 1319e080313cSDave Liu #define PIWAR_IWS_128K 0x00000010 1320e080313cSDave Liu #define PIWAR_IWS_256K 0x00000011 1321e080313cSDave Liu #define PIWAR_IWS_512K 0x00000012 1322e080313cSDave Liu #define PIWAR_IWS_1M 0x00000013 1323e080313cSDave Liu #define PIWAR_IWS_2M 0x00000014 1324e080313cSDave Liu #define PIWAR_IWS_4M 0x00000015 1325e080313cSDave Liu #define PIWAR_IWS_8M 0x00000016 1326e080313cSDave Liu #define PIWAR_IWS_16M 0x00000017 1327e080313cSDave Liu #define PIWAR_IWS_32M 0x00000018 1328e080313cSDave Liu #define PIWAR_IWS_64M 0x00000019 1329e080313cSDave Liu #define PIWAR_IWS_128M 0x0000001A 1330e080313cSDave Liu #define PIWAR_IWS_256M 0x0000001B 1331e080313cSDave Liu #define PIWAR_IWS_512M 0x0000001C 1332e080313cSDave Liu #define PIWAR_IWS_1G 0x0000001D 1333e080313cSDave Liu #define PIWAR_IWS_2G 0x0000001E 1334f6eda7f8SDave Liu 13354e8b750cSHeiko Schocher /* 13364e8b750cSHeiko Schocher * PMCCR1 - PCI Configuration Register 1 1337d87c57b2SScott Wood */ 1338d87c57b2SScott Wood #define PMCCR1_POWER_OFF 0x00000020 1339d87c57b2SScott Wood 13404e8b750cSHeiko Schocher /* 13414e8b750cSHeiko Schocher * DDRCDR - DDR Control Driver Register 1342d87c57b2SScott Wood */ 13439e896478SKim Phillips #define DDRCDR_DHC_EN 0x80000000 1344d87c57b2SScott Wood #define DDRCDR_EN 0x40000000 1345d87c57b2SScott Wood #define DDRCDR_PZ 0x3C000000 1346d87c57b2SScott Wood #define DDRCDR_PZ_MAXZ 0x00000000 1347d87c57b2SScott Wood #define DDRCDR_PZ_HIZ 0x20000000 1348d87c57b2SScott Wood #define DDRCDR_PZ_NOMZ 0x30000000 1349d87c57b2SScott Wood #define DDRCDR_PZ_LOZ 0x38000000 1350d87c57b2SScott Wood #define DDRCDR_PZ_MINZ 0x3C000000 1351d87c57b2SScott Wood #define DDRCDR_NZ 0x3C000000 1352d87c57b2SScott Wood #define DDRCDR_NZ_MAXZ 0x00000000 1353d87c57b2SScott Wood #define DDRCDR_NZ_HIZ 0x02000000 1354d87c57b2SScott Wood #define DDRCDR_NZ_NOMZ 0x03000000 1355d87c57b2SScott Wood #define DDRCDR_NZ_LOZ 0x03800000 1356d87c57b2SScott Wood #define DDRCDR_NZ_MINZ 0x03C00000 1357d87c57b2SScott Wood #define DDRCDR_ODT 0x00080000 1358d87c57b2SScott Wood #define DDRCDR_DDR_CFG 0x00040000 1359d87c57b2SScott Wood #define DDRCDR_M_ODR 0x00000002 1360d87c57b2SScott Wood #define DDRCDR_Q_DRN 0x00000001 1361d87c57b2SScott Wood 13624e8b750cSHeiko Schocher /* 13634e8b750cSHeiko Schocher * PCIE Bridge Register 1364fd6646c0SAnton Vorontsov */ 1365fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_OBPIOE 0x00000001 1366fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_IBPIOE 0x00000002 1367fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_WDMAE 0x00000004 1368fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_RDMAE 0x00000008 1369fd6646c0SAnton Vorontsov 1370fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_PIOE 0x00000001 1371fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_MEMWE 0x00000002 1372fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_IOWE 0x00000004 1373fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_CFGWE 0x00000008 1374fd6646c0SAnton Vorontsov 1375fd6646c0SAnton Vorontsov #define PEX_CSB_IBCTRL_PIOE 0x00000001 1376fd6646c0SAnton Vorontsov 1377fd6646c0SAnton Vorontsov #define PEX_OWAR_EN 0x00000001 1378fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_CFG 0x00000000 1379fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_IO 0x00000002 1380fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_MEM 0x00000004 1381fd6646c0SAnton Vorontsov #define PEX_OWAR_RLXO 0x00000008 1382fd6646c0SAnton Vorontsov #define PEX_OWAR_NANP 0x00000010 1383fd6646c0SAnton Vorontsov #define PEX_OWAR_SIZE 0xFFFFF000 1384fd6646c0SAnton Vorontsov 1385fd6646c0SAnton Vorontsov #define PEX_IWAR_EN 0x00000001 1386fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_INT 0x00000000 1387fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_PF 0x00000004 1388fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_NO_PF 0x00000006 1389fd6646c0SAnton Vorontsov #define PEX_IWAR_NSOV 0x00000008 1390fd6646c0SAnton Vorontsov #define PEX_IWAR_NSNP 0x00000010 1391fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE 0xFFFFF000 1392fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_1M 0x000FF000 1393fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_2M 0x001FF000 1394fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_4M 0x003FF000 1395fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_8M 0x007FF000 1396fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_16M 0x00FFF000 1397fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_32M 0x01FFF000 1398fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_64M 0x03FFF000 1399fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_128M 0x07FFF000 1400fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_256M 0x0FFFF000 1401fd6646c0SAnton Vorontsov 1402fd6646c0SAnton Vorontsov #define PEX_GCLK_RATIO 0x440 1403fd6646c0SAnton Vorontsov 140449ea3b6eSScott Wood #ifndef __ASSEMBLY__ 140549ea3b6eSScott Wood struct pci_region; 14066aa3d3bfSPeter Tyser void mpc83xx_pci_init(int num_buses, struct pci_region **reg); 140775f35209SIra Snyder void mpc83xx_pcislave_unlock(int bus); 14086aa3d3bfSPeter Tyser void mpc83xx_pcie_init(int num_buses, struct pci_region **reg); 140949ea3b6eSScott Wood #endif 141049ea3b6eSScott Wood 1411f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 1412