1f046ccd1SEran Liberty /* 2f046ccd1SEran Liberty * Copyright 2004 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty * 12f046ccd1SEran Liberty * This program is distributed in the hope that it will be useful, 13f046ccd1SEran Liberty * but WITHOUT ANY WARRANTY; without even the implied warranty of 14f046ccd1SEran Liberty * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15f046ccd1SEran Liberty * GNU General Public License for more details. 16f046ccd1SEran Liberty * 17f046ccd1SEran Liberty * You should have received a copy of the GNU General Public License 18f046ccd1SEran Liberty * along with this program; if not, write to the Free Software 19f046ccd1SEran Liberty * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20f046ccd1SEran Liberty * MA 02111-1307 USA 21f046ccd1SEran Liberty */ 22f046ccd1SEran Liberty 23f046ccd1SEran Liberty /* 24f046ccd1SEran Liberty * mpc83xx.h 25f046ccd1SEran Liberty * 26f046ccd1SEran Liberty * MPC83xx specific definitions 27f046ccd1SEran Liberty */ 28f046ccd1SEran Liberty 29f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 30f046ccd1SEran Liberty #define __MPC83XX_H__ 31f046ccd1SEran Liberty 32f046ccd1SEran Liberty #if defined(CONFIG_E300) 33f046ccd1SEran Liberty #include <asm/e300.h> 34f046ccd1SEran Liberty #endif 35f046ccd1SEran Liberty 36f046ccd1SEran Liberty /* 37f046ccd1SEran Liberty * MPC83xx cpu provide RCR register to do reset thing specially. easier 38f046ccd1SEran Liberty * to implement 39f046ccd1SEran Liberty */ 40f046ccd1SEran Liberty 41f046ccd1SEran Liberty #define MPC83xx_RESET 42f046ccd1SEran Liberty 43f046ccd1SEran Liberty /* 44f046ccd1SEran Liberty * System reset offset (PowerPC standard) 45f046ccd1SEran Liberty */ 46f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 47f046ccd1SEran Liberty 48f046ccd1SEran Liberty /* 49f046ccd1SEran Liberty * Default Internal Memory Register Space (Freescale recomandation) 50f046ccd1SEran Liberty */ 51f046ccd1SEran Liberty #define CONFIG_DEFAULT_IMMR 0xFF400000 52f046ccd1SEran Liberty 53f046ccd1SEran Liberty /* 54f046ccd1SEran Liberty * Watchdog 55f046ccd1SEran Liberty */ 56f046ccd1SEran Liberty #define SWCRR 0x0204 57f046ccd1SEran Liberty #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ 58f046ccd1SEran Liberty #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ 59f046ccd1SEran Liberty #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ 60f046ccd1SEran Liberty #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ 61f046ccd1SEran Liberty #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 62f046ccd1SEran Liberty 63f046ccd1SEran Liberty #define SWCNR 0x0208 64f046ccd1SEran Liberty #define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. 65f046ccd1SEran Liberty #define SWCNR_RES ~(SWCNR_SWCN) 66f046ccd1SEran Liberty 67f046ccd1SEran Liberty #define SWSRR 0x020E 68f046ccd1SEran Liberty 69f046ccd1SEran Liberty /* 70f046ccd1SEran Liberty * Default Internal Memory Register Space (Freescale recomandation) 71f046ccd1SEran Liberty */ 72f046ccd1SEran Liberty #define IMMRBAR 0x0000 73f046ccd1SEran Liberty #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */ 74f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 75f046ccd1SEran Liberty 76f046ccd1SEran Liberty /* 77f046ccd1SEran Liberty * Default Internal Memory Register Space (Freescale recomandation) 78f046ccd1SEran Liberty */ 79f046ccd1SEran Liberty #define LBLAWBAR0 0x0020 80f046ccd1SEran Liberty #define LBLAWAR0 0x0024 81f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 82f046ccd1SEran Liberty #define LBLAWAR1 0x002C 83f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 84f046ccd1SEran Liberty #define LBLAWAR2 0x0034 85f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 86f046ccd1SEran Liberty #define LBLAWAR3 0x003C 87f046ccd1SEran Liberty 88f046ccd1SEran Liberty 89f046ccd1SEran Liberty /* 90f046ccd1SEran Liberty * Base Registers & Option Registers 91f046ccd1SEran Liberty */ 92f046ccd1SEran Liberty #define BR0 0x5000 93f046ccd1SEran Liberty #define BR1 0x5008 94f046ccd1SEran Liberty #define BR2 0x5010 95f046ccd1SEran Liberty #define BR3 0x5018 96f046ccd1SEran Liberty #define BR4 0x5020 97f046ccd1SEran Liberty #define BR5 0x5028 98f046ccd1SEran Liberty #define BR6 0x5030 99f046ccd1SEran Liberty #define BR7 0x5038 100f046ccd1SEran Liberty 101f046ccd1SEran Liberty #define BR_BA 0xFFFF8000 102f046ccd1SEran Liberty #define BR_BA_SHIFT 15 103f046ccd1SEran Liberty #define BR_PS 0x00001800 104f046ccd1SEran Liberty #define BR_PS_SHIFT 11 105*e6f2e902SMarian Balakowicz #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 106*e6f2e902SMarian Balakowicz #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 107*e6f2e902SMarian Balakowicz #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 108f046ccd1SEran Liberty #define BR_DECC 0x00000600 109f046ccd1SEran Liberty #define BR_DECC_SHIFT 9 110f046ccd1SEran Liberty #define BR_WP 0x00000100 111f046ccd1SEran Liberty #define BR_WP_SHIFT 8 112f046ccd1SEran Liberty #define BR_MSEL 0x000000E0 113f046ccd1SEran Liberty #define BR_MSEL_SHIFT 5 114*e6f2e902SMarian Balakowicz #define BR_MS_GPCM 0x00000000 /* GPCM */ 115*e6f2e902SMarian Balakowicz #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 116*e6f2e902SMarian Balakowicz #define BR_MS_UPMA 0x00000080 /* UPMA */ 117*e6f2e902SMarian Balakowicz #define BR_MS_UPMB 0x000000A0 /* UPMB */ 118*e6f2e902SMarian Balakowicz #define BR_MS_UPMC 0x000000C0 /* UPMC */ 119f046ccd1SEran Liberty #define BR_V 0x00000001 120f046ccd1SEran Liberty #define BR_V_SHIFT 0 121f046ccd1SEran Liberty #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) 122f046ccd1SEran Liberty 123f046ccd1SEran Liberty #define OR0 0x5004 124f046ccd1SEran Liberty #define OR1 0x500C 125f046ccd1SEran Liberty #define OR2 0x5014 126f046ccd1SEran Liberty #define OR3 0x501C 127f046ccd1SEran Liberty #define OR4 0x5024 128f046ccd1SEran Liberty #define OR5 0x502C 129f046ccd1SEran Liberty #define OR6 0x5034 130f046ccd1SEran Liberty #define OR7 0x503C 131f046ccd1SEran Liberty 132f046ccd1SEran Liberty #define OR_GPCM_AM 0xFFFF8000 133f046ccd1SEran Liberty #define OR_GPCM_AM_SHIFT 15 134f046ccd1SEran Liberty #define OR_GPCM_BCTLD 0x00001000 135f046ccd1SEran Liberty #define OR_GPCM_BCTLD_SHIFT 12 136f046ccd1SEran Liberty #define OR_GPCM_CSNT 0x00000800 137f046ccd1SEran Liberty #define OR_GPCM_CSNT_SHIFT 11 138f046ccd1SEran Liberty #define OR_GPCM_ACS 0x00000600 139f046ccd1SEran Liberty #define OR_GPCM_ACS_SHIFT 9 140*e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b10 0x00000400 141*e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b11 0x00000600 142f046ccd1SEran Liberty #define OR_GPCM_XACS 0x00000100 143f046ccd1SEran Liberty #define OR_GPCM_XACS_SHIFT 8 144f046ccd1SEran Liberty #define OR_GPCM_SCY 0x000000F0 145f046ccd1SEran Liberty #define OR_GPCM_SCY_SHIFT 4 146*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_1 0x00000010 147*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_2 0x00000020 148*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_3 0x00000030 149*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_4 0x00000040 150*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_5 0x00000050 151*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_6 0x00000060 152*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_7 0x00000070 153*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_8 0x00000080 154*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_9 0x00000090 155*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_10 0x000000a0 156*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_11 0x000000b0 157*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_12 0x000000c0 158*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_13 0x000000d0 159*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_14 0x000000e0 160*e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_15 0x000000f0 161f046ccd1SEran Liberty #define OR_GPCM_SETA 0x00000008 162f046ccd1SEran Liberty #define OR_GPCM_SETA_SHIFT 3 163f046ccd1SEran Liberty #define OR_GPCM_TRLX 0x00000004 164f046ccd1SEran Liberty #define OR_GPCM_TRLX_SHIFT 2 165f046ccd1SEran Liberty #define OR_GPCM_EHTR 0x00000002 166f046ccd1SEran Liberty #define OR_GPCM_EHTR_SHIFT 1 167f046ccd1SEran Liberty #define OR_GPCM_EAD 0x00000001 168f046ccd1SEran Liberty #define OR_GPCM_EAD_SHIFT 0 169f046ccd1SEran Liberty 170f046ccd1SEran Liberty #define OR_UPM_AM 0xFFFF8000 171f046ccd1SEran Liberty #define OR_UPM_AM_SHIFT 15 172f046ccd1SEran Liberty #define OR_UPM_XAM 0x00006000 173f046ccd1SEran Liberty #define OR_UPM_XAM_SHIFT 13 174f046ccd1SEran Liberty #define OR_UPM_BCTLD 0x00001000 175f046ccd1SEran Liberty #define OR_UPM_BCTLD_SHIFT 12 176f046ccd1SEran Liberty #define OR_UPM_BI 0x00000100 177f046ccd1SEran Liberty #define OR_UPM_BI_SHIFT 8 178f046ccd1SEran Liberty #define OR_UPM_TRLX 0x00000004 179f046ccd1SEran Liberty #define OR_UPM_TRLX_SHIFT 2 180f046ccd1SEran Liberty #define OR_UPM_EHTR 0x00000002 181f046ccd1SEran Liberty #define OR_UPM_EHTR_SHIFT 1 182f046ccd1SEran Liberty #define OR_UPM_EAD 0x00000001 183f046ccd1SEran Liberty #define OR_UPM_EAD_SHIFT 0 184f046ccd1SEran Liberty 185f046ccd1SEran Liberty #define OR_SDRAM_AM 0xFFFF8000 186f046ccd1SEran Liberty #define OR_SDRAM_AM_SHIFT 15 187f046ccd1SEran Liberty #define OR_SDRAM_XAM 0x00006000 188f046ccd1SEran Liberty #define OR_SDRAM_XAM_SHIFT 13 189f046ccd1SEran Liberty #define OR_SDRAM_COLS 0x00001C00 190f046ccd1SEran Liberty #define OR_SDRAM_COLS_SHIFT 10 191f046ccd1SEran Liberty #define OR_SDRAM_ROWS 0x000001C0 192f046ccd1SEran Liberty #define OR_SDRAM_ROWS_SHIFT 6 193f046ccd1SEran Liberty #define OR_SDRAM_PMSEL 0x00000020 194f046ccd1SEran Liberty #define OR_SDRAM_PMSEL_SHIFT 5 195f046ccd1SEran Liberty #define OR_SDRAM_EAD 0x00000001 196f046ccd1SEran Liberty #define OR_SDRAM_EAD_SHIFT 0 197f046ccd1SEran Liberty 198f046ccd1SEran Liberty /* 199f046ccd1SEran Liberty * Hard Reset Configration Word - High 200f046ccd1SEran Liberty */ 201f046ccd1SEran Liberty #define HRCWH_PCI_AGENT 0x00000000 202f046ccd1SEran Liberty #define HRCWH_PCI_HOST 0x80000000 203f046ccd1SEran Liberty 204f046ccd1SEran Liberty #define HRCWH_32_BIT_PCI 0x00000000 205f046ccd1SEran Liberty #define HRCWH_64_BIT_PCI 0x40000000 206f046ccd1SEran Liberty 207f046ccd1SEran Liberty #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 208f046ccd1SEran Liberty #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 209f046ccd1SEran Liberty 210f046ccd1SEran Liberty #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 211f046ccd1SEran Liberty #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 212f046ccd1SEran Liberty 213f046ccd1SEran Liberty #define HRCWH_CORE_DISABLE 0x08000000 214f046ccd1SEran Liberty #define HRCWH_CORE_ENABLE 0x00000000 215f046ccd1SEran Liberty 216f046ccd1SEran Liberty #define HRCWH_FROM_0X00000100 0x00000000 217f046ccd1SEran Liberty #define HRCWH_FROM_0XFFF00100 0x04000000 218f046ccd1SEran Liberty 219f046ccd1SEran Liberty #define HRCWH_BOOTSEQ_DISABLE 0x00000000 220f046ccd1SEran Liberty #define HRCWH_BOOTSEQ_NORMAL 0x01000000 221f046ccd1SEran Liberty #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 222f046ccd1SEran Liberty 223f046ccd1SEran Liberty #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 224f046ccd1SEran Liberty #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 225f046ccd1SEran Liberty 226f046ccd1SEran Liberty #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 227f046ccd1SEran Liberty #define HRCWH_ROM_LOC_PCI1 0x00100000 228f046ccd1SEran Liberty #define HRCWH_ROM_LOC_PCI2 0x00200000 229f046ccd1SEran Liberty #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 230f046ccd1SEran Liberty #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 231f046ccd1SEran Liberty #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 232f046ccd1SEran Liberty 233f046ccd1SEran Liberty #define HRCWH_TSEC1M_IN_RGMII 0x00000000 234f046ccd1SEran Liberty #define HRCWH_TSEC1M_IN_RTBI 0x00004000 235f046ccd1SEran Liberty #define HRCWH_TSEC1M_IN_GMII 0x00008000 236f046ccd1SEran Liberty #define HRCWH_TSEC1M_IN_TBI 0x0000C000 237f046ccd1SEran Liberty 238f046ccd1SEran Liberty #define HRCWH_TSEC2M_IN_RGMII 0x00000000 239f046ccd1SEran Liberty #define HRCWH_TSEC2M_IN_RTBI 0x00001000 240f046ccd1SEran Liberty #define HRCWH_TSEC2M_IN_GMII 0x00002000 241f046ccd1SEran Liberty #define HRCWH_TSEC2M_IN_TBI 0x00003000 242f046ccd1SEran Liberty 243f046ccd1SEran Liberty #define HRCWH_BIG_ENDIAN 0x00000000 244f046ccd1SEran Liberty #define HRCWH_LITTLE_ENDIAN 0x00000008 245f046ccd1SEran Liberty 246f046ccd1SEran Liberty /* 247f046ccd1SEran Liberty * Hard Reset Configration Word - Low 248f046ccd1SEran Liberty */ 249f046ccd1SEran Liberty #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 250f046ccd1SEran Liberty #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 251f046ccd1SEran Liberty 252f046ccd1SEran Liberty #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 253f046ccd1SEran Liberty #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 254f046ccd1SEran Liberty 255f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 256f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 257f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 258f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 259f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 260f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 261f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 262f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 263f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 264f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 265f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 266f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 267f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 268f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 269f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 270f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 271f046ccd1SEran Liberty 272f046ccd1SEran Liberty #define HRCWL_VCO_BYPASS 0x00000000 273f046ccd1SEran Liberty #define HRCWL_VCO_1X2 0x00000000 274f046ccd1SEran Liberty #define HRCWL_VCO_1X4 0x00200000 275f046ccd1SEran Liberty #define HRCWL_VCO_1X8 0x00400000 276f046ccd1SEran Liberty 277f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 278f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_1X1 0x00020000 279f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 280f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_2X1 0x00040000 281f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 282f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_3X1 0x00060000 283f046ccd1SEran Liberty 284f046ccd1SEran Liberty /* 285f046ccd1SEran Liberty * LCRR - Clock Ratio Register (10.3.1.16) 286f046ccd1SEran Liberty */ 287f046ccd1SEran Liberty #define LCRR_DBYP 0x80000000 288f046ccd1SEran Liberty #define LCRR_DBYP_SHIFT 31 289f046ccd1SEran Liberty #define LCRR_BUFCMDC 0x30000000 290f046ccd1SEran Liberty #define LCRR_BUFCMDC_1 0x10000000 291f046ccd1SEran Liberty #define LCRR_BUFCMDC_2 0x20000000 292f046ccd1SEran Liberty #define LCRR_BUFCMDC_3 0x30000000 293f046ccd1SEran Liberty #define LCRR_BUFCMDC_4 0x00000000 294f046ccd1SEran Liberty #define LCRR_BUFCMDC_SHIFT 28 295f046ccd1SEran Liberty #define LCRR_ECL 0x03000000 296f046ccd1SEran Liberty #define LCRR_ECL_4 0x00000000 297f046ccd1SEran Liberty #define LCRR_ECL_5 0x01000000 298f046ccd1SEran Liberty #define LCRR_ECL_6 0x02000000 299f046ccd1SEran Liberty #define LCRR_ECL_7 0x03000000 300f046ccd1SEran Liberty #define LCRR_ECL_SHIFT 24 301f046ccd1SEran Liberty #define LCRR_EADC 0x00030000 302f046ccd1SEran Liberty #define LCRR_EADC_1 0x00010000 303f046ccd1SEran Liberty #define LCRR_EADC_2 0x00020000 304f046ccd1SEran Liberty #define LCRR_EADC_3 0x00030000 305f046ccd1SEran Liberty #define LCRR_EADC_4 0x00000000 306f046ccd1SEran Liberty #define LCRR_EADC_SHIFT 16 307f046ccd1SEran Liberty #define LCRR_CLKDIV 0x0000000F 308f046ccd1SEran Liberty #define LCRR_CLKDIV_2 0x00000002 309f046ccd1SEran Liberty #define LCRR_CLKDIV_4 0x00000004 310f046ccd1SEran Liberty #define LCRR_CLKDIV_8 0x00000008 311f046ccd1SEran Liberty #define LCRR_CLKDIV_SHIFT 0 312f046ccd1SEran Liberty 313f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 314