1f046ccd1SEran Liberty /* 2f6eda7f8SDave Liu * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty */ 12f046ccd1SEran Liberty 13f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 14f046ccd1SEran Liberty #define __MPC83XX_H__ 15f046ccd1SEran Liberty 16f6eda7f8SDave Liu #include <config.h> 17f046ccd1SEran Liberty #if defined(CONFIG_E300) 18f046ccd1SEran Liberty #include <asm/e300.h> 19f046ccd1SEran Liberty #endif 20f046ccd1SEran Liberty 21*e080313cSDave Liu /* MPC83xx cpu provide RCR register to do reset thing specially 22f046ccd1SEran Liberty */ 23f046ccd1SEran Liberty #define MPC83xx_RESET 24f046ccd1SEran Liberty 25*e080313cSDave Liu /* System reset offset (PowerPC standard) 26f046ccd1SEran Liberty */ 27f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 28f046ccd1SEran Liberty 29*e080313cSDave Liu /* IMMRBAR - Internal Memory Register Base Address 30f046ccd1SEran Liberty */ 31*e080313cSDave Liu #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 32*e080313cSDave Liu #define IMMRBAR 0x0000 /* Register offset to immr */ 33*e080313cSDave Liu #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 34f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 35f046ccd1SEran Liberty 36*e080313cSDave Liu /* LAWBAR - Local Access Window Base Address Register 37f046ccd1SEran Liberty */ 38*e080313cSDave Liu #define LBLAWBAR0 0x0020 /* Register offset to immr */ 39f046ccd1SEran Liberty #define LBLAWAR0 0x0024 40f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 41f046ccd1SEran Liberty #define LBLAWAR1 0x002C 42f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 43f046ccd1SEran Liberty #define LBLAWAR2 0x0034 44f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 45f046ccd1SEran Liberty #define LBLAWAR3 0x003C 46*e080313cSDave Liu #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 47f046ccd1SEran Liberty 48*e080313cSDave Liu /* SPRIDR - System Part and Revision ID Register 49f6eda7f8SDave Liu */ 50*e080313cSDave Liu #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ 51*e080313cSDave Liu #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ 52*e080313cSDave Liu 53f6eda7f8SDave Liu #define SPR_8349E_REV10 0x80300100 545f820439SDave Liu #define SPR_8349_REV10 0x80310100 555f820439SDave Liu #define SPR_8347E_REV10_TBGA 0x80320100 565f820439SDave Liu #define SPR_8347_REV10_TBGA 0x80330100 575f820439SDave Liu #define SPR_8347E_REV10_PBGA 0x80340100 585f820439SDave Liu #define SPR_8347_REV10_PBGA 0x80350100 595f820439SDave Liu #define SPR_8343E_REV10 0x80360100 605f820439SDave Liu #define SPR_8343_REV10 0x80370100 615f820439SDave Liu 62f6eda7f8SDave Liu #define SPR_8349E_REV11 0x80300101 635f820439SDave Liu #define SPR_8349_REV11 0x80310101 645f820439SDave Liu #define SPR_8347E_REV11_TBGA 0x80320101 655f820439SDave Liu #define SPR_8347_REV11_TBGA 0x80330101 665f820439SDave Liu #define SPR_8347E_REV11_PBGA 0x80340101 675f820439SDave Liu #define SPR_8347_REV11_PBGA 0x80350101 685f820439SDave Liu #define SPR_8343E_REV11 0x80360101 695f820439SDave Liu #define SPR_8343_REV11 0x80370101 705f820439SDave Liu 715f820439SDave Liu #define SPR_8360E_REV10 0x80480010 725f820439SDave Liu #define SPR_8360_REV10 0x80490010 735f820439SDave Liu #define SPR_8360E_REV11 0x80480011 745f820439SDave Liu #define SPR_8360_REV11 0x80490011 755f820439SDave Liu #define SPR_8360E_REV12 0x80480012 765f820439SDave Liu #define SPR_8360_REV12 0x80490012 77f046ccd1SEran Liberty 78*e080313cSDave Liu /* SPCR - System Priority Configuration Register 79f046ccd1SEran Liberty */ 80*e080313cSDave Liu #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 81*e080313cSDave Liu #define SPCR_PCIHPE_SHIFT (31-3) 82*e080313cSDave Liu #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 83*e080313cSDave Liu #define SPCR_PCIPR_SHIFT (31-7) 84*e080313cSDave Liu #define SPCR_OPT 0x00800000 /* Optimize */ 85*e080313cSDave Liu #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 86*e080313cSDave Liu #define SPCR_TBEN_SHIFT (31-9) 87*e080313cSDave Liu #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 88*e080313cSDave Liu #define SPCR_COREPR_SHIFT (31-11) 89*e080313cSDave Liu 90*e080313cSDave Liu #if defined(CONFIG_MPC8349) 91*e080313cSDave Liu /* SPCR bits - MPC8349 specific */ 92*e080313cSDave Liu #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 93*e080313cSDave Liu #define SPCR_TSEC1DP_SHIFT (31-19) 94*e080313cSDave Liu #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 95*e080313cSDave Liu #define SPCR_TSEC1BDP_SHIFT (31-21) 96*e080313cSDave Liu #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 97*e080313cSDave Liu #define SPCR_TSEC1EP_SHIFT (31-23) 98*e080313cSDave Liu #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 99*e080313cSDave Liu #define SPCR_TSEC2DP_SHIFT (31-27) 100*e080313cSDave Liu #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 101*e080313cSDave Liu #define SPCR_TSEC2BDP_SHIFT (31-29) 102*e080313cSDave Liu #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 103*e080313cSDave Liu #define SPCR_TSEC2EP_SHIFT (31-31) 104*e080313cSDave Liu #endif 105*e080313cSDave Liu 106*e080313cSDave Liu /* SICRL/H - System I/O Configuration Register Low/High 107*e080313cSDave Liu */ 108*e080313cSDave Liu #if defined(CONFIG_MPC8349) 109*e080313cSDave Liu /* SICRL bits - MPC8349 specific */ 110*e080313cSDave Liu #define SICRL_LDP_A 0x80000000 111*e080313cSDave Liu #define SICRL_USB1 0x40000000 112*e080313cSDave Liu #define SICRL_USB0 0x20000000 113*e080313cSDave Liu #define SICRL_UART 0x0C000000 114*e080313cSDave Liu #define SICRL_GPIO1_A 0x02000000 115*e080313cSDave Liu #define SICRL_GPIO1_B 0x01000000 116*e080313cSDave Liu #define SICRL_GPIO1_C 0x00800000 117*e080313cSDave Liu #define SICRL_GPIO1_D 0x00400000 118*e080313cSDave Liu #define SICRL_GPIO1_E 0x00200000 119*e080313cSDave Liu #define SICRL_GPIO1_F 0x00180000 120*e080313cSDave Liu #define SICRL_GPIO1_G 0x00040000 121*e080313cSDave Liu #define SICRL_GPIO1_H 0x00020000 122*e080313cSDave Liu #define SICRL_GPIO1_I 0x00010000 123*e080313cSDave Liu #define SICRL_GPIO1_J 0x00008000 124*e080313cSDave Liu #define SICRL_GPIO1_K 0x00004000 125*e080313cSDave Liu #define SICRL_GPIO1_L 0x00003000 126*e080313cSDave Liu 127*e080313cSDave Liu /* SICRH bits - MPC8349 specific */ 128*e080313cSDave Liu #define SICRH_DDR 0x80000000 129*e080313cSDave Liu #define SICRH_TSEC1_A 0x10000000 130*e080313cSDave Liu #define SICRH_TSEC1_B 0x08000000 131*e080313cSDave Liu #define SICRH_TSEC1_C 0x04000000 132*e080313cSDave Liu #define SICRH_TSEC1_D 0x02000000 133*e080313cSDave Liu #define SICRH_TSEC1_E 0x01000000 134*e080313cSDave Liu #define SICRH_TSEC1_F 0x00800000 135*e080313cSDave Liu #define SICRH_TSEC2_A 0x00400000 136*e080313cSDave Liu #define SICRH_TSEC2_B 0x00200000 137*e080313cSDave Liu #define SICRH_TSEC2_C 0x00100000 138*e080313cSDave Liu #define SICRH_TSEC2_D 0x00080000 139*e080313cSDave Liu #define SICRH_TSEC2_E 0x00040000 140*e080313cSDave Liu #define SICRH_TSEC2_F 0x00020000 141*e080313cSDave Liu #define SICRH_TSEC2_G 0x00010000 142*e080313cSDave Liu #define SICRH_TSEC2_H 0x00008000 143*e080313cSDave Liu #define SICRH_GPIO2_A 0x00004000 144*e080313cSDave Liu #define SICRH_GPIO2_B 0x00002000 145*e080313cSDave Liu #define SICRH_GPIO2_C 0x00001000 146*e080313cSDave Liu #define SICRH_GPIO2_D 0x00000800 147*e080313cSDave Liu #define SICRH_GPIO2_E 0x00000400 148*e080313cSDave Liu #define SICRH_GPIO2_F 0x00000200 149*e080313cSDave Liu #define SICRH_GPIO2_G 0x00000180 150*e080313cSDave Liu #define SICRH_GPIO2_H 0x00000060 151*e080313cSDave Liu #define SICRH_TSOBI1 0x00000002 152*e080313cSDave Liu #define SICRH_TSOBI2 0x00000001 153*e080313cSDave Liu 154*e080313cSDave Liu #elif defined(CONFIG_MPC8360) 155*e080313cSDave Liu /* SICRL bits - MPC8360 specific */ 156*e080313cSDave Liu #define SICRL_LDP_A 0xC0000000 157*e080313cSDave Liu #define SICRL_LCLK_1 0x10000000 158*e080313cSDave Liu #define SICRL_LCLK_2 0x08000000 159*e080313cSDave Liu #define SICRL_SRCID_A 0x03000000 160*e080313cSDave Liu #define SICRL_IRQ_CKSTP_A 0x00C00000 161*e080313cSDave Liu 162*e080313cSDave Liu /* SICRH bits - MPC8360 specific */ 163*e080313cSDave Liu #define SICRH_DDR 0x80000000 164*e080313cSDave Liu #define SICRH_SECONDARY_DDR 0x40000000 165*e080313cSDave Liu #define SICRH_SDDROE 0x20000000 166*e080313cSDave Liu #define SICRH_IRQ3 0x10000000 167*e080313cSDave Liu #define SICRH_UC1EOBI 0x00000004 168*e080313cSDave Liu #define SICRH_UC2E1OBI 0x00000002 169*e080313cSDave Liu #define SICRH_UC2E2OBI 0x00000001 170*e080313cSDave Liu #endif 171*e080313cSDave Liu 172*e080313cSDave Liu /* SWCRR - System Watchdog Control Register 173*e080313cSDave Liu */ 174*e080313cSDave Liu #define SWCRR 0x0204 /* Register offset to immr */ 175*e080313cSDave Liu #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 176*e080313cSDave Liu #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 177*e080313cSDave Liu #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 178*e080313cSDave Liu #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 179*e080313cSDave Liu #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 180*e080313cSDave Liu 181*e080313cSDave Liu /* SWCNR - System Watchdog Counter Register 182*e080313cSDave Liu */ 183*e080313cSDave Liu #define SWCNR 0x0208 /* Register offset to immr */ 184*e080313cSDave Liu #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 185*e080313cSDave Liu #define SWCNR_RES ~(SWCNR_SWCN) 186*e080313cSDave Liu 187*e080313cSDave Liu /* SWSRR - System Watchdog Service Register 188*e080313cSDave Liu */ 189*e080313cSDave Liu #define SWSRR 0x020E /* Register offset to immr */ 190*e080313cSDave Liu 191*e080313cSDave Liu /* ACR - Arbiter Configuration Register 192*e080313cSDave Liu */ 193*e080313cSDave Liu #define ACR_COREDIS 0x10000000 /* Core disable */ 194*e080313cSDave Liu #define ACR_COREDIS_SHIFT (31-7) 195*e080313cSDave Liu #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 196*e080313cSDave Liu #define ACR_PIPE_DEP_SHIFT (31-15) 197*e080313cSDave Liu #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 198*e080313cSDave Liu #define ACR_PCI_RPTCNT_SHIFT (31-19) 199*e080313cSDave Liu #define ACR_RPTCNT 0x00000700 /* Repeat count */ 200*e080313cSDave Liu #define ACR_RPTCNT_SHIFT (31-23) 201*e080313cSDave Liu #define ACR_APARK 0x00000030 /* Address parking */ 202*e080313cSDave Liu #define ACR_APARK_SHIFT (31-27) 203*e080313cSDave Liu #define ACR_PARKM 0x0000000F /* Parking master */ 204*e080313cSDave Liu #define ACR_PARKM_SHIFT (31-31) 205*e080313cSDave Liu 206*e080313cSDave Liu /* ATR - Arbiter Timers Register 207*e080313cSDave Liu */ 208*e080313cSDave Liu #define ATR_DTO 0x00FF0000 /* Data time out */ 209*e080313cSDave Liu #define ATR_ATO 0x000000FF /* Address time out */ 210*e080313cSDave Liu 211*e080313cSDave Liu /* AER - Arbiter Event Register 212*e080313cSDave Liu */ 213*e080313cSDave Liu #define AER_ETEA 0x00000020 /* Transfer error */ 214*e080313cSDave Liu #define AER_RES 0x00000010 /* Reserved transfer type */ 215*e080313cSDave Liu #define AER_ECW 0x00000008 /* External control word transfer type */ 216*e080313cSDave Liu #define AER_AO 0x00000004 /* Address Only transfer type */ 217*e080313cSDave Liu #define AER_DTO 0x00000002 /* Data time out */ 218*e080313cSDave Liu #define AER_ATO 0x00000001 /* Address time out */ 219*e080313cSDave Liu 220*e080313cSDave Liu /* AEATR - Arbiter Event Address Register 221*e080313cSDave Liu */ 222*e080313cSDave Liu #define AEATR_EVENT 0x07000000 /* Event type */ 223*e080313cSDave Liu #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 224*e080313cSDave Liu #define AEATR_TBST 0x00000800 /* Transfer burst */ 225*e080313cSDave Liu #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 226*e080313cSDave Liu #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 227*e080313cSDave Liu 228*e080313cSDave Liu /* HRCWL - Hard Reset Configuration Word Low 229*e080313cSDave Liu */ 230*e080313cSDave Liu #define HRCWL_LBIUCM 0x80000000 231*e080313cSDave Liu #define HRCWL_LBIUCM_SHIFT 31 232*e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 233*e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 234*e080313cSDave Liu 235*e080313cSDave Liu #define HRCWL_DDRCM 0x40000000 236*e080313cSDave Liu #define HRCWL_DDRCM_SHIFT 30 237*e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 238*e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 239*e080313cSDave Liu 240*e080313cSDave Liu #define HRCWL_SPMF 0x0f000000 241*e080313cSDave Liu #define HRCWL_SPMF_SHIFT 24 242*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 243*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 244*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 245*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 246*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 247*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 248*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 249*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 250*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 251*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 252*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 253*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 254*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 255*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 256*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 257*e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 258*e080313cSDave Liu 259*e080313cSDave Liu #define HRCWL_VCO_BYPASS 0x00000000 260*e080313cSDave Liu #define HRCWL_VCO_1X2 0x00000000 261*e080313cSDave Liu #define HRCWL_VCO_1X4 0x00200000 262*e080313cSDave Liu #define HRCWL_VCO_1X8 0x00400000 263*e080313cSDave Liu 264*e080313cSDave Liu #define HRCWL_COREPLL 0x007F0000 265*e080313cSDave Liu #define HRCWL_COREPLL_SHIFT 16 266*e080313cSDave Liu #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 267*e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1X1 0x00020000 268*e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 269*e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2X1 0x00040000 270*e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 271*e080313cSDave Liu #define HRCWL_CORE_TO_CSB_3X1 0x00060000 272*e080313cSDave Liu 273*e080313cSDave Liu #if defined(CONFIG_MPC8360) 274*e080313cSDave Liu #define HRCWL_CEVCOD 0x000000C0 275*e080313cSDave Liu #define HRCWL_CEVCOD_SHIFT 6 276*e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 277*e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 278*e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 279*e080313cSDave Liu 280*e080313cSDave Liu #define HRCWL_CEPDF 0x00000020 281*e080313cSDave Liu #define HRCWL_CEPDF_SHIFT 5 282*e080313cSDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 283*e080313cSDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 284*e080313cSDave Liu 285*e080313cSDave Liu #define HRCWL_CEPMF 0x0000001F 286*e080313cSDave Liu #define HRCWL_CEPMF_SHIFT 0 287*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 288*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 289*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 290*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 291*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 292*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 293*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 294*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 295*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 296*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 297*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 298*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 299*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 300*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 301*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 302*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 303*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 304*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 305*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 306*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 307*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 308*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 309*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 310*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 311*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 312*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 313*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 314*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 315*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 316*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 317*e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 318*e080313cSDave Liu #endif 319*e080313cSDave Liu 320*e080313cSDave Liu /* HRCWH - Hardware Reset Configuration Word High 321*e080313cSDave Liu */ 322*e080313cSDave Liu #define HRCWH_PCI_HOST 0x80000000 323*e080313cSDave Liu #define HRCWH_PCI_HOST_SHIFT 31 324*e080313cSDave Liu #define HRCWH_PCI_AGENT 0x00000000 325*e080313cSDave Liu 326*e080313cSDave Liu #if defined(CONFIG_MPC8349) 327*e080313cSDave Liu #define HRCWH_32_BIT_PCI 0x00000000 328*e080313cSDave Liu #define HRCWH_64_BIT_PCI 0x40000000 329*e080313cSDave Liu #endif 330*e080313cSDave Liu 331*e080313cSDave Liu #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 332*e080313cSDave Liu #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 333*e080313cSDave Liu 334*e080313cSDave Liu #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 335*e080313cSDave Liu #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 336*e080313cSDave Liu 337*e080313cSDave Liu #if defined(CONFIG_MPC8349) 338*e080313cSDave Liu #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 339*e080313cSDave Liu #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 340*e080313cSDave Liu 341*e080313cSDave Liu #elif defined(CONFIG_MPC8360) 342*e080313cSDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 343*e080313cSDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 344*e080313cSDave Liu #endif 345*e080313cSDave Liu 346*e080313cSDave Liu #define HRCWH_CORE_DISABLE 0x08000000 347*e080313cSDave Liu #define HRCWH_CORE_ENABLE 0x00000000 348*e080313cSDave Liu 349*e080313cSDave Liu #define HRCWH_FROM_0X00000100 0x00000000 350*e080313cSDave Liu #define HRCWH_FROM_0XFFF00100 0x04000000 351*e080313cSDave Liu 352*e080313cSDave Liu #define HRCWH_BOOTSEQ_DISABLE 0x00000000 353*e080313cSDave Liu #define HRCWH_BOOTSEQ_NORMAL 0x01000000 354*e080313cSDave Liu #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 355*e080313cSDave Liu 356*e080313cSDave Liu #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 357*e080313cSDave Liu #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 358*e080313cSDave Liu 359*e080313cSDave Liu #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 360*e080313cSDave Liu #define HRCWH_ROM_LOC_PCI1 0x00100000 361*e080313cSDave Liu #if defined(CONFIG_MPC8349) 362*e080313cSDave Liu #define HRCWH_ROM_LOC_PCI2 0x00200000 363*e080313cSDave Liu #endif 364*e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 365*e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 366*e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 367*e080313cSDave Liu 368*e080313cSDave Liu #if defined(CONFIG_MPC8349) 369*e080313cSDave Liu #define HRCWH_TSEC1M_IN_RGMII 0x00000000 370*e080313cSDave Liu #define HRCWH_TSEC1M_IN_RTBI 0x00004000 371*e080313cSDave Liu #define HRCWH_TSEC1M_IN_GMII 0x00008000 372*e080313cSDave Liu #define HRCWH_TSEC1M_IN_TBI 0x0000C000 373*e080313cSDave Liu #define HRCWH_TSEC2M_IN_RGMII 0x00000000 374*e080313cSDave Liu #define HRCWH_TSEC2M_IN_RTBI 0x00001000 375*e080313cSDave Liu #define HRCWH_TSEC2M_IN_GMII 0x00002000 376*e080313cSDave Liu #define HRCWH_TSEC2M_IN_TBI 0x00003000 377*e080313cSDave Liu #endif 378*e080313cSDave Liu 379*e080313cSDave Liu #if defined(CONFIG_MPC8360) 380*e080313cSDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 381*e080313cSDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 382*e080313cSDave Liu #endif 383*e080313cSDave Liu 384*e080313cSDave Liu #define HRCWH_BIG_ENDIAN 0x00000000 385*e080313cSDave Liu #define HRCWH_LITTLE_ENDIAN 0x00000008 386*e080313cSDave Liu 387*e080313cSDave Liu #define HRCWH_LALE_NORMAL 0x00000000 388*e080313cSDave Liu #define HRCWH_LALE_EARLY 0x00000004 389*e080313cSDave Liu 390*e080313cSDave Liu #define HRCWH_LDP_SET 0x00000000 391*e080313cSDave Liu #define HRCWH_LDP_CLEAR 0x00000002 392*e080313cSDave Liu 393*e080313cSDave Liu /* RSR - Reset Status Register 394*e080313cSDave Liu */ 395*e080313cSDave Liu #define RSR_RSTSRC 0xE0000000 /* Reset source */ 396*e080313cSDave Liu #define RSR_RSTSRC_SHIFT 29 397*e080313cSDave Liu #define RSR_BSF 0x00010000 /* Boot seq. fail */ 398*e080313cSDave Liu #define RSR_BSF_SHIFT 16 399*e080313cSDave Liu #define RSR_SWSR 0x00002000 /* software soft reset */ 400*e080313cSDave Liu #define RSR_SWSR_SHIFT 13 401*e080313cSDave Liu #define RSR_SWHR 0x00001000 /* software hard reset */ 402*e080313cSDave Liu #define RSR_SWHR_SHIFT 12 403*e080313cSDave Liu #define RSR_JHRS 0x00000200 /* jtag hreset */ 404*e080313cSDave Liu #define RSR_JHRS_SHIFT 9 405*e080313cSDave Liu #define RSR_JSRS 0x00000100 /* jtag sreset status */ 406*e080313cSDave Liu #define RSR_JSRS_SHIFT 8 407*e080313cSDave Liu #define RSR_CSHR 0x00000010 /* checkstop reset status */ 408*e080313cSDave Liu #define RSR_CSHR_SHIFT 4 409*e080313cSDave Liu #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 410*e080313cSDave Liu #define RSR_SWRS_SHIFT 3 411*e080313cSDave Liu #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 412*e080313cSDave Liu #define RSR_BMRS_SHIFT 2 413*e080313cSDave Liu #define RSR_SRS 0x00000002 /* soft reset status */ 414*e080313cSDave Liu #define RSR_SRS_SHIFT 1 415*e080313cSDave Liu #define RSR_HRS 0x00000001 /* hard reset status */ 416*e080313cSDave Liu #define RSR_HRS_SHIFT 0 417*e080313cSDave Liu #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 418*e080313cSDave Liu RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 419*e080313cSDave Liu RSR_BMRS | RSR_SRS | RSR_HRS) 420*e080313cSDave Liu /* RMR - Reset Mode Register 421*e080313cSDave Liu */ 422*e080313cSDave Liu #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 423*e080313cSDave Liu #define RMR_CSRE_SHIFT 0 424*e080313cSDave Liu #define RMR_RES ~(RMR_CSRE) 425*e080313cSDave Liu 426*e080313cSDave Liu /* RCR - Reset Control Register 427*e080313cSDave Liu */ 428*e080313cSDave Liu #define RCR_SWHR 0x00000002 /* software hard reset */ 429*e080313cSDave Liu #define RCR_SWSR 0x00000001 /* software soft reset */ 430*e080313cSDave Liu #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 431*e080313cSDave Liu 432*e080313cSDave Liu /* RCER - Reset Control Enable Register 433*e080313cSDave Liu */ 434*e080313cSDave Liu #define RCER_CRE 0x00000001 /* software hard reset */ 435*e080313cSDave Liu #define RCER_RES ~(RCER_CRE) 436*e080313cSDave Liu 437*e080313cSDave Liu /* SPMR - System PLL Mode Register 438*e080313cSDave Liu */ 439*e080313cSDave Liu #define SPMR_LBIUCM 0x80000000 440*e080313cSDave Liu #define SPMR_DDRCM 0x40000000 441*e080313cSDave Liu #define SPMR_SPMF 0x0F000000 442*e080313cSDave Liu #define SPMR_CKID 0x00800000 443*e080313cSDave Liu #define SPMR_CKID_SHIFT 23 444*e080313cSDave Liu #define SPMR_COREPLL 0x007F0000 445*e080313cSDave Liu #define SPMR_CEVCOD 0x000000C0 446*e080313cSDave Liu #define SPMR_CEPDF 0x00000020 447*e080313cSDave Liu #define SPMR_CEPMF 0x0000001F 448*e080313cSDave Liu 449*e080313cSDave Liu /* OCCR - Output Clock Control Register 450*e080313cSDave Liu */ 451*e080313cSDave Liu #define OCCR_PCICOE0 0x80000000 452*e080313cSDave Liu #define OCCR_PCICOE1 0x40000000 453*e080313cSDave Liu #define OCCR_PCICOE2 0x20000000 454*e080313cSDave Liu #define OCCR_PCICOE3 0x10000000 455*e080313cSDave Liu #define OCCR_PCICOE4 0x08000000 456*e080313cSDave Liu #define OCCR_PCICOE5 0x04000000 457*e080313cSDave Liu #define OCCR_PCICOE6 0x02000000 458*e080313cSDave Liu #define OCCR_PCICOE7 0x01000000 459*e080313cSDave Liu #define OCCR_PCICD0 0x00800000 460*e080313cSDave Liu #define OCCR_PCICD1 0x00400000 461*e080313cSDave Liu #define OCCR_PCICD2 0x00200000 462*e080313cSDave Liu #define OCCR_PCICD3 0x00100000 463*e080313cSDave Liu #define OCCR_PCICD4 0x00080000 464*e080313cSDave Liu #define OCCR_PCICD5 0x00040000 465*e080313cSDave Liu #define OCCR_PCICD6 0x00020000 466*e080313cSDave Liu #define OCCR_PCICD7 0x00010000 467*e080313cSDave Liu #define OCCR_PCI1CR 0x00000002 468*e080313cSDave Liu #define OCCR_PCI2CR 0x00000001 469*e080313cSDave Liu #define OCCR_PCICR OCCR_PCI1CR 470*e080313cSDave Liu 471*e080313cSDave Liu /* SCCR - System Clock Control Register 472*e080313cSDave Liu */ 473*e080313cSDave Liu #define SCCR_ENCCM 0x03000000 474*e080313cSDave Liu #define SCCR_ENCCM_SHIFT 24 475*e080313cSDave Liu #define SCCR_ENCCM_0 0x00000000 476*e080313cSDave Liu #define SCCR_ENCCM_1 0x01000000 477*e080313cSDave Liu #define SCCR_ENCCM_2 0x02000000 478*e080313cSDave Liu #define SCCR_ENCCM_3 0x03000000 479*e080313cSDave Liu 480*e080313cSDave Liu #define SCCR_PCICM 0x00010000 481*e080313cSDave Liu #define SCCR_PCICM_SHIFT 16 482*e080313cSDave Liu 483*e080313cSDave Liu /* SCCR bits - MPC8349 specific */ 484*e080313cSDave Liu #define SCCR_TSEC1CM 0xc0000000 485*e080313cSDave Liu #define SCCR_TSEC1CM_SHIFT 30 486*e080313cSDave Liu #define SCCR_TSEC1CM_0 0x00000000 487*e080313cSDave Liu #define SCCR_TSEC1CM_1 0x40000000 488*e080313cSDave Liu #define SCCR_TSEC1CM_2 0x80000000 489*e080313cSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 490*e080313cSDave Liu 491*e080313cSDave Liu #define SCCR_TSEC2CM 0x30000000 492*e080313cSDave Liu #define SCCR_TSEC2CM_SHIFT 28 493*e080313cSDave Liu #define SCCR_TSEC2CM_0 0x00000000 494*e080313cSDave Liu #define SCCR_TSEC2CM_1 0x10000000 495*e080313cSDave Liu #define SCCR_TSEC2CM_2 0x20000000 496*e080313cSDave Liu #define SCCR_TSEC2CM_3 0x30000000 497*e080313cSDave Liu 498*e080313cSDave Liu #define SCCR_USBMPHCM 0x00c00000 499*e080313cSDave Liu #define SCCR_USBMPHCM_SHIFT 22 500*e080313cSDave Liu #define SCCR_USBDRCM 0x00300000 501*e080313cSDave Liu #define SCCR_USBDRCM_SHIFT 20 502*e080313cSDave Liu 503*e080313cSDave Liu #define SCCR_USBCM_0 0x00000000 504*e080313cSDave Liu #define SCCR_USBCM_1 0x00500000 505*e080313cSDave Liu #define SCCR_USBCM_2 0x00A00000 506*e080313cSDave Liu #define SCCR_USBCM_3 0x00F00000 507*e080313cSDave Liu 508*e080313cSDave Liu #define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ 509*e080313cSDave Liu | SCCR_TSEC2CM_3 \ 510*e080313cSDave Liu | SCCR_ENCCM_3 \ 511*e080313cSDave Liu | SCCR_USBCM_3 ) 512*e080313cSDave Liu 513*e080313cSDave Liu #define SCCR_DEFAULT 0xFFFFFFFF 514*e080313cSDave Liu 515*e080313cSDave Liu /* CSn_BDNS - Chip Select memory Bounds Register 516*e080313cSDave Liu */ 517*e080313cSDave Liu #define CSBNDS_SA 0x00FF0000 518*e080313cSDave Liu #define CSBNDS_SA_SHIFT 8 519*e080313cSDave Liu #define CSBNDS_EA 0x000000FF 520*e080313cSDave Liu #define CSBNDS_EA_SHIFT 24 521*e080313cSDave Liu 522*e080313cSDave Liu /* CSn_CONFIG - Chip Select Configuration Register 523*e080313cSDave Liu */ 524*e080313cSDave Liu #define CSCONFIG_EN 0x80000000 525*e080313cSDave Liu #define CSCONFIG_AP 0x00800000 526*e080313cSDave Liu #define CSCONFIG_ROW_BIT 0x00000700 527*e080313cSDave Liu #define CSCONFIG_ROW_BIT_12 0x00000000 528*e080313cSDave Liu #define CSCONFIG_ROW_BIT_13 0x00000100 529*e080313cSDave Liu #define CSCONFIG_ROW_BIT_14 0x00000200 530*e080313cSDave Liu #define CSCONFIG_COL_BIT 0x00000007 531*e080313cSDave Liu #define CSCONFIG_COL_BIT_8 0x00000000 532*e080313cSDave Liu #define CSCONFIG_COL_BIT_9 0x00000001 533*e080313cSDave Liu #define CSCONFIG_COL_BIT_10 0x00000002 534*e080313cSDave Liu #define CSCONFIG_COL_BIT_11 0x00000003 535*e080313cSDave Liu 536*e080313cSDave Liu /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 537*e080313cSDave Liu */ 538*e080313cSDave Liu #define TIMING_CFG1_PRETOACT 0x70000000 539*e080313cSDave Liu #define TIMING_CFG1_PRETOACT_SHIFT 28 540*e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE 0x0F000000 541*e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE_SHIFT 24 542*e080313cSDave Liu #define TIMING_CFG1_ACTTORW 0x00700000 543*e080313cSDave Liu #define TIMING_CFG1_ACTTORW_SHIFT 20 544*e080313cSDave Liu #define TIMING_CFG1_CASLAT 0x00070000 545*e080313cSDave Liu #define TIMING_CFG1_CASLAT_SHIFT 16 546*e080313cSDave Liu #define TIMING_CFG1_REFREC 0x0000F000 547*e080313cSDave Liu #define TIMING_CFG1_REFREC_SHIFT 12 548*e080313cSDave Liu #define TIMING_CFG1_WRREC 0x00000700 549*e080313cSDave Liu #define TIMING_CFG1_WRREC_SHIFT 8 550*e080313cSDave Liu #define TIMING_CFG1_ACTTOACT 0x00000070 551*e080313cSDave Liu #define TIMING_CFG1_ACTTOACT_SHIFT 4 552*e080313cSDave Liu #define TIMING_CFG1_WRTORD 0x00000007 553*e080313cSDave Liu #define TIMING_CFG1_WRTORD_SHIFT 0 554*e080313cSDave Liu #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 555*e080313cSDave Liu #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 556*e080313cSDave Liu 557*e080313cSDave Liu /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 558*e080313cSDave Liu */ 559*e080313cSDave Liu #define TIMING_CFG2_CPO 0x0F000000 560*e080313cSDave Liu #define TIMING_CFG2_CPO_SHIFT 24 561*e080313cSDave Liu #define TIMING_CFG2_ACSM 0x00080000 562*e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 563*e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 564*e080313cSDave Liu #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 565*e080313cSDave Liu 566*e080313cSDave Liu /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 567*e080313cSDave Liu */ 568*e080313cSDave Liu #define SDRAM_CFG_MEM_EN 0x80000000 569*e080313cSDave Liu #define SDRAM_CFG_SREN 0x40000000 570*e080313cSDave Liu #define SDRAM_CFG_ECC_EN 0x20000000 571*e080313cSDave Liu #define SDRAM_CFG_RD_EN 0x10000000 572*e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE 0x03000000 573*e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 574*e080313cSDave Liu #define SDRAM_CFG_DYN_PWR 0x00200000 575*e080313cSDave Liu #define SDRAM_CFG_32_BE 0x00080000 576*e080313cSDave Liu #define SDRAM_CFG_8_BE 0x00040000 577*e080313cSDave Liu #define SDRAM_CFG_NCAP 0x00020000 578*e080313cSDave Liu #define SDRAM_CFG_2T_EN 0x00008000 579*e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 580*e080313cSDave Liu 581*e080313cSDave Liu /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 582*e080313cSDave Liu */ 583*e080313cSDave Liu #define SDRAM_MODE_ESD 0xFFFF0000 584*e080313cSDave Liu #define SDRAM_MODE_ESD_SHIFT 16 585*e080313cSDave Liu #define SDRAM_MODE_SD 0x0000FFFF 586*e080313cSDave Liu #define SDRAM_MODE_SD_SHIFT 0 587*e080313cSDave Liu #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 588*e080313cSDave Liu #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 589*e080313cSDave Liu #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 590*e080313cSDave Liu #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 591*e080313cSDave Liu #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 592*e080313cSDave Liu #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 593*e080313cSDave Liu #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 594*e080313cSDave Liu #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 595*e080313cSDave Liu #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 596*e080313cSDave Liu #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 597*e080313cSDave Liu #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 598*e080313cSDave Liu #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 599*e080313cSDave Liu #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 600*e080313cSDave Liu #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 601*e080313cSDave Liu #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 602*e080313cSDave Liu #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 603*e080313cSDave Liu #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 604*e080313cSDave Liu #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 605*e080313cSDave Liu #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 606*e080313cSDave Liu 607*e080313cSDave Liu /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 608*e080313cSDave Liu */ 609*e080313cSDave Liu #define SDRAM_INTERVAL_REFINT 0x3FFF0000 610*e080313cSDave Liu #define SDRAM_INTERVAL_REFINT_SHIFT 16 611*e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 612*e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 613*e080313cSDave Liu 614*e080313cSDave Liu /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 615*e080313cSDave Liu */ 616*e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 617*e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 618*e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 619*e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 620*e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 621*e080313cSDave Liu 622*e080313cSDave Liu /* ECC_ERR_INJECT - Memory data path error injection mask ECC 623*e080313cSDave Liu */ 624*e080313cSDave Liu #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 625*e080313cSDave Liu #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 626*e080313cSDave Liu #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 627*e080313cSDave Liu #define ECC_ERR_INJECT_EEIM_SHIFT 0 628*e080313cSDave Liu 629*e080313cSDave Liu /* CAPTURE_ECC - Memory data path read capture ECC 630*e080313cSDave Liu */ 631*e080313cSDave Liu #define CAPTURE_ECC_ECE (0xff000000>>24) 632*e080313cSDave Liu #define CAPTURE_ECC_ECE_SHIFT 0 633*e080313cSDave Liu 634*e080313cSDave Liu /* ERR_DETECT - Memory error detect 635*e080313cSDave Liu */ 636*e080313cSDave Liu #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 637*e080313cSDave Liu #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 638*e080313cSDave Liu #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 639*e080313cSDave Liu #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 640*e080313cSDave Liu 641*e080313cSDave Liu /* ERR_DISABLE - Memory error disable 642*e080313cSDave Liu */ 643*e080313cSDave Liu #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 644*e080313cSDave Liu #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 645*e080313cSDave Liu #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 646*e080313cSDave Liu #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 647*e080313cSDave Liu ECC_ERROR_DISABLE_MBED) 648*e080313cSDave Liu /* ERR_INT_EN - Memory error interrupt enable 649*e080313cSDave Liu */ 650*e080313cSDave Liu #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 651*e080313cSDave Liu #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 652*e080313cSDave Liu #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 653*e080313cSDave Liu #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 654*e080313cSDave Liu ECC_ERR_INT_EN_MSEE) 655*e080313cSDave Liu /* CAPTURE_ATTRIBUTES - Memory error attributes capture 656*e080313cSDave Liu */ 657*e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 658*e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM_SHIFT 28 659*e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 660*e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 661*e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 662*e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 663*e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 664*e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 665*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 666*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 667*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 668*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 669*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 670*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 671*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 672*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_I2C 0x9 673*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 674*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 675*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 676*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_DMA 0xF 677*e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_SHIFT 16 678*e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 679*e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 680*e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_READ 0x2 681*e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 682*e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_SHIFT 12 683*e080313cSDave Liu #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 684*e080313cSDave Liu 685*e080313cSDave Liu /* ERR_SBE - Single bit ECC memory error management 686*e080313cSDave Liu */ 687*e080313cSDave Liu #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 688*e080313cSDave Liu #define ECC_ERROR_MAN_SBET_SHIFT 16 689*e080313cSDave Liu #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 690*e080313cSDave Liu #define ECC_ERROR_MAN_SBEC_SHIFT 0 691*e080313cSDave Liu 692*e080313cSDave Liu /* BR - Base Registers 693*e080313cSDave Liu */ 694*e080313cSDave Liu #define BR0 0x5000 /* Register offset to immr */ 695f046ccd1SEran Liberty #define BR1 0x5008 696f046ccd1SEran Liberty #define BR2 0x5010 697f046ccd1SEran Liberty #define BR3 0x5018 698f046ccd1SEran Liberty #define BR4 0x5020 699f046ccd1SEran Liberty #define BR5 0x5028 700f046ccd1SEran Liberty #define BR6 0x5030 701f046ccd1SEran Liberty #define BR7 0x5038 702f046ccd1SEran Liberty 703f046ccd1SEran Liberty #define BR_BA 0xFFFF8000 704f046ccd1SEran Liberty #define BR_BA_SHIFT 15 705f046ccd1SEran Liberty #define BR_PS 0x00001800 706f046ccd1SEran Liberty #define BR_PS_SHIFT 11 707e6f2e902SMarian Balakowicz #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 708e6f2e902SMarian Balakowicz #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 709e6f2e902SMarian Balakowicz #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 710f046ccd1SEran Liberty #define BR_DECC 0x00000600 711f046ccd1SEran Liberty #define BR_DECC_SHIFT 9 712f046ccd1SEran Liberty #define BR_WP 0x00000100 713f046ccd1SEran Liberty #define BR_WP_SHIFT 8 714f046ccd1SEran Liberty #define BR_MSEL 0x000000E0 715f046ccd1SEran Liberty #define BR_MSEL_SHIFT 5 716e6f2e902SMarian Balakowicz #define BR_MS_GPCM 0x00000000 /* GPCM */ 717e6f2e902SMarian Balakowicz #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 718e6f2e902SMarian Balakowicz #define BR_MS_UPMA 0x00000080 /* UPMA */ 719e6f2e902SMarian Balakowicz #define BR_MS_UPMB 0x000000A0 /* UPMB */ 720e6f2e902SMarian Balakowicz #define BR_MS_UPMC 0x000000C0 /* UPMC */ 7215f820439SDave Liu #if defined(CONFIG_MPC8360) 7225f820439SDave Liu #define BR_ATOM 0x0000000C 7235f820439SDave Liu #define BR_ATOM_SHIFT 2 7245f820439SDave Liu #endif 725f046ccd1SEran Liberty #define BR_V 0x00000001 726f046ccd1SEran Liberty #define BR_V_SHIFT 0 727*e080313cSDave Liu 7285f820439SDave Liu #if defined(CONFIG_MPC8349) 729f046ccd1SEran Liberty #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) 7305f820439SDave Liu #elif defined(CONFIG_MPC8360) 7315f820439SDave Liu #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) 7325f820439SDave Liu #endif 733f046ccd1SEran Liberty 734*e080313cSDave Liu /* OR - Option Registers 735*e080313cSDave Liu */ 736*e080313cSDave Liu #define OR0 0x5004 /* Register offset to immr */ 737f046ccd1SEran Liberty #define OR1 0x500C 738f046ccd1SEran Liberty #define OR2 0x5014 739f046ccd1SEran Liberty #define OR3 0x501C 740f046ccd1SEran Liberty #define OR4 0x5024 741f046ccd1SEran Liberty #define OR5 0x502C 742f046ccd1SEran Liberty #define OR6 0x5034 743f046ccd1SEran Liberty #define OR7 0x503C 744f046ccd1SEran Liberty 745f046ccd1SEran Liberty #define OR_GPCM_AM 0xFFFF8000 746f046ccd1SEran Liberty #define OR_GPCM_AM_SHIFT 15 747f046ccd1SEran Liberty #define OR_GPCM_BCTLD 0x00001000 748f046ccd1SEran Liberty #define OR_GPCM_BCTLD_SHIFT 12 749f046ccd1SEran Liberty #define OR_GPCM_CSNT 0x00000800 750f046ccd1SEran Liberty #define OR_GPCM_CSNT_SHIFT 11 751f046ccd1SEran Liberty #define OR_GPCM_ACS 0x00000600 752f046ccd1SEran Liberty #define OR_GPCM_ACS_SHIFT 9 753e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b10 0x00000400 754e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b11 0x00000600 755f046ccd1SEran Liberty #define OR_GPCM_XACS 0x00000100 756f046ccd1SEran Liberty #define OR_GPCM_XACS_SHIFT 8 757f046ccd1SEran Liberty #define OR_GPCM_SCY 0x000000F0 758f046ccd1SEran Liberty #define OR_GPCM_SCY_SHIFT 4 759e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_1 0x00000010 760e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_2 0x00000020 761e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_3 0x00000030 762e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_4 0x00000040 763e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_5 0x00000050 764e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_6 0x00000060 765e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_7 0x00000070 766e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_8 0x00000080 767e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_9 0x00000090 768e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_10 0x000000a0 769e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_11 0x000000b0 770e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_12 0x000000c0 771e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_13 0x000000d0 772e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_14 0x000000e0 773e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_15 0x000000f0 774f046ccd1SEran Liberty #define OR_GPCM_SETA 0x00000008 775f046ccd1SEran Liberty #define OR_GPCM_SETA_SHIFT 3 776f046ccd1SEran Liberty #define OR_GPCM_TRLX 0x00000004 777f046ccd1SEran Liberty #define OR_GPCM_TRLX_SHIFT 2 778f046ccd1SEran Liberty #define OR_GPCM_EHTR 0x00000002 779f046ccd1SEran Liberty #define OR_GPCM_EHTR_SHIFT 1 780f046ccd1SEran Liberty #define OR_GPCM_EAD 0x00000001 781f046ccd1SEran Liberty #define OR_GPCM_EAD_SHIFT 0 782f046ccd1SEran Liberty 783f046ccd1SEran Liberty #define OR_UPM_AM 0xFFFF8000 784f046ccd1SEran Liberty #define OR_UPM_AM_SHIFT 15 785f046ccd1SEran Liberty #define OR_UPM_XAM 0x00006000 786f046ccd1SEran Liberty #define OR_UPM_XAM_SHIFT 13 787f046ccd1SEran Liberty #define OR_UPM_BCTLD 0x00001000 788f046ccd1SEran Liberty #define OR_UPM_BCTLD_SHIFT 12 789f046ccd1SEran Liberty #define OR_UPM_BI 0x00000100 790f046ccd1SEran Liberty #define OR_UPM_BI_SHIFT 8 791f046ccd1SEran Liberty #define OR_UPM_TRLX 0x00000004 792f046ccd1SEran Liberty #define OR_UPM_TRLX_SHIFT 2 793f046ccd1SEran Liberty #define OR_UPM_EHTR 0x00000002 794f046ccd1SEran Liberty #define OR_UPM_EHTR_SHIFT 1 795f046ccd1SEran Liberty #define OR_UPM_EAD 0x00000001 796f046ccd1SEran Liberty #define OR_UPM_EAD_SHIFT 0 797f046ccd1SEran Liberty 798f046ccd1SEran Liberty #define OR_SDRAM_AM 0xFFFF8000 799f046ccd1SEran Liberty #define OR_SDRAM_AM_SHIFT 15 800f046ccd1SEran Liberty #define OR_SDRAM_XAM 0x00006000 801f046ccd1SEran Liberty #define OR_SDRAM_XAM_SHIFT 13 802f046ccd1SEran Liberty #define OR_SDRAM_COLS 0x00001C00 803f046ccd1SEran Liberty #define OR_SDRAM_COLS_SHIFT 10 804f046ccd1SEran Liberty #define OR_SDRAM_ROWS 0x000001C0 805f046ccd1SEran Liberty #define OR_SDRAM_ROWS_SHIFT 6 806f046ccd1SEran Liberty #define OR_SDRAM_PMSEL 0x00000020 807f046ccd1SEran Liberty #define OR_SDRAM_PMSEL_SHIFT 5 808f046ccd1SEran Liberty #define OR_SDRAM_EAD 0x00000001 809f046ccd1SEran Liberty #define OR_SDRAM_EAD_SHIFT 0 810f046ccd1SEran Liberty 811*e080313cSDave Liu /* LBCR - Local Bus Configuration Register 812f046ccd1SEran Liberty */ 813*e080313cSDave Liu #define LBCR_LDIS 0x80000000 814*e080313cSDave Liu #define LBCR_LDIS_SHIFT 31 815*e080313cSDave Liu #define LBCR_BCTLC 0x00C00000 816*e080313cSDave Liu #define LBCR_BCTLC_SHIFT 22 817*e080313cSDave Liu #define LBCR_LPBSE 0x00020000 818*e080313cSDave Liu #define LBCR_LPBSE_SHIFT 17 819*e080313cSDave Liu #define LBCR_EPAR 0x00010000 820*e080313cSDave Liu #define LBCR_EPAR_SHIFT 16 821*e080313cSDave Liu #define LBCR_BMT 0x0000FF00 822*e080313cSDave Liu #define LBCR_BMT_SHIFT 8 823f046ccd1SEran Liberty 824*e080313cSDave Liu /* LCRR - Clock Ratio Register 825f046ccd1SEran Liberty */ 826f046ccd1SEran Liberty #define LCRR_DBYP 0x80000000 827f046ccd1SEran Liberty #define LCRR_DBYP_SHIFT 31 828f046ccd1SEran Liberty #define LCRR_BUFCMDC 0x30000000 829*e080313cSDave Liu #define LCRR_BUFCMDC_SHIFT 28 830f046ccd1SEran Liberty #define LCRR_BUFCMDC_1 0x10000000 831f046ccd1SEran Liberty #define LCRR_BUFCMDC_2 0x20000000 832f046ccd1SEran Liberty #define LCRR_BUFCMDC_3 0x30000000 833f046ccd1SEran Liberty #define LCRR_BUFCMDC_4 0x00000000 834f046ccd1SEran Liberty #define LCRR_ECL 0x03000000 835*e080313cSDave Liu #define LCRR_ECL_SHIFT 24 836f046ccd1SEran Liberty #define LCRR_ECL_4 0x00000000 837f046ccd1SEran Liberty #define LCRR_ECL_5 0x01000000 838f046ccd1SEran Liberty #define LCRR_ECL_6 0x02000000 839f046ccd1SEran Liberty #define LCRR_ECL_7 0x03000000 840f046ccd1SEran Liberty #define LCRR_EADC 0x00030000 841*e080313cSDave Liu #define LCRR_EADC_SHIFT 16 842f046ccd1SEran Liberty #define LCRR_EADC_1 0x00010000 843f046ccd1SEran Liberty #define LCRR_EADC_2 0x00020000 844f046ccd1SEran Liberty #define LCRR_EADC_3 0x00030000 845f046ccd1SEran Liberty #define LCRR_EADC_4 0x00000000 846f046ccd1SEran Liberty #define LCRR_CLKDIV 0x0000000F 847*e080313cSDave Liu #define LCRR_CLKDIV_SHIFT 0 848f046ccd1SEran Liberty #define LCRR_CLKDIV_2 0x00000002 849f046ccd1SEran Liberty #define LCRR_CLKDIV_4 0x00000004 850f046ccd1SEran Liberty #define LCRR_CLKDIV_8 0x00000008 851f046ccd1SEran Liberty 852*e080313cSDave Liu /* DMAMR - DMA Mode Register 853f6eda7f8SDave Liu */ 854*e080313cSDave Liu #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 855*e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 856*e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 857*e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 858*e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 859*e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 860*e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 861*e080313cSDave Liu #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 862f6eda7f8SDave Liu 863*e080313cSDave Liu /* DMASR - DMA Status Register 864*e080313cSDave Liu */ 865*e080313cSDave Liu #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 866*e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 8675f820439SDave Liu 868*e080313cSDave Liu /* CONFIG_ADDRESS - PCI Config Address Register 869*e080313cSDave Liu */ 870*e080313cSDave Liu #define PCI_CONFIG_ADDRESS_EN 0x80000000 871*e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 872*e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 873*e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 874*e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 875*e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 876*e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 877*e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 878*e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 879*e080313cSDave Liu 880*e080313cSDave Liu /* POTAR - PCI Outbound Translation Address Register 881*e080313cSDave Liu */ 882*e080313cSDave Liu #define POTAR_TA_MASK 0x000fffff 883*e080313cSDave Liu 884*e080313cSDave Liu /* POBAR - PCI Outbound Base Address Register 885*e080313cSDave Liu */ 886*e080313cSDave Liu #define POBAR_BA_MASK 0x000fffff 887*e080313cSDave Liu 888*e080313cSDave Liu /* POCMR - PCI Outbound Comparision Mask Register 889*e080313cSDave Liu */ 890*e080313cSDave Liu #define POCMR_EN 0x80000000 891*e080313cSDave Liu #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 892*e080313cSDave Liu #define POCMR_SE 0x20000000 /* streaming enable */ 893*e080313cSDave Liu #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 894*e080313cSDave Liu #define POCMR_CM_MASK 0x000fffff 895*e080313cSDave Liu #define POCMR_CM_4G 0x00000000 896*e080313cSDave Liu #define POCMR_CM_2G 0x00080000 897*e080313cSDave Liu #define POCMR_CM_1G 0x000C0000 898*e080313cSDave Liu #define POCMR_CM_512M 0x000E0000 899*e080313cSDave Liu #define POCMR_CM_256M 0x000F0000 900*e080313cSDave Liu #define POCMR_CM_128M 0x000F8000 901*e080313cSDave Liu #define POCMR_CM_64M 0x000FC000 902*e080313cSDave Liu #define POCMR_CM_32M 0x000FE000 903*e080313cSDave Liu #define POCMR_CM_16M 0x000FF000 904*e080313cSDave Liu #define POCMR_CM_8M 0x000FF800 905*e080313cSDave Liu #define POCMR_CM_4M 0x000FFC00 906*e080313cSDave Liu #define POCMR_CM_2M 0x000FFE00 907*e080313cSDave Liu #define POCMR_CM_1M 0x000FFF00 908*e080313cSDave Liu #define POCMR_CM_512K 0x000FFF80 909*e080313cSDave Liu #define POCMR_CM_256K 0x000FFFC0 910*e080313cSDave Liu #define POCMR_CM_128K 0x000FFFE0 911*e080313cSDave Liu #define POCMR_CM_64K 0x000FFFF0 912*e080313cSDave Liu #define POCMR_CM_32K 0x000FFFF8 913*e080313cSDave Liu #define POCMR_CM_16K 0x000FFFFC 914*e080313cSDave Liu #define POCMR_CM_8K 0x000FFFFE 915*e080313cSDave Liu #define POCMR_CM_4K 0x000FFFFF 916*e080313cSDave Liu 917*e080313cSDave Liu /* PITAR - PCI Inbound Translation Address Register 918*e080313cSDave Liu */ 919*e080313cSDave Liu #define PITAR_TA_MASK 0x000fffff 920*e080313cSDave Liu 921*e080313cSDave Liu /* PIBAR - PCI Inbound Base/Extended Address Register 922*e080313cSDave Liu */ 923*e080313cSDave Liu #define PIBAR_MASK 0xffffffff 924*e080313cSDave Liu #define PIEBAR_EBA_MASK 0x000fffff 925*e080313cSDave Liu 926*e080313cSDave Liu /* PIWAR - PCI Inbound Windows Attributes Register 927*e080313cSDave Liu */ 928*e080313cSDave Liu #define PIWAR_EN 0x80000000 929*e080313cSDave Liu #define PIWAR_PF 0x20000000 930*e080313cSDave Liu #define PIWAR_RTT_MASK 0x000f0000 931*e080313cSDave Liu #define PIWAR_RTT_NO_SNOOP 0x00040000 932*e080313cSDave Liu #define PIWAR_RTT_SNOOP 0x00050000 933*e080313cSDave Liu #define PIWAR_WTT_MASK 0x0000f000 934*e080313cSDave Liu #define PIWAR_WTT_NO_SNOOP 0x00004000 935*e080313cSDave Liu #define PIWAR_WTT_SNOOP 0x00005000 936*e080313cSDave Liu #define PIWAR_IWS_MASK 0x0000003F 937*e080313cSDave Liu #define PIWAR_IWS_4K 0x0000000B 938*e080313cSDave Liu #define PIWAR_IWS_8K 0x0000000C 939*e080313cSDave Liu #define PIWAR_IWS_16K 0x0000000D 940*e080313cSDave Liu #define PIWAR_IWS_32K 0x0000000E 941*e080313cSDave Liu #define PIWAR_IWS_64K 0x0000000F 942*e080313cSDave Liu #define PIWAR_IWS_128K 0x00000010 943*e080313cSDave Liu #define PIWAR_IWS_256K 0x00000011 944*e080313cSDave Liu #define PIWAR_IWS_512K 0x00000012 945*e080313cSDave Liu #define PIWAR_IWS_1M 0x00000013 946*e080313cSDave Liu #define PIWAR_IWS_2M 0x00000014 947*e080313cSDave Liu #define PIWAR_IWS_4M 0x00000015 948*e080313cSDave Liu #define PIWAR_IWS_8M 0x00000016 949*e080313cSDave Liu #define PIWAR_IWS_16M 0x00000017 950*e080313cSDave Liu #define PIWAR_IWS_32M 0x00000018 951*e080313cSDave Liu #define PIWAR_IWS_64M 0x00000019 952*e080313cSDave Liu #define PIWAR_IWS_128M 0x0000001A 953*e080313cSDave Liu #define PIWAR_IWS_256M 0x0000001B 954*e080313cSDave Liu #define PIWAR_IWS_512M 0x0000001C 955*e080313cSDave Liu #define PIWAR_IWS_1G 0x0000001D 956*e080313cSDave Liu #define PIWAR_IWS_2G 0x0000001E 957f6eda7f8SDave Liu 958f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 959