1f046ccd1SEran Liberty /* 203051c3dSDave Liu * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty */ 12f046ccd1SEran Liberty 13f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 14f046ccd1SEran Liberty #define __MPC83XX_H__ 15f046ccd1SEran Liberty 16f6eda7f8SDave Liu #include <config.h> 17f046ccd1SEran Liberty #if defined(CONFIG_E300) 18f046ccd1SEran Liberty #include <asm/e300.h> 19f046ccd1SEran Liberty #endif 20f046ccd1SEran Liberty 21e080313cSDave Liu /* MPC83xx cpu provide RCR register to do reset thing specially 22f046ccd1SEran Liberty */ 23f046ccd1SEran Liberty #define MPC83xx_RESET 24f046ccd1SEran Liberty 25e080313cSDave Liu /* System reset offset (PowerPC standard) 26f046ccd1SEran Liberty */ 27f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 2802032e8fSRafal Jaworowski #define _START_OFFSET EXC_OFF_SYS_RESET 29f046ccd1SEran Liberty 30e080313cSDave Liu /* IMMRBAR - Internal Memory Register Base Address 31f046ccd1SEran Liberty */ 32e080313cSDave Liu #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 33e080313cSDave Liu #define IMMRBAR 0x0000 /* Register offset to immr */ 34e080313cSDave Liu #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 35f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 36f046ccd1SEran Liberty 37e080313cSDave Liu /* LAWBAR - Local Access Window Base Address Register 38f046ccd1SEran Liberty */ 39e080313cSDave Liu #define LBLAWBAR0 0x0020 /* Register offset to immr */ 40f046ccd1SEran Liberty #define LBLAWAR0 0x0024 41f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 42f046ccd1SEran Liberty #define LBLAWAR1 0x002C 43f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 44f046ccd1SEran Liberty #define LBLAWAR2 0x0034 45f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 46f046ccd1SEran Liberty #define LBLAWAR3 0x003C 47e080313cSDave Liu #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 48f046ccd1SEran Liberty 49e080313cSDave Liu /* SPRIDR - System Part and Revision ID Register 50f6eda7f8SDave Liu */ 51e080313cSDave Liu #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ 52e080313cSDave Liu #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ 53e080313cSDave Liu 54f6eda7f8SDave Liu #define SPR_8349E_REV10 0x80300100 555f820439SDave Liu #define SPR_8349_REV10 0x80310100 565f820439SDave Liu #define SPR_8347E_REV10_TBGA 0x80320100 575f820439SDave Liu #define SPR_8347_REV10_TBGA 0x80330100 585f820439SDave Liu #define SPR_8347E_REV10_PBGA 0x80340100 595f820439SDave Liu #define SPR_8347_REV10_PBGA 0x80350100 605f820439SDave Liu #define SPR_8343E_REV10 0x80360100 615f820439SDave Liu #define SPR_8343_REV10 0x80370100 625f820439SDave Liu 63f6eda7f8SDave Liu #define SPR_8349E_REV11 0x80300101 645f820439SDave Liu #define SPR_8349_REV11 0x80310101 655f820439SDave Liu #define SPR_8347E_REV11_TBGA 0x80320101 665f820439SDave Liu #define SPR_8347_REV11_TBGA 0x80330101 675f820439SDave Liu #define SPR_8347E_REV11_PBGA 0x80340101 685f820439SDave Liu #define SPR_8347_REV11_PBGA 0x80350101 695f820439SDave Liu #define SPR_8343E_REV11 0x80360101 705f820439SDave Liu #define SPR_8343_REV11 0x80370101 715f820439SDave Liu 728d172c0fSXie Xiaobo #define SPR_8349E_REV31 0x80300300 738d172c0fSXie Xiaobo #define SPR_8349_REV31 0x80310300 748d172c0fSXie Xiaobo #define SPR_8347E_REV31_TBGA 0x80320300 758d172c0fSXie Xiaobo #define SPR_8347_REV31_TBGA 0x80330300 768d172c0fSXie Xiaobo #define SPR_8347E_REV31_PBGA 0x80340300 778d172c0fSXie Xiaobo #define SPR_8347_REV31_PBGA 0x80350300 788d172c0fSXie Xiaobo #define SPR_8343E_REV31 0x80360300 798d172c0fSXie Xiaobo #define SPR_8343_REV31 0x80370300 808d172c0fSXie Xiaobo 815f820439SDave Liu #define SPR_8360E_REV10 0x80480010 825f820439SDave Liu #define SPR_8360_REV10 0x80490010 835f820439SDave Liu #define SPR_8360E_REV11 0x80480011 845f820439SDave Liu #define SPR_8360_REV11 0x80490011 855f820439SDave Liu #define SPR_8360E_REV12 0x80480012 865f820439SDave Liu #define SPR_8360_REV12 0x80490012 87b110f40bSXie Xiaobo #define SPR_8360E_REV20 0x80480020 88b110f40bSXie Xiaobo #define SPR_8360_REV20 0x80490020 891ded0242SLee Nipper #define SPR_8360E_REV21 0x80480021 901ded0242SLee Nipper #define SPR_8360_REV21 0x80490021 91f046ccd1SEran Liberty 9224c3aca3SDave Liu #define SPR_8323E_REV10 0x80620010 9324c3aca3SDave Liu #define SPR_8323_REV10 0x80630010 9424c3aca3SDave Liu #define SPR_8321E_REV10 0x80660010 9524c3aca3SDave Liu #define SPR_8321_REV10 0x80670010 9624c3aca3SDave Liu #define SPR_8323E_REV11 0x80620011 9724c3aca3SDave Liu #define SPR_8323_REV11 0x80630011 9824c3aca3SDave Liu #define SPR_8321E_REV11 0x80660011 9924c3aca3SDave Liu #define SPR_8321_REV11 0x80670011 10024c3aca3SDave Liu 101d87c57b2SScott Wood #define SPR_8313E_REV10 0x80B00010 10203051c3dSDave Liu #define SPR_8313_REV10 0x80B10010 10303051c3dSDave Liu #define SPR_8311E_REV10 0x80B20010 10403051c3dSDave Liu #define SPR_8311_REV10 0x80B30010 105555da617SDave Liu #define SPR_8315E_REV10 0x80B40010 106555da617SDave Liu #define SPR_8315_REV10 0x80B50010 107555da617SDave Liu #define SPR_8314E_REV10 0x80B60010 108555da617SDave Liu #define SPR_8314_REV10 0x80B70010 10903051c3dSDave Liu 11003051c3dSDave Liu #define SPR_8379E_REV10 0x80C20010 11103051c3dSDave Liu #define SPR_8379_REV10 0x80C30010 11203051c3dSDave Liu #define SPR_8378E_REV10 0x80C40010 11303051c3dSDave Liu #define SPR_8378_REV10 0x80C50010 11403051c3dSDave Liu #define SPR_8377E_REV10 0x80C60010 11503051c3dSDave Liu #define SPR_8377_REV10 0x80C70010 116d87c57b2SScott Wood 117e080313cSDave Liu /* SPCR - System Priority Configuration Register 118f046ccd1SEran Liberty */ 119e080313cSDave Liu #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 120e080313cSDave Liu #define SPCR_PCIHPE_SHIFT (31-3) 121e080313cSDave Liu #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 122e080313cSDave Liu #define SPCR_PCIPR_SHIFT (31-7) 123e080313cSDave Liu #define SPCR_OPT 0x00800000 /* Optimize */ 124e080313cSDave Liu #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 125e080313cSDave Liu #define SPCR_TBEN_SHIFT (31-9) 126e080313cSDave Liu #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 127e080313cSDave Liu #define SPCR_COREPR_SHIFT (31-11) 128e080313cSDave Liu 1293e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 130e080313cSDave Liu /* SPCR bits - MPC8349 specific */ 131e080313cSDave Liu #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 132e080313cSDave Liu #define SPCR_TSEC1DP_SHIFT (31-19) 133e080313cSDave Liu #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 134e080313cSDave Liu #define SPCR_TSEC1BDP_SHIFT (31-21) 135e080313cSDave Liu #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 136e080313cSDave Liu #define SPCR_TSEC1EP_SHIFT (31-23) 137e080313cSDave Liu #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 138e080313cSDave Liu #define SPCR_TSEC2DP_SHIFT (31-27) 139e080313cSDave Liu #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 140e080313cSDave Liu #define SPCR_TSEC2BDP_SHIFT (31-29) 141e080313cSDave Liu #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 142e080313cSDave Liu #define SPCR_TSEC2EP_SHIFT (31-31) 143d87c57b2SScott Wood 14403051c3dSDave Liu #elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 14503051c3dSDave Liu /* SPCR bits - MPC831x and MPC837x specific */ 146d87c57b2SScott Wood #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 147d87c57b2SScott Wood #define SPCR_TSECDP_SHIFT (31-19) 148ec2638eaSDave Liu #define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */ 149ec2638eaSDave Liu #define SPCR_TSECBDP_SHIFT (31-21) 150ec2638eaSDave Liu #define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */ 151ec2638eaSDave Liu #define SPCR_TSECEP_SHIFT (31-23) 152e080313cSDave Liu #endif 153e080313cSDave Liu 154e080313cSDave Liu /* SICRL/H - System I/O Configuration Register Low/High 155e080313cSDave Liu */ 1563e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 157e080313cSDave Liu /* SICRL bits - MPC8349 specific */ 158e080313cSDave Liu #define SICRL_LDP_A 0x80000000 159e080313cSDave Liu #define SICRL_USB1 0x40000000 160e080313cSDave Liu #define SICRL_USB0 0x20000000 161e080313cSDave Liu #define SICRL_UART 0x0C000000 162e080313cSDave Liu #define SICRL_GPIO1_A 0x02000000 163e080313cSDave Liu #define SICRL_GPIO1_B 0x01000000 164e080313cSDave Liu #define SICRL_GPIO1_C 0x00800000 165e080313cSDave Liu #define SICRL_GPIO1_D 0x00400000 166e080313cSDave Liu #define SICRL_GPIO1_E 0x00200000 167e080313cSDave Liu #define SICRL_GPIO1_F 0x00180000 168e080313cSDave Liu #define SICRL_GPIO1_G 0x00040000 169e080313cSDave Liu #define SICRL_GPIO1_H 0x00020000 170e080313cSDave Liu #define SICRL_GPIO1_I 0x00010000 171e080313cSDave Liu #define SICRL_GPIO1_J 0x00008000 172e080313cSDave Liu #define SICRL_GPIO1_K 0x00004000 173e080313cSDave Liu #define SICRL_GPIO1_L 0x00003000 174e080313cSDave Liu 175e080313cSDave Liu /* SICRH bits - MPC8349 specific */ 176e080313cSDave Liu #define SICRH_DDR 0x80000000 177e080313cSDave Liu #define SICRH_TSEC1_A 0x10000000 178e080313cSDave Liu #define SICRH_TSEC1_B 0x08000000 179e080313cSDave Liu #define SICRH_TSEC1_C 0x04000000 180e080313cSDave Liu #define SICRH_TSEC1_D 0x02000000 181e080313cSDave Liu #define SICRH_TSEC1_E 0x01000000 182e080313cSDave Liu #define SICRH_TSEC1_F 0x00800000 183e080313cSDave Liu #define SICRH_TSEC2_A 0x00400000 184e080313cSDave Liu #define SICRH_TSEC2_B 0x00200000 185e080313cSDave Liu #define SICRH_TSEC2_C 0x00100000 186e080313cSDave Liu #define SICRH_TSEC2_D 0x00080000 187e080313cSDave Liu #define SICRH_TSEC2_E 0x00040000 188e080313cSDave Liu #define SICRH_TSEC2_F 0x00020000 189e080313cSDave Liu #define SICRH_TSEC2_G 0x00010000 190e080313cSDave Liu #define SICRH_TSEC2_H 0x00008000 191e080313cSDave Liu #define SICRH_GPIO2_A 0x00004000 192e080313cSDave Liu #define SICRH_GPIO2_B 0x00002000 193e080313cSDave Liu #define SICRH_GPIO2_C 0x00001000 194e080313cSDave Liu #define SICRH_GPIO2_D 0x00000800 195e080313cSDave Liu #define SICRH_GPIO2_E 0x00000400 196e080313cSDave Liu #define SICRH_GPIO2_F 0x00000200 197e080313cSDave Liu #define SICRH_GPIO2_G 0x00000180 198e080313cSDave Liu #define SICRH_GPIO2_H 0x00000060 199e080313cSDave Liu #define SICRH_TSOBI1 0x00000002 200e080313cSDave Liu #define SICRH_TSOBI2 0x00000001 201e080313cSDave Liu 202e080313cSDave Liu #elif defined(CONFIG_MPC8360) 203e080313cSDave Liu /* SICRL bits - MPC8360 specific */ 204e080313cSDave Liu #define SICRL_LDP_A 0xC0000000 205e080313cSDave Liu #define SICRL_LCLK_1 0x10000000 206e080313cSDave Liu #define SICRL_LCLK_2 0x08000000 207e080313cSDave Liu #define SICRL_SRCID_A 0x03000000 208e080313cSDave Liu #define SICRL_IRQ_CKSTP_A 0x00C00000 209e080313cSDave Liu 210e080313cSDave Liu /* SICRH bits - MPC8360 specific */ 211e080313cSDave Liu #define SICRH_DDR 0x80000000 212e080313cSDave Liu #define SICRH_SECONDARY_DDR 0x40000000 213e080313cSDave Liu #define SICRH_SDDROE 0x20000000 214e080313cSDave Liu #define SICRH_IRQ3 0x10000000 215e080313cSDave Liu #define SICRH_UC1EOBI 0x00000004 216e080313cSDave Liu #define SICRH_UC2E1OBI 0x00000002 217e080313cSDave Liu #define SICRH_UC2E2OBI 0x00000001 21824c3aca3SDave Liu 21924c3aca3SDave Liu #elif defined(CONFIG_MPC832X) 22024c3aca3SDave Liu /* SICRL bits - MPC832X specific */ 22124c3aca3SDave Liu #define SICRL_LDP_LCS_A 0x80000000 22224c3aca3SDave Liu #define SICRL_IRQ_CKS 0x20000000 22324c3aca3SDave Liu #define SICRL_PCI_MSRC 0x10000000 22424c3aca3SDave Liu #define SICRL_URT_CTPR 0x06000000 22524c3aca3SDave Liu #define SICRL_IRQ_CTPR 0x00C00000 226d87c57b2SScott Wood 227555da617SDave Liu #elif defined(CONFIG_MPC8313) 228555da617SDave Liu /* SICRL bits - MPC8313 specific */ 229d87c57b2SScott Wood #define SICRL_LBC 0x30000000 230d87c57b2SScott Wood #define SICRL_UART 0x0C000000 231d87c57b2SScott Wood #define SICRL_SPI_A 0x03000000 232d87c57b2SScott Wood #define SICRL_SPI_B 0x00C00000 233d87c57b2SScott Wood #define SICRL_SPI_C 0x00300000 234d87c57b2SScott Wood #define SICRL_SPI_D 0x000C0000 235d87c57b2SScott Wood #define SICRL_USBDR 0x00000C00 236d87c57b2SScott Wood #define SICRL_ETSEC1_A 0x0000000C 237d87c57b2SScott Wood #define SICRL_ETSEC2_A 0x00000003 238d87c57b2SScott Wood 239555da617SDave Liu /* SICRH bits - MPC8313 specific */ 240d87c57b2SScott Wood #define SICRH_INTR_A 0x02000000 241d87c57b2SScott Wood #define SICRH_INTR_B 0x00C00000 242d87c57b2SScott Wood #define SICRH_IIC 0x00300000 243d87c57b2SScott Wood #define SICRH_ETSEC2_B 0x000C0000 244d87c57b2SScott Wood #define SICRH_ETSEC2_C 0x00030000 245d87c57b2SScott Wood #define SICRH_ETSEC2_D 0x0000C000 246d87c57b2SScott Wood #define SICRH_ETSEC2_E 0x00003000 247d87c57b2SScott Wood #define SICRH_ETSEC2_F 0x00000C00 248d87c57b2SScott Wood #define SICRH_ETSEC2_G 0x00000300 249d87c57b2SScott Wood #define SICRH_ETSEC1_B 0x00000080 250d87c57b2SScott Wood #define SICRH_ETSEC1_C 0x00000060 251d87c57b2SScott Wood #define SICRH_GTX1_DLY 0x00000008 252d87c57b2SScott Wood #define SICRH_GTX2_DLY 0x00000004 253d87c57b2SScott Wood #define SICRH_TSOBI1 0x00000002 254d87c57b2SScott Wood #define SICRH_TSOBI2 0x00000001 255d87c57b2SScott Wood 256555da617SDave Liu #elif defined(CONFIG_MPC8315) 257555da617SDave Liu /* SICRL bits - MPC8315 specific */ 258555da617SDave Liu #define SICRL_DMA_CH0 0xc0000000 259555da617SDave Liu #define SICRL_DMA_SPI 0x30000000 260555da617SDave Liu #define SICRL_UART 0x0c000000 261555da617SDave Liu #define SICRL_IRQ4 0x02000000 262555da617SDave Liu #define SICRL_IRQ5 0x01800000 263555da617SDave Liu #define SICRL_IRQ6_7 0x00400000 264555da617SDave Liu #define SICRL_IIC1 0x00300000 265555da617SDave Liu #define SICRL_TDM 0x000c0000 266555da617SDave Liu #define SICRL_TDM_SHARED 0x00030000 267555da617SDave Liu #define SICRL_PCI_A 0x0000c000 268555da617SDave Liu #define SICRL_ELBC_A 0x00003000 269555da617SDave Liu #define SICRL_ETSEC1_A 0x000000c0 270555da617SDave Liu #define SICRL_ETSEC1_B 0x00000030 271555da617SDave Liu #define SICRL_ETSEC1_C 0x0000000c 272555da617SDave Liu #define SICRL_TSEXPOBI 0x00000001 273555da617SDave Liu 274555da617SDave Liu /* SICRH bits - MPC8315 specific */ 275555da617SDave Liu #define SICRH_GPIO_0 0xc0000000 276555da617SDave Liu #define SICRH_GPIO_1 0x30000000 277555da617SDave Liu #define SICRH_GPIO_2 0x0c000000 278555da617SDave Liu #define SICRH_GPIO_3 0x03000000 279555da617SDave Liu #define SICRH_GPIO_4 0x00c00000 280555da617SDave Liu #define SICRH_GPIO_5 0x00300000 281555da617SDave Liu #define SICRH_GPIO_6 0x000c0000 282555da617SDave Liu #define SICRH_GPIO_7 0x00030000 283555da617SDave Liu #define SICRH_GPIO_8 0x0000c000 284555da617SDave Liu #define SICRH_GPIO_9 0x00003000 285555da617SDave Liu #define SICRH_GPIO_10 0x00000c00 286555da617SDave Liu #define SICRH_GPIO_11 0x00000300 287555da617SDave Liu #define SICRH_ETSEC2_A 0x000000c0 288555da617SDave Liu #define SICRH_TSOBI1 0x00000002 289555da617SDave Liu #define SICRH_TSOBI2 0x00000001 290555da617SDave Liu 29103051c3dSDave Liu #elif defined(CONFIG_MPC837X) 29203051c3dSDave Liu /* SICRL bits - MPC837x specific */ 29303051c3dSDave Liu #define SICRL_USB_A 0xC0000000 29403051c3dSDave Liu #define SICRL_USB_B 0x30000000 29503051c3dSDave Liu #define SICRL_UART 0x0C000000 29603051c3dSDave Liu #define SICRL_GPIO_A 0x02000000 29703051c3dSDave Liu #define SICRL_GPIO_B 0x01000000 29803051c3dSDave Liu #define SICRL_GPIO_C 0x00800000 29903051c3dSDave Liu #define SICRL_GPIO_D 0x00400000 30003051c3dSDave Liu #define SICRL_GPIO_E 0x00200000 30103051c3dSDave Liu #define SICRL_GPIO_F 0x00180000 30203051c3dSDave Liu #define SICRL_GPIO_G 0x00040000 30303051c3dSDave Liu #define SICRL_GPIO_H 0x00020000 30403051c3dSDave Liu #define SICRL_GPIO_I 0x00010000 30503051c3dSDave Liu #define SICRL_GPIO_J 0x00008000 30603051c3dSDave Liu #define SICRL_GPIO_K 0x00004000 30703051c3dSDave Liu #define SICRL_GPIO_L 0x00003000 30803051c3dSDave Liu #define SICRL_DMA_A 0x00000800 30903051c3dSDave Liu #define SICRL_DMA_B 0x00000400 31003051c3dSDave Liu #define SICRL_DMA_C 0x00000200 31103051c3dSDave Liu #define SICRL_DMA_D 0x00000100 31203051c3dSDave Liu #define SICRL_DMA_E 0x00000080 31303051c3dSDave Liu #define SICRL_DMA_F 0x00000040 31403051c3dSDave Liu #define SICRL_DMA_G 0x00000020 31503051c3dSDave Liu #define SICRL_DMA_H 0x00000010 31603051c3dSDave Liu #define SICRL_DMA_I 0x00000008 31703051c3dSDave Liu #define SICRL_DMA_J 0x00000004 31803051c3dSDave Liu #define SICRL_LDP_A 0x00000002 31903051c3dSDave Liu #define SICRL_LDP_B 0x00000001 32003051c3dSDave Liu 32103051c3dSDave Liu /* SICRH bits - MPC837x specific */ 32203051c3dSDave Liu #define SICRH_DDR 0x80000000 32303051c3dSDave Liu #define SICRH_TSEC1_A 0x10000000 32403051c3dSDave Liu #define SICRH_TSEC1_B 0x08000000 32503051c3dSDave Liu #define SICRH_TSEC2_A 0x00400000 32603051c3dSDave Liu #define SICRH_TSEC2_B 0x00200000 32703051c3dSDave Liu #define SICRH_TSEC2_C 0x00100000 32803051c3dSDave Liu #define SICRH_TSEC2_D 0x00080000 32903051c3dSDave Liu #define SICRH_TSEC2_E 0x00040000 33003051c3dSDave Liu #define SICRH_TMR 0x00010000 33103051c3dSDave Liu #define SICRH_GPIO2_A 0x00008000 33203051c3dSDave Liu #define SICRH_GPIO2_B 0x00004000 33303051c3dSDave Liu #define SICRH_GPIO2_C 0x00002000 33403051c3dSDave Liu #define SICRH_GPIO2_D 0x00001000 33503051c3dSDave Liu #define SICRH_GPIO2_E 0x00000C00 33603051c3dSDave Liu #define SICRH_GPIO2_F 0x00000300 33703051c3dSDave Liu #define SICRH_GPIO2_G 0x000000C0 33803051c3dSDave Liu #define SICRH_GPIO2_H 0x00000030 33903051c3dSDave Liu #define SICRH_SPI 0x00000003 340e080313cSDave Liu #endif 341e080313cSDave Liu 342e080313cSDave Liu /* SWCRR - System Watchdog Control Register 343e080313cSDave Liu */ 344e080313cSDave Liu #define SWCRR 0x0204 /* Register offset to immr */ 345e080313cSDave Liu #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 346e080313cSDave Liu #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 347e080313cSDave Liu #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 348e080313cSDave Liu #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 349e080313cSDave Liu #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 350e080313cSDave Liu 351e080313cSDave Liu /* SWCNR - System Watchdog Counter Register 352e080313cSDave Liu */ 353e080313cSDave Liu #define SWCNR 0x0208 /* Register offset to immr */ 354e080313cSDave Liu #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 355e080313cSDave Liu #define SWCNR_RES ~(SWCNR_SWCN) 356e080313cSDave Liu 357e080313cSDave Liu /* SWSRR - System Watchdog Service Register 358e080313cSDave Liu */ 359e080313cSDave Liu #define SWSRR 0x020E /* Register offset to immr */ 360e080313cSDave Liu 361e080313cSDave Liu /* ACR - Arbiter Configuration Register 362e080313cSDave Liu */ 363e080313cSDave Liu #define ACR_COREDIS 0x10000000 /* Core disable */ 364e080313cSDave Liu #define ACR_COREDIS_SHIFT (31-7) 365e080313cSDave Liu #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 366e080313cSDave Liu #define ACR_PIPE_DEP_SHIFT (31-15) 367e080313cSDave Liu #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 368e080313cSDave Liu #define ACR_PCI_RPTCNT_SHIFT (31-19) 369e080313cSDave Liu #define ACR_RPTCNT 0x00000700 /* Repeat count */ 370e080313cSDave Liu #define ACR_RPTCNT_SHIFT (31-23) 371e080313cSDave Liu #define ACR_APARK 0x00000030 /* Address parking */ 372e080313cSDave Liu #define ACR_APARK_SHIFT (31-27) 373e080313cSDave Liu #define ACR_PARKM 0x0000000F /* Parking master */ 374e080313cSDave Liu #define ACR_PARKM_SHIFT (31-31) 375e080313cSDave Liu 376e080313cSDave Liu /* ATR - Arbiter Timers Register 377e080313cSDave Liu */ 378e080313cSDave Liu #define ATR_DTO 0x00FF0000 /* Data time out */ 379e080313cSDave Liu #define ATR_ATO 0x000000FF /* Address time out */ 380e080313cSDave Liu 381e080313cSDave Liu /* AER - Arbiter Event Register 382e080313cSDave Liu */ 383e080313cSDave Liu #define AER_ETEA 0x00000020 /* Transfer error */ 384e080313cSDave Liu #define AER_RES 0x00000010 /* Reserved transfer type */ 385e080313cSDave Liu #define AER_ECW 0x00000008 /* External control word transfer type */ 386e080313cSDave Liu #define AER_AO 0x00000004 /* Address Only transfer type */ 387e080313cSDave Liu #define AER_DTO 0x00000002 /* Data time out */ 388e080313cSDave Liu #define AER_ATO 0x00000001 /* Address time out */ 389e080313cSDave Liu 390e080313cSDave Liu /* AEATR - Arbiter Event Address Register 391e080313cSDave Liu */ 392e080313cSDave Liu #define AEATR_EVENT 0x07000000 /* Event type */ 393e080313cSDave Liu #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 394e080313cSDave Liu #define AEATR_TBST 0x00000800 /* Transfer burst */ 395e080313cSDave Liu #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 396e080313cSDave Liu #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 397e080313cSDave Liu 398e080313cSDave Liu /* HRCWL - Hard Reset Configuration Word Low 399e080313cSDave Liu */ 400e080313cSDave Liu #define HRCWL_LBIUCM 0x80000000 401e080313cSDave Liu #define HRCWL_LBIUCM_SHIFT 31 402e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 403e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 404e080313cSDave Liu 405e080313cSDave Liu #define HRCWL_DDRCM 0x40000000 406e080313cSDave Liu #define HRCWL_DDRCM_SHIFT 30 407e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 408e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 409e080313cSDave Liu 410e080313cSDave Liu #define HRCWL_SPMF 0x0f000000 411e080313cSDave Liu #define HRCWL_SPMF_SHIFT 24 412e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 413e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 414e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 415e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 416e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 417e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 418e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 419e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 420e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 421e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 422e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 423e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 424e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 425e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 426e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 427e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 428e080313cSDave Liu 429e080313cSDave Liu #define HRCWL_VCO_BYPASS 0x00000000 430e080313cSDave Liu #define HRCWL_VCO_1X2 0x00000000 431e080313cSDave Liu #define HRCWL_VCO_1X4 0x00200000 432e080313cSDave Liu #define HRCWL_VCO_1X8 0x00400000 433e080313cSDave Liu 434e080313cSDave Liu #define HRCWL_COREPLL 0x007F0000 435e080313cSDave Liu #define HRCWL_COREPLL_SHIFT 16 436e080313cSDave Liu #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 437e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1X1 0x00020000 438e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 439e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2X1 0x00040000 440e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 441e080313cSDave Liu #define HRCWL_CORE_TO_CSB_3X1 0x00060000 442e080313cSDave Liu 44324c3aca3SDave Liu #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 444e080313cSDave Liu #define HRCWL_CEVCOD 0x000000C0 445e080313cSDave Liu #define HRCWL_CEVCOD_SHIFT 6 446e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 447e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 448e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 449e080313cSDave Liu 450e080313cSDave Liu #define HRCWL_CEPDF 0x00000020 451e080313cSDave Liu #define HRCWL_CEPDF_SHIFT 5 452e080313cSDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 453e080313cSDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 454e080313cSDave Liu 455e080313cSDave Liu #define HRCWL_CEPMF 0x0000001F 456e080313cSDave Liu #define HRCWL_CEPMF_SHIFT 0 457e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 458e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 459e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 460e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 461e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 462e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 463e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 464e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 465e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 466e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 467e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 468e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 469e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 470e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 471e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 472e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 473e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 474e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 475e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 476e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 477e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 478e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 479e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 480e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 481e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 482e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 483e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 484e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 485e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 486e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 487e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 48803051c3dSDave Liu 4896f3931a2SDave Liu #elif defined(CONFIG_MPC8315) 4906f3931a2SDave Liu #define HRCWL_SVCOD 0x30000000 4916f3931a2SDave Liu #define HRCWL_SVCOD_SHIFT 28 4926f3931a2SDave Liu #define HRCWL_SVCOD_DIV_2 0x00000000 4936f3931a2SDave Liu #define HRCWL_SVCOD_DIV_4 0x10000000 4946f3931a2SDave Liu #define HRCWL_SVCOD_DIV_8 0x20000000 4956f3931a2SDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 4966f3931a2SDave Liu 4976f3931a2SDave Liu #elif defined(CONFIG_MPC837X) 49803051c3dSDave Liu #define HRCWL_SVCOD 0x30000000 49903051c3dSDave Liu #define HRCWL_SVCOD_SHIFT 28 50003051c3dSDave Liu #define HRCWL_SVCOD_DIV_4 0x00000000 50103051c3dSDave Liu #define HRCWL_SVCOD_DIV_8 0x10000000 50203051c3dSDave Liu #define HRCWL_SVCOD_DIV_2 0x20000000 50303051c3dSDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 504e080313cSDave Liu #endif 505e080313cSDave Liu 506e080313cSDave Liu /* HRCWH - Hardware Reset Configuration Word High 507e080313cSDave Liu */ 508e080313cSDave Liu #define HRCWH_PCI_HOST 0x80000000 509e080313cSDave Liu #define HRCWH_PCI_HOST_SHIFT 31 510e080313cSDave Liu #define HRCWH_PCI_AGENT 0x00000000 511e080313cSDave Liu 5123e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 513e080313cSDave Liu #define HRCWH_32_BIT_PCI 0x00000000 514e080313cSDave Liu #define HRCWH_64_BIT_PCI 0x40000000 515e080313cSDave Liu #endif 516e080313cSDave Liu 517e080313cSDave Liu #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 518e080313cSDave Liu #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 519e080313cSDave Liu 520e080313cSDave Liu #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 521e080313cSDave Liu #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 522e080313cSDave Liu 5233e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 524e080313cSDave Liu #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 525e080313cSDave Liu #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 526e080313cSDave Liu 527e080313cSDave Liu #elif defined(CONFIG_MPC8360) 528e080313cSDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 529e080313cSDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 530e080313cSDave Liu #endif 531e080313cSDave Liu 532e080313cSDave Liu #define HRCWH_CORE_DISABLE 0x08000000 533e080313cSDave Liu #define HRCWH_CORE_ENABLE 0x00000000 534e080313cSDave Liu 535e080313cSDave Liu #define HRCWH_FROM_0X00000100 0x00000000 536e080313cSDave Liu #define HRCWH_FROM_0XFFF00100 0x04000000 537e080313cSDave Liu 538e080313cSDave Liu #define HRCWH_BOOTSEQ_DISABLE 0x00000000 539e080313cSDave Liu #define HRCWH_BOOTSEQ_NORMAL 0x01000000 540e080313cSDave Liu #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 541e080313cSDave Liu 542e080313cSDave Liu #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 543e080313cSDave Liu #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 544e080313cSDave Liu 545e080313cSDave Liu #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 546e080313cSDave Liu #define HRCWH_ROM_LOC_PCI1 0x00100000 5473e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 548e080313cSDave Liu #define HRCWH_ROM_LOC_PCI2 0x00200000 549e080313cSDave Liu #endif 55003051c3dSDave Liu #if defined(CONIFG_MPC837X) 55103051c3dSDave Liu #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 55203051c3dSDave Liu #endif 553e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 554e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 555e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 556e080313cSDave Liu 55703051c3dSDave Liu #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 558d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 559d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 560d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 561d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 562d87c57b2SScott Wood 563d87c57b2SScott Wood #define HRCWH_RL_EXT_LEGACY 0x00000000 564d87c57b2SScott Wood #define HRCWH_RL_EXT_NAND 0x00040000 565d87c57b2SScott Wood 566d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_MII 0x00000000 567d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RMII 0x00002000 568d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RGMII 0x00006000 569d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 570d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 571d87c57b2SScott Wood 572d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_MII 0x00000000 573d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RMII 0x00000400 574d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 575d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RTBI 0x00001400 576d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_SGMII 0x00001800 577d87c57b2SScott Wood #endif 578d87c57b2SScott Wood 5793e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 580e080313cSDave Liu #define HRCWH_TSEC1M_IN_RGMII 0x00000000 581e080313cSDave Liu #define HRCWH_TSEC1M_IN_RTBI 0x00004000 582e080313cSDave Liu #define HRCWH_TSEC1M_IN_GMII 0x00008000 583e080313cSDave Liu #define HRCWH_TSEC1M_IN_TBI 0x0000C000 584e080313cSDave Liu #define HRCWH_TSEC2M_IN_RGMII 0x00000000 585e080313cSDave Liu #define HRCWH_TSEC2M_IN_RTBI 0x00001000 586e080313cSDave Liu #define HRCWH_TSEC2M_IN_GMII 0x00002000 587e080313cSDave Liu #define HRCWH_TSEC2M_IN_TBI 0x00003000 588e080313cSDave Liu #endif 589e080313cSDave Liu 590e080313cSDave Liu #if defined(CONFIG_MPC8360) 591e080313cSDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 592e080313cSDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 593e080313cSDave Liu #endif 594e080313cSDave Liu 595e080313cSDave Liu #define HRCWH_BIG_ENDIAN 0x00000000 596e080313cSDave Liu #define HRCWH_LITTLE_ENDIAN 0x00000008 597e080313cSDave Liu 598e080313cSDave Liu #define HRCWH_LALE_NORMAL 0x00000000 599e080313cSDave Liu #define HRCWH_LALE_EARLY 0x00000004 600e080313cSDave Liu 601e080313cSDave Liu #define HRCWH_LDP_SET 0x00000000 602e080313cSDave Liu #define HRCWH_LDP_CLEAR 0x00000002 603e080313cSDave Liu 604e080313cSDave Liu /* RSR - Reset Status Register 605e080313cSDave Liu */ 606555da617SDave Liu #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 60703051c3dSDave Liu #define RSR_RSTSRC 0xF0000000 /* Reset source */ 60803051c3dSDave Liu #define RSR_RSTSRC_SHIFT 28 60903051c3dSDave Liu #else 610e080313cSDave Liu #define RSR_RSTSRC 0xE0000000 /* Reset source */ 611e080313cSDave Liu #define RSR_RSTSRC_SHIFT 29 61203051c3dSDave Liu #endif 613e080313cSDave Liu #define RSR_BSF 0x00010000 /* Boot seq. fail */ 614e080313cSDave Liu #define RSR_BSF_SHIFT 16 615e080313cSDave Liu #define RSR_SWSR 0x00002000 /* software soft reset */ 616e080313cSDave Liu #define RSR_SWSR_SHIFT 13 617e080313cSDave Liu #define RSR_SWHR 0x00001000 /* software hard reset */ 618e080313cSDave Liu #define RSR_SWHR_SHIFT 12 619e080313cSDave Liu #define RSR_JHRS 0x00000200 /* jtag hreset */ 620e080313cSDave Liu #define RSR_JHRS_SHIFT 9 621e080313cSDave Liu #define RSR_JSRS 0x00000100 /* jtag sreset status */ 622e080313cSDave Liu #define RSR_JSRS_SHIFT 8 623e080313cSDave Liu #define RSR_CSHR 0x00000010 /* checkstop reset status */ 624e080313cSDave Liu #define RSR_CSHR_SHIFT 4 625e080313cSDave Liu #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 626e080313cSDave Liu #define RSR_SWRS_SHIFT 3 627e080313cSDave Liu #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 628e080313cSDave Liu #define RSR_BMRS_SHIFT 2 629e080313cSDave Liu #define RSR_SRS 0x00000002 /* soft reset status */ 630e080313cSDave Liu #define RSR_SRS_SHIFT 1 631e080313cSDave Liu #define RSR_HRS 0x00000001 /* hard reset status */ 632e080313cSDave Liu #define RSR_HRS_SHIFT 0 633e080313cSDave Liu #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 634e080313cSDave Liu RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 635e080313cSDave Liu RSR_BMRS | RSR_SRS | RSR_HRS) 636e080313cSDave Liu /* RMR - Reset Mode Register 637e080313cSDave Liu */ 638e080313cSDave Liu #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 639e080313cSDave Liu #define RMR_CSRE_SHIFT 0 640e080313cSDave Liu #define RMR_RES ~(RMR_CSRE) 641e080313cSDave Liu 642e080313cSDave Liu /* RCR - Reset Control Register 643e080313cSDave Liu */ 644e080313cSDave Liu #define RCR_SWHR 0x00000002 /* software hard reset */ 645e080313cSDave Liu #define RCR_SWSR 0x00000001 /* software soft reset */ 646e080313cSDave Liu #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 647e080313cSDave Liu 648e080313cSDave Liu /* RCER - Reset Control Enable Register 649e080313cSDave Liu */ 650e080313cSDave Liu #define RCER_CRE 0x00000001 /* software hard reset */ 651e080313cSDave Liu #define RCER_RES ~(RCER_CRE) 652e080313cSDave Liu 653e080313cSDave Liu /* SPMR - System PLL Mode Register 654e080313cSDave Liu */ 655e080313cSDave Liu #define SPMR_LBIUCM 0x80000000 656e080313cSDave Liu #define SPMR_DDRCM 0x40000000 657e080313cSDave Liu #define SPMR_SPMF 0x0F000000 658e080313cSDave Liu #define SPMR_CKID 0x00800000 659e080313cSDave Liu #define SPMR_CKID_SHIFT 23 660e080313cSDave Liu #define SPMR_COREPLL 0x007F0000 661e080313cSDave Liu #define SPMR_CEVCOD 0x000000C0 662e080313cSDave Liu #define SPMR_CEPDF 0x00000020 663e080313cSDave Liu #define SPMR_CEPMF 0x0000001F 664e080313cSDave Liu 665e080313cSDave Liu /* OCCR - Output Clock Control Register 666e080313cSDave Liu */ 667e080313cSDave Liu #define OCCR_PCICOE0 0x80000000 668e080313cSDave Liu #define OCCR_PCICOE1 0x40000000 669e080313cSDave Liu #define OCCR_PCICOE2 0x20000000 670e080313cSDave Liu #define OCCR_PCICOE3 0x10000000 671e080313cSDave Liu #define OCCR_PCICOE4 0x08000000 672e080313cSDave Liu #define OCCR_PCICOE5 0x04000000 673e080313cSDave Liu #define OCCR_PCICOE6 0x02000000 674e080313cSDave Liu #define OCCR_PCICOE7 0x01000000 675e080313cSDave Liu #define OCCR_PCICD0 0x00800000 676e080313cSDave Liu #define OCCR_PCICD1 0x00400000 677e080313cSDave Liu #define OCCR_PCICD2 0x00200000 678e080313cSDave Liu #define OCCR_PCICD3 0x00100000 679e080313cSDave Liu #define OCCR_PCICD4 0x00080000 680e080313cSDave Liu #define OCCR_PCICD5 0x00040000 681e080313cSDave Liu #define OCCR_PCICD6 0x00020000 682e080313cSDave Liu #define OCCR_PCICD7 0x00010000 683e080313cSDave Liu #define OCCR_PCI1CR 0x00000002 684e080313cSDave Liu #define OCCR_PCI2CR 0x00000001 685e080313cSDave Liu #define OCCR_PCICR OCCR_PCI1CR 686e080313cSDave Liu 687e080313cSDave Liu /* SCCR - System Clock Control Register 688e080313cSDave Liu */ 689e080313cSDave Liu #define SCCR_ENCCM 0x03000000 690e080313cSDave Liu #define SCCR_ENCCM_SHIFT 24 691e080313cSDave Liu #define SCCR_ENCCM_0 0x00000000 692e080313cSDave Liu #define SCCR_ENCCM_1 0x01000000 693e080313cSDave Liu #define SCCR_ENCCM_2 0x02000000 694e080313cSDave Liu #define SCCR_ENCCM_3 0x03000000 695e080313cSDave Liu 696e080313cSDave Liu #define SCCR_PCICM 0x00010000 697e080313cSDave Liu #define SCCR_PCICM_SHIFT 16 698e080313cSDave Liu 69903051c3dSDave Liu #if defined(CONFIG_MPC834X) 70003051c3dSDave Liu /* SCCR bits - MPC834x specific */ 701e080313cSDave Liu #define SCCR_TSEC1CM 0xc0000000 702e080313cSDave Liu #define SCCR_TSEC1CM_SHIFT 30 703e080313cSDave Liu #define SCCR_TSEC1CM_0 0x00000000 704e080313cSDave Liu #define SCCR_TSEC1CM_1 0x40000000 705e080313cSDave Liu #define SCCR_TSEC1CM_2 0x80000000 706e080313cSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 707e080313cSDave Liu 708e080313cSDave Liu #define SCCR_TSEC2CM 0x30000000 709e080313cSDave Liu #define SCCR_TSEC2CM_SHIFT 28 710e080313cSDave Liu #define SCCR_TSEC2CM_0 0x00000000 711e080313cSDave Liu #define SCCR_TSEC2CM_1 0x10000000 712e080313cSDave Liu #define SCCR_TSEC2CM_2 0x20000000 713e080313cSDave Liu #define SCCR_TSEC2CM_3 0x30000000 714d87c57b2SScott Wood 71503051c3dSDave Liu /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 71603051c3dSDave Liu #define SCCR_USBMPHCM 0x00c00000 71703051c3dSDave Liu #define SCCR_USBMPHCM_SHIFT 22 71803051c3dSDave Liu #define SCCR_USBDRCM 0x00300000 71903051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 20 72003051c3dSDave Liu #define SCCR_USBCM 0x00f00000 72103051c3dSDave Liu #define SCCR_USBCM_SHIFT 20 72203051c3dSDave Liu #define SCCR_USBCM_0 0x00000000 72303051c3dSDave Liu #define SCCR_USBCM_1 0x00500000 72403051c3dSDave Liu #define SCCR_USBCM_2 0x00A00000 72503051c3dSDave Liu #define SCCR_USBCM_3 0x00F00000 72603051c3dSDave Liu 727555da617SDave Liu #elif defined(CONFIG_MPC8313) 728*a8cb43a8SDave Liu /* TSEC1 bits are for TSEC2 as well */ 729d87c57b2SScott Wood #define SCCR_TSEC1CM 0xc0000000 730d87c57b2SScott Wood #define SCCR_TSEC1CM_SHIFT 30 7319e896478SKim Phillips #define SCCR_TSEC1CM_0 0x00000000 732d87c57b2SScott Wood #define SCCR_TSEC1CM_1 0x40000000 733d87c57b2SScott Wood #define SCCR_TSEC1CM_2 0x80000000 734d87c57b2SScott Wood #define SCCR_TSEC1CM_3 0xC0000000 735d87c57b2SScott Wood 736d87c57b2SScott Wood #define SCCR_TSEC1ON 0x20000000 737df33f6b4STimur Tabi #define SCCR_TSEC1ON_SHIFT 29 738d87c57b2SScott Wood #define SCCR_TSEC2ON 0x10000000 739df33f6b4STimur Tabi #define SCCR_TSEC2ON_SHIFT 28 740d87c57b2SScott Wood 741e080313cSDave Liu #define SCCR_USBDRCM 0x00300000 742e080313cSDave Liu #define SCCR_USBDRCM_SHIFT 20 74303051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 74403051c3dSDave Liu #define SCCR_USBDRCM_1 0x00100000 74503051c3dSDave Liu #define SCCR_USBDRCM_2 0x00200000 74603051c3dSDave Liu #define SCCR_USBDRCM_3 0x00300000 747e080313cSDave Liu 748555da617SDave Liu #elif defined(CONFIG_MPC8315) 749555da617SDave Liu /* SCCR bits - MPC8315 specific */ 750555da617SDave Liu #define SCCR_TSEC1CM 0xc0000000 751555da617SDave Liu #define SCCR_TSEC1CM_SHIFT 30 752555da617SDave Liu #define SCCR_TSEC1CM_0 0x00000000 753555da617SDave Liu #define SCCR_TSEC1CM_1 0x40000000 754555da617SDave Liu #define SCCR_TSEC1CM_2 0x80000000 755555da617SDave Liu #define SCCR_TSEC1CM_3 0xC0000000 756555da617SDave Liu 757555da617SDave Liu #define SCCR_TSEC2CM 0x30000000 758555da617SDave Liu #define SCCR_TSEC2CM_SHIFT 28 759555da617SDave Liu #define SCCR_TSEC2CM_0 0x00000000 760555da617SDave Liu #define SCCR_TSEC2CM_1 0x10000000 761555da617SDave Liu #define SCCR_TSEC2CM_2 0x20000000 762555da617SDave Liu #define SCCR_TSEC2CM_3 0x30000000 763555da617SDave Liu 7646f3931a2SDave Liu #define SCCR_USBDRCM 0x00c00000 7656f3931a2SDave Liu #define SCCR_USBDRCM_SHIFT 22 766555da617SDave Liu #define SCCR_USBDRCM_0 0x00000000 7676f3931a2SDave Liu #define SCCR_USBDRCM_1 0x00400000 7686f3931a2SDave Liu #define SCCR_USBDRCM_2 0x00800000 7696f3931a2SDave Liu #define SCCR_USBDRCM_3 0x00c00000 770555da617SDave Liu 7716f3931a2SDave Liu #define SCCR_PCIEXP1CM 0x00300000 7726f3931a2SDave Liu #define SCCR_PCIEXP2CM 0x000c0000 773555da617SDave Liu 7746f3931a2SDave Liu #define SCCR_SATA1CM 0x00003000 7756f3931a2SDave Liu #define SCCR_SATA1CM_SHIFT 12 7766f3931a2SDave Liu #define SCCR_SATACM 0x00003c00 7776f3931a2SDave Liu #define SCCR_SATACM_SHIFT 10 778555da617SDave Liu #define SCCR_SATACM_0 0x00000000 7796f3931a2SDave Liu #define SCCR_SATACM_1 0x00001400 7806f3931a2SDave Liu #define SCCR_SATACM_2 0x00002800 7816f3931a2SDave Liu #define SCCR_SATACM_3 0x00003c00 782555da617SDave Liu 7836f3931a2SDave Liu #define SCCR_TDMCM 0x00000030 7846f3931a2SDave Liu #define SCCR_TDMCM_SHIFT 4 785555da617SDave Liu #define SCCR_TDMCM_0 0x00000000 7866f3931a2SDave Liu #define SCCR_TDMCM_1 0x00000010 7876f3931a2SDave Liu #define SCCR_TDMCM_2 0x00000020 7886f3931a2SDave Liu #define SCCR_TDMCM_3 0x00000030 789555da617SDave Liu 79003051c3dSDave Liu #elif defined(CONFIG_MPC837X) 79103051c3dSDave Liu /* SCCR bits - MPC837x specific */ 79203051c3dSDave Liu #define SCCR_TSEC1CM 0xc0000000 79303051c3dSDave Liu #define SCCR_TSEC1CM_SHIFT 30 79403051c3dSDave Liu #define SCCR_TSEC1CM_0 0x00000000 79503051c3dSDave Liu #define SCCR_TSEC1CM_1 0x40000000 79603051c3dSDave Liu #define SCCR_TSEC1CM_2 0x80000000 79703051c3dSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 79803051c3dSDave Liu 79903051c3dSDave Liu #define SCCR_TSEC2CM 0x30000000 80003051c3dSDave Liu #define SCCR_TSEC2CM_SHIFT 28 80103051c3dSDave Liu #define SCCR_TSEC2CM_0 0x00000000 80203051c3dSDave Liu #define SCCR_TSEC2CM_1 0x10000000 80303051c3dSDave Liu #define SCCR_TSEC2CM_2 0x20000000 80403051c3dSDave Liu #define SCCR_TSEC2CM_3 0x30000000 80503051c3dSDave Liu 80603051c3dSDave Liu #define SCCR_SDHCCM 0x0c000000 80703051c3dSDave Liu #define SCCR_SDHCCM_SHIFT 26 80803051c3dSDave Liu #define SCCR_SDHCCM_0 0x00000000 80903051c3dSDave Liu #define SCCR_SDHCCM_1 0x04000000 81003051c3dSDave Liu #define SCCR_SDHCCM_2 0x08000000 81103051c3dSDave Liu #define SCCR_SDHCCM_3 0x0c000000 81203051c3dSDave Liu 81303051c3dSDave Liu #define SCCR_USBDRCM 0x00c00000 81403051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 22 81503051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 81603051c3dSDave Liu #define SCCR_USBDRCM_1 0x00400000 81703051c3dSDave Liu #define SCCR_USBDRCM_2 0x00800000 81803051c3dSDave Liu #define SCCR_USBDRCM_3 0x00c00000 81903051c3dSDave Liu 82003051c3dSDave Liu #define SCCR_PCIEXP1CM 0x00300000 82103051c3dSDave Liu #define SCCR_PCIEXP1CM_SHIFT 20 82203051c3dSDave Liu #define SCCR_PCIEXP1CM_0 0x00000000 82303051c3dSDave Liu #define SCCR_PCIEXP1CM_1 0x00100000 82403051c3dSDave Liu #define SCCR_PCIEXP1CM_2 0x00200000 82503051c3dSDave Liu #define SCCR_PCIEXP1CM_3 0x00300000 82603051c3dSDave Liu 82703051c3dSDave Liu #define SCCR_PCIEXP2CM 0x000c0000 82803051c3dSDave Liu #define SCCR_PCIEXP2CM_SHIFT 18 82903051c3dSDave Liu #define SCCR_PCIEXP2CM_0 0x00000000 83003051c3dSDave Liu #define SCCR_PCIEXP2CM_1 0x00040000 83103051c3dSDave Liu #define SCCR_PCIEXP2CM_2 0x00080000 83203051c3dSDave Liu #define SCCR_PCIEXP2CM_3 0x000c0000 83303051c3dSDave Liu 83403051c3dSDave Liu /* All of the four SATA controllers must have the same clock ratio */ 835*a8cb43a8SDave Liu #define SCCR_SATA1CM 0x000000c0 836*a8cb43a8SDave Liu #define SCCR_SATA1CM_SHIFT 6 83703051c3dSDave Liu #define SCCR_SATACM 0x000000ff 83803051c3dSDave Liu #define SCCR_SATACM_SHIFT 0 83903051c3dSDave Liu #define SCCR_SATACM_0 0x00000000 84003051c3dSDave Liu #define SCCR_SATACM_1 0x00000055 84103051c3dSDave Liu #define SCCR_SATACM_2 0x000000aa 84203051c3dSDave Liu #define SCCR_SATACM_3 0x000000ff 84303051c3dSDave Liu #endif 844e080313cSDave Liu 845e080313cSDave Liu /* CSn_BDNS - Chip Select memory Bounds Register 846e080313cSDave Liu */ 847e080313cSDave Liu #define CSBNDS_SA 0x00FF0000 848e080313cSDave Liu #define CSBNDS_SA_SHIFT 8 849e080313cSDave Liu #define CSBNDS_EA 0x000000FF 850e080313cSDave Liu #define CSBNDS_EA_SHIFT 24 851e080313cSDave Liu 852e080313cSDave Liu /* CSn_CONFIG - Chip Select Configuration Register 853e080313cSDave Liu */ 854e080313cSDave Liu #define CSCONFIG_EN 0x80000000 855e080313cSDave Liu #define CSCONFIG_AP 0x00800000 8569e896478SKim Phillips #define CSCONFIG_ODT_WR_ACS 0x00010000 857e080313cSDave Liu #define CSCONFIG_ROW_BIT 0x00000700 858e080313cSDave Liu #define CSCONFIG_ROW_BIT_12 0x00000000 859e080313cSDave Liu #define CSCONFIG_ROW_BIT_13 0x00000100 860e080313cSDave Liu #define CSCONFIG_ROW_BIT_14 0x00000200 861e080313cSDave Liu #define CSCONFIG_COL_BIT 0x00000007 862e080313cSDave Liu #define CSCONFIG_COL_BIT_8 0x00000000 863e080313cSDave Liu #define CSCONFIG_COL_BIT_9 0x00000001 864e080313cSDave Liu #define CSCONFIG_COL_BIT_10 0x00000002 865e080313cSDave Liu #define CSCONFIG_COL_BIT_11 0x00000003 866e080313cSDave Liu 867d87c57b2SScott Wood /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 868d87c57b2SScott Wood */ 869d87c57b2SScott Wood #define TIMING_CFG0_RWT 0xC0000000 870d87c57b2SScott Wood #define TIMING_CFG0_RWT_SHIFT 30 871d87c57b2SScott Wood #define TIMING_CFG0_WRT 0x30000000 872d87c57b2SScott Wood #define TIMING_CFG0_WRT_SHIFT 28 873d87c57b2SScott Wood #define TIMING_CFG0_RRT 0x0C000000 874d87c57b2SScott Wood #define TIMING_CFG0_RRT_SHIFT 26 875d87c57b2SScott Wood #define TIMING_CFG0_WWT 0x03000000 876d87c57b2SScott Wood #define TIMING_CFG0_WWT_SHIFT 24 877d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 878d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 879d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 880d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 881d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 882d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 883d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC 0x00000F00 884d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC_SHIFT 0 885d87c57b2SScott Wood 886e080313cSDave Liu /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 887e080313cSDave Liu */ 888e080313cSDave Liu #define TIMING_CFG1_PRETOACT 0x70000000 889e080313cSDave Liu #define TIMING_CFG1_PRETOACT_SHIFT 28 890e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE 0x0F000000 891e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE_SHIFT 24 892e080313cSDave Liu #define TIMING_CFG1_ACTTORW 0x00700000 893e080313cSDave Liu #define TIMING_CFG1_ACTTORW_SHIFT 20 894e080313cSDave Liu #define TIMING_CFG1_CASLAT 0x00070000 895e080313cSDave Liu #define TIMING_CFG1_CASLAT_SHIFT 16 896e080313cSDave Liu #define TIMING_CFG1_REFREC 0x0000F000 897e080313cSDave Liu #define TIMING_CFG1_REFREC_SHIFT 12 898e080313cSDave Liu #define TIMING_CFG1_WRREC 0x00000700 899e080313cSDave Liu #define TIMING_CFG1_WRREC_SHIFT 8 900e080313cSDave Liu #define TIMING_CFG1_ACTTOACT 0x00000070 901e080313cSDave Liu #define TIMING_CFG1_ACTTOACT_SHIFT 4 902e080313cSDave Liu #define TIMING_CFG1_WRTORD 0x00000007 903e080313cSDave Liu #define TIMING_CFG1_WRTORD_SHIFT 0 904e080313cSDave Liu #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 905e080313cSDave Liu #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 906e080313cSDave Liu 907e080313cSDave Liu /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 908e080313cSDave Liu */ 9098d172c0fSXie Xiaobo #define TIMING_CFG2_CPO 0x0F800000 9108d172c0fSXie Xiaobo #define TIMING_CFG2_CPO_SHIFT 23 911e080313cSDave Liu #define TIMING_CFG2_ACSM 0x00080000 912e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 913e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 914e080313cSDave Liu #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 915e080313cSDave Liu 916d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT 0x70000000 917d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT_SHIFT 28 918d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 919d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 920d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE 0x0000E000 921d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 922d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS 0x000001C0 923d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS_SHIFT 6 924d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT 0x0000003F 925d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT_SHIFT 0 926d87c57b2SScott Wood 927e080313cSDave Liu /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 928e080313cSDave Liu */ 929e080313cSDave Liu #define SDRAM_CFG_MEM_EN 0x80000000 930e080313cSDave Liu #define SDRAM_CFG_SREN 0x40000000 931e080313cSDave Liu #define SDRAM_CFG_ECC_EN 0x20000000 932e080313cSDave Liu #define SDRAM_CFG_RD_EN 0x10000000 933bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 934bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 935bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 936e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 937e080313cSDave Liu #define SDRAM_CFG_DYN_PWR 0x00200000 938e080313cSDave Liu #define SDRAM_CFG_32_BE 0x00080000 939e080313cSDave Liu #define SDRAM_CFG_8_BE 0x00040000 940e080313cSDave Liu #define SDRAM_CFG_NCAP 0x00020000 941e080313cSDave Liu #define SDRAM_CFG_2T_EN 0x00008000 942d87c57b2SScott Wood #define SDRAM_CFG_BI 0x00000001 943e080313cSDave Liu 944e080313cSDave Liu /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 945e080313cSDave Liu */ 946e080313cSDave Liu #define SDRAM_MODE_ESD 0xFFFF0000 947e080313cSDave Liu #define SDRAM_MODE_ESD_SHIFT 16 948e080313cSDave Liu #define SDRAM_MODE_SD 0x0000FFFF 949e080313cSDave Liu #define SDRAM_MODE_SD_SHIFT 0 950e080313cSDave Liu #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 951e080313cSDave Liu #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 952e080313cSDave Liu #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 953e080313cSDave Liu #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 954e080313cSDave Liu #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 955e080313cSDave Liu #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 956e080313cSDave Liu #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 957e080313cSDave Liu #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 958e080313cSDave Liu #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 959e080313cSDave Liu #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 960e080313cSDave Liu #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 961e080313cSDave Liu #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 962e080313cSDave Liu #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 963e080313cSDave Liu #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 964e080313cSDave Liu #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 965e080313cSDave Liu #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 966e080313cSDave Liu #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 967e080313cSDave Liu #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 968e080313cSDave Liu #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 969e080313cSDave Liu 970e080313cSDave Liu /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 971e080313cSDave Liu */ 972e080313cSDave Liu #define SDRAM_INTERVAL_REFINT 0x3FFF0000 973e080313cSDave Liu #define SDRAM_INTERVAL_REFINT_SHIFT 16 974e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 975e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 976e080313cSDave Liu 977e080313cSDave Liu /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 978e080313cSDave Liu */ 979e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 980e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 981e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 982e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 983e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 984e080313cSDave Liu 985e080313cSDave Liu /* ECC_ERR_INJECT - Memory data path error injection mask ECC 986e080313cSDave Liu */ 987e080313cSDave Liu #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 988e080313cSDave Liu #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 989e080313cSDave Liu #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 990e080313cSDave Liu #define ECC_ERR_INJECT_EEIM_SHIFT 0 991e080313cSDave Liu 992e080313cSDave Liu /* CAPTURE_ECC - Memory data path read capture ECC 993e080313cSDave Liu */ 994e080313cSDave Liu #define CAPTURE_ECC_ECE (0xff000000>>24) 995e080313cSDave Liu #define CAPTURE_ECC_ECE_SHIFT 0 996e080313cSDave Liu 997e080313cSDave Liu /* ERR_DETECT - Memory error detect 998e080313cSDave Liu */ 999e080313cSDave Liu #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 1000e080313cSDave Liu #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 1001e080313cSDave Liu #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 1002e080313cSDave Liu #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 1003e080313cSDave Liu 1004e080313cSDave Liu /* ERR_DISABLE - Memory error disable 1005e080313cSDave Liu */ 1006e080313cSDave Liu #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 1007e080313cSDave Liu #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 1008e080313cSDave Liu #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 1009e080313cSDave Liu #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 1010e080313cSDave Liu ECC_ERROR_DISABLE_MBED) 1011e080313cSDave Liu /* ERR_INT_EN - Memory error interrupt enable 1012e080313cSDave Liu */ 1013e080313cSDave Liu #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 1014e080313cSDave Liu #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 1015e080313cSDave Liu #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 1016e080313cSDave Liu #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 1017e080313cSDave Liu ECC_ERR_INT_EN_MSEE) 1018e080313cSDave Liu /* CAPTURE_ATTRIBUTES - Memory error attributes capture 1019e080313cSDave Liu */ 1020e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 1021e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM_SHIFT 28 1022e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 1023e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 1024e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 1025e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1026e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1027e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 1028e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 1029e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1030e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1031e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1032e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1033e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1034e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1035e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1036e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1037e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1038e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1039e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1040e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_SHIFT 16 1041e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 1042e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1043e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_READ 0x2 1044e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1045e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1046e080313cSDave Liu #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 1047e080313cSDave Liu 1048e080313cSDave Liu /* ERR_SBE - Single bit ECC memory error management 1049e080313cSDave Liu */ 1050e080313cSDave Liu #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 1051e080313cSDave Liu #define ECC_ERROR_MAN_SBET_SHIFT 16 1052e080313cSDave Liu #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 1053e080313cSDave Liu #define ECC_ERROR_MAN_SBEC_SHIFT 0 1054e080313cSDave Liu 1055e080313cSDave Liu /* BR - Base Registers 1056e080313cSDave Liu */ 1057e080313cSDave Liu #define BR0 0x5000 /* Register offset to immr */ 1058f046ccd1SEran Liberty #define BR1 0x5008 1059f046ccd1SEran Liberty #define BR2 0x5010 1060f046ccd1SEran Liberty #define BR3 0x5018 1061f046ccd1SEran Liberty #define BR4 0x5020 1062f046ccd1SEran Liberty #define BR5 0x5028 1063f046ccd1SEran Liberty #define BR6 0x5030 1064f046ccd1SEran Liberty #define BR7 0x5038 1065f046ccd1SEran Liberty 1066f046ccd1SEran Liberty #define BR_BA 0xFFFF8000 1067f046ccd1SEran Liberty #define BR_BA_SHIFT 15 1068f046ccd1SEran Liberty #define BR_PS 0x00001800 1069f046ccd1SEran Liberty #define BR_PS_SHIFT 11 1070e6f2e902SMarian Balakowicz #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 1071e6f2e902SMarian Balakowicz #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 1072e6f2e902SMarian Balakowicz #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 1073f046ccd1SEran Liberty #define BR_DECC 0x00000600 1074f046ccd1SEran Liberty #define BR_DECC_SHIFT 9 1075d87c57b2SScott Wood #define BR_DECC_OFF 0x00000000 1076d87c57b2SScott Wood #define BR_DECC_CHK 0x00000200 1077d87c57b2SScott Wood #define BR_DECC_CHK_GEN 0x00000400 1078f046ccd1SEran Liberty #define BR_WP 0x00000100 1079f046ccd1SEran Liberty #define BR_WP_SHIFT 8 1080f046ccd1SEran Liberty #define BR_MSEL 0x000000E0 1081f046ccd1SEran Liberty #define BR_MSEL_SHIFT 5 1082e6f2e902SMarian Balakowicz #define BR_MS_GPCM 0x00000000 /* GPCM */ 1083d87c57b2SScott Wood #define BR_MS_FCM 0x00000020 /* FCM */ 1084e6f2e902SMarian Balakowicz #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 1085e6f2e902SMarian Balakowicz #define BR_MS_UPMA 0x00000080 /* UPMA */ 1086e6f2e902SMarian Balakowicz #define BR_MS_UPMB 0x000000A0 /* UPMB */ 1087e6f2e902SMarian Balakowicz #define BR_MS_UPMC 0x000000C0 /* UPMC */ 108803051c3dSDave Liu #if !defined(CONFIG_MPC834X) 10895f820439SDave Liu #define BR_ATOM 0x0000000C 10905f820439SDave Liu #define BR_ATOM_SHIFT 2 10915f820439SDave Liu #endif 1092f046ccd1SEran Liberty #define BR_V 0x00000001 1093f046ccd1SEran Liberty #define BR_V_SHIFT 0 1094e080313cSDave Liu 10953e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 1096f046ccd1SEran Liberty #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) 109703051c3dSDave Liu #else 10985f820439SDave Liu #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) 10995f820439SDave Liu #endif 1100f046ccd1SEran Liberty 1101e080313cSDave Liu /* OR - Option Registers 1102e080313cSDave Liu */ 1103e080313cSDave Liu #define OR0 0x5004 /* Register offset to immr */ 1104f046ccd1SEran Liberty #define OR1 0x500C 1105f046ccd1SEran Liberty #define OR2 0x5014 1106f046ccd1SEran Liberty #define OR3 0x501C 1107f046ccd1SEran Liberty #define OR4 0x5024 1108f046ccd1SEran Liberty #define OR5 0x502C 1109f046ccd1SEran Liberty #define OR6 0x5034 1110f046ccd1SEran Liberty #define OR7 0x503C 1111f046ccd1SEran Liberty 1112f046ccd1SEran Liberty #define OR_GPCM_AM 0xFFFF8000 1113f046ccd1SEran Liberty #define OR_GPCM_AM_SHIFT 15 1114f046ccd1SEran Liberty #define OR_GPCM_BCTLD 0x00001000 1115f046ccd1SEran Liberty #define OR_GPCM_BCTLD_SHIFT 12 1116f046ccd1SEran Liberty #define OR_GPCM_CSNT 0x00000800 1117f046ccd1SEran Liberty #define OR_GPCM_CSNT_SHIFT 11 1118f046ccd1SEran Liberty #define OR_GPCM_ACS 0x00000600 1119f046ccd1SEran Liberty #define OR_GPCM_ACS_SHIFT 9 1120e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b10 0x00000400 1121e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b11 0x00000600 1122f046ccd1SEran Liberty #define OR_GPCM_XACS 0x00000100 1123f046ccd1SEran Liberty #define OR_GPCM_XACS_SHIFT 8 1124f046ccd1SEran Liberty #define OR_GPCM_SCY 0x000000F0 1125f046ccd1SEran Liberty #define OR_GPCM_SCY_SHIFT 4 1126e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_1 0x00000010 1127e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_2 0x00000020 1128e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_3 0x00000030 1129e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_4 0x00000040 1130e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_5 0x00000050 1131e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_6 0x00000060 1132e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_7 0x00000070 1133e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_8 0x00000080 1134e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_9 0x00000090 1135e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_10 0x000000a0 1136e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_11 0x000000b0 1137e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_12 0x000000c0 1138e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_13 0x000000d0 1139e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_14 0x000000e0 1140e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_15 0x000000f0 1141f046ccd1SEran Liberty #define OR_GPCM_SETA 0x00000008 1142f046ccd1SEran Liberty #define OR_GPCM_SETA_SHIFT 3 1143f046ccd1SEran Liberty #define OR_GPCM_TRLX 0x00000004 1144f046ccd1SEran Liberty #define OR_GPCM_TRLX_SHIFT 2 1145f046ccd1SEran Liberty #define OR_GPCM_EHTR 0x00000002 1146f046ccd1SEran Liberty #define OR_GPCM_EHTR_SHIFT 1 1147f046ccd1SEran Liberty #define OR_GPCM_EAD 0x00000001 1148f046ccd1SEran Liberty #define OR_GPCM_EAD_SHIFT 0 1149f046ccd1SEran Liberty 1150d87c57b2SScott Wood #define OR_FCM_AM 0xFFFF8000 1151d87c57b2SScott Wood #define OR_FCM_AM_SHIFT 15 1152d87c57b2SScott Wood #define OR_FCM_BCTLD 0x00001000 1153d87c57b2SScott Wood #define OR_FCM_BCTLD_SHIFT 12 1154d87c57b2SScott Wood #define OR_FCM_PGS 0x00000400 1155d87c57b2SScott Wood #define OR_FCM_PGS_SHIFT 10 1156d87c57b2SScott Wood #define OR_FCM_CSCT 0x00000200 1157d87c57b2SScott Wood #define OR_FCM_CSCT_SHIFT 9 1158d87c57b2SScott Wood #define OR_FCM_CST 0x00000100 1159d87c57b2SScott Wood #define OR_FCM_CST_SHIFT 8 1160d87c57b2SScott Wood #define OR_FCM_CHT 0x00000080 1161d87c57b2SScott Wood #define OR_FCM_CHT_SHIFT 7 1162d87c57b2SScott Wood #define OR_FCM_SCY 0x00000070 1163d87c57b2SScott Wood #define OR_FCM_SCY_SHIFT 4 1164d87c57b2SScott Wood #define OR_FCM_SCY_1 0x00000010 1165d87c57b2SScott Wood #define OR_FCM_SCY_2 0x00000020 1166d87c57b2SScott Wood #define OR_FCM_SCY_3 0x00000030 1167d87c57b2SScott Wood #define OR_FCM_SCY_4 0x00000040 1168d87c57b2SScott Wood #define OR_FCM_SCY_5 0x00000050 1169d87c57b2SScott Wood #define OR_FCM_SCY_6 0x00000060 1170d87c57b2SScott Wood #define OR_FCM_SCY_7 0x00000070 1171d87c57b2SScott Wood #define OR_FCM_RST 0x00000008 1172d87c57b2SScott Wood #define OR_FCM_RST_SHIFT 3 1173d87c57b2SScott Wood #define OR_FCM_TRLX 0x00000004 1174d87c57b2SScott Wood #define OR_FCM_TRLX_SHIFT 2 1175d87c57b2SScott Wood #define OR_FCM_EHTR 0x00000002 1176d87c57b2SScott Wood #define OR_FCM_EHTR_SHIFT 1 1177d87c57b2SScott Wood 1178f046ccd1SEran Liberty #define OR_UPM_AM 0xFFFF8000 1179f046ccd1SEran Liberty #define OR_UPM_AM_SHIFT 15 1180f046ccd1SEran Liberty #define OR_UPM_XAM 0x00006000 1181f046ccd1SEran Liberty #define OR_UPM_XAM_SHIFT 13 1182f046ccd1SEran Liberty #define OR_UPM_BCTLD 0x00001000 1183f046ccd1SEran Liberty #define OR_UPM_BCTLD_SHIFT 12 1184f046ccd1SEran Liberty #define OR_UPM_BI 0x00000100 1185f046ccd1SEran Liberty #define OR_UPM_BI_SHIFT 8 1186f046ccd1SEran Liberty #define OR_UPM_TRLX 0x00000004 1187f046ccd1SEran Liberty #define OR_UPM_TRLX_SHIFT 2 1188f046ccd1SEran Liberty #define OR_UPM_EHTR 0x00000002 1189f046ccd1SEran Liberty #define OR_UPM_EHTR_SHIFT 1 1190f046ccd1SEran Liberty #define OR_UPM_EAD 0x00000001 1191f046ccd1SEran Liberty #define OR_UPM_EAD_SHIFT 0 1192f046ccd1SEran Liberty 1193f046ccd1SEran Liberty #define OR_SDRAM_AM 0xFFFF8000 1194f046ccd1SEran Liberty #define OR_SDRAM_AM_SHIFT 15 1195f046ccd1SEran Liberty #define OR_SDRAM_XAM 0x00006000 1196f046ccd1SEran Liberty #define OR_SDRAM_XAM_SHIFT 13 1197f046ccd1SEran Liberty #define OR_SDRAM_COLS 0x00001C00 1198f046ccd1SEran Liberty #define OR_SDRAM_COLS_SHIFT 10 1199f046ccd1SEran Liberty #define OR_SDRAM_ROWS 0x000001C0 1200f046ccd1SEran Liberty #define OR_SDRAM_ROWS_SHIFT 6 1201f046ccd1SEran Liberty #define OR_SDRAM_PMSEL 0x00000020 1202f046ccd1SEran Liberty #define OR_SDRAM_PMSEL_SHIFT 5 1203f046ccd1SEran Liberty #define OR_SDRAM_EAD 0x00000001 1204f046ccd1SEran Liberty #define OR_SDRAM_EAD_SHIFT 0 1205f046ccd1SEran Liberty 12067a78f148STimur Tabi #define OR_AM_32KB 0xFFFF8000 12077a78f148STimur Tabi #define OR_AM_64KB 0xFFFF0000 12087a78f148STimur Tabi #define OR_AM_128KB 0xFFFE0000 12097a78f148STimur Tabi #define OR_AM_256KB 0xFFFC0000 12107a78f148STimur Tabi #define OR_AM_512KB 0xFFF80000 12117a78f148STimur Tabi #define OR_AM_1MB 0xFFF00000 12127a78f148STimur Tabi #define OR_AM_2MB 0xFFE00000 12137a78f148STimur Tabi #define OR_AM_4MB 0xFFC00000 12147a78f148STimur Tabi #define OR_AM_8MB 0xFF800000 12157a78f148STimur Tabi #define OR_AM_16MB 0xFF000000 12167a78f148STimur Tabi #define OR_AM_32MB 0xFE000000 12177a78f148STimur Tabi #define OR_AM_64MB 0xFC000000 12187a78f148STimur Tabi #define OR_AM_128MB 0xF8000000 12197a78f148STimur Tabi #define OR_AM_256MB 0xF0000000 12207a78f148STimur Tabi #define OR_AM_512MB 0xE0000000 12217a78f148STimur Tabi #define OR_AM_1GB 0xC0000000 12227a78f148STimur Tabi #define OR_AM_2GB 0x80000000 12237a78f148STimur Tabi #define OR_AM_4GB 0x00000000 12247a78f148STimur Tabi 12257a78f148STimur Tabi #define LBLAWAR_EN 0x80000000 12267a78f148STimur Tabi #define LBLAWAR_4KB 0x0000000B 12277a78f148STimur Tabi #define LBLAWAR_8KB 0x0000000C 12287a78f148STimur Tabi #define LBLAWAR_16KB 0x0000000D 12297a78f148STimur Tabi #define LBLAWAR_32KB 0x0000000E 12307a78f148STimur Tabi #define LBLAWAR_64KB 0x0000000F 12317a78f148STimur Tabi #define LBLAWAR_128KB 0x00000010 12327a78f148STimur Tabi #define LBLAWAR_256KB 0x00000011 12337a78f148STimur Tabi #define LBLAWAR_512KB 0x00000012 12347a78f148STimur Tabi #define LBLAWAR_1MB 0x00000013 12357a78f148STimur Tabi #define LBLAWAR_2MB 0x00000014 12367a78f148STimur Tabi #define LBLAWAR_4MB 0x00000015 12377a78f148STimur Tabi #define LBLAWAR_8MB 0x00000016 12387a78f148STimur Tabi #define LBLAWAR_16MB 0x00000017 12397a78f148STimur Tabi #define LBLAWAR_32MB 0x00000018 12407a78f148STimur Tabi #define LBLAWAR_64MB 0x00000019 12417a78f148STimur Tabi #define LBLAWAR_128MB 0x0000001A 12427a78f148STimur Tabi #define LBLAWAR_256MB 0x0000001B 12437a78f148STimur Tabi #define LBLAWAR_512MB 0x0000001C 12447a78f148STimur Tabi #define LBLAWAR_1GB 0x0000001D 12457a78f148STimur Tabi #define LBLAWAR_2GB 0x0000001E 12467a78f148STimur Tabi 1247e080313cSDave Liu /* LBCR - Local Bus Configuration Register 1248f046ccd1SEran Liberty */ 1249e080313cSDave Liu #define LBCR_LDIS 0x80000000 1250e080313cSDave Liu #define LBCR_LDIS_SHIFT 31 1251e080313cSDave Liu #define LBCR_BCTLC 0x00C00000 1252e080313cSDave Liu #define LBCR_BCTLC_SHIFT 22 1253e080313cSDave Liu #define LBCR_LPBSE 0x00020000 1254e080313cSDave Liu #define LBCR_LPBSE_SHIFT 17 1255e080313cSDave Liu #define LBCR_EPAR 0x00010000 1256e080313cSDave Liu #define LBCR_EPAR_SHIFT 16 1257e080313cSDave Liu #define LBCR_BMT 0x0000FF00 1258e080313cSDave Liu #define LBCR_BMT_SHIFT 8 1259f046ccd1SEran Liberty 1260e080313cSDave Liu /* LCRR - Clock Ratio Register 1261f046ccd1SEran Liberty */ 1262f046ccd1SEran Liberty #define LCRR_DBYP 0x80000000 1263f046ccd1SEran Liberty #define LCRR_DBYP_SHIFT 31 1264f046ccd1SEran Liberty #define LCRR_BUFCMDC 0x30000000 1265e080313cSDave Liu #define LCRR_BUFCMDC_SHIFT 28 1266f046ccd1SEran Liberty #define LCRR_BUFCMDC_1 0x10000000 1267f046ccd1SEran Liberty #define LCRR_BUFCMDC_2 0x20000000 1268f046ccd1SEran Liberty #define LCRR_BUFCMDC_3 0x30000000 1269f046ccd1SEran Liberty #define LCRR_BUFCMDC_4 0x00000000 1270f046ccd1SEran Liberty #define LCRR_ECL 0x03000000 1271e080313cSDave Liu #define LCRR_ECL_SHIFT 24 1272f046ccd1SEran Liberty #define LCRR_ECL_4 0x00000000 1273f046ccd1SEran Liberty #define LCRR_ECL_5 0x01000000 1274f046ccd1SEran Liberty #define LCRR_ECL_6 0x02000000 1275f046ccd1SEran Liberty #define LCRR_ECL_7 0x03000000 1276f046ccd1SEran Liberty #define LCRR_EADC 0x00030000 1277e080313cSDave Liu #define LCRR_EADC_SHIFT 16 1278f046ccd1SEran Liberty #define LCRR_EADC_1 0x00010000 1279f046ccd1SEran Liberty #define LCRR_EADC_2 0x00020000 1280f046ccd1SEran Liberty #define LCRR_EADC_3 0x00030000 1281f046ccd1SEran Liberty #define LCRR_EADC_4 0x00000000 1282f046ccd1SEran Liberty #define LCRR_CLKDIV 0x0000000F 1283e080313cSDave Liu #define LCRR_CLKDIV_SHIFT 0 1284f046ccd1SEran Liberty #define LCRR_CLKDIV_2 0x00000002 1285f046ccd1SEran Liberty #define LCRR_CLKDIV_4 0x00000004 1286f046ccd1SEran Liberty #define LCRR_CLKDIV_8 0x00000008 1287f046ccd1SEran Liberty 1288e080313cSDave Liu /* DMAMR - DMA Mode Register 1289f6eda7f8SDave Liu */ 1290e080313cSDave Liu #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 1291e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 1292e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 1293e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 1294e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 1295e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 1296e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 1297e080313cSDave Liu #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 1298f6eda7f8SDave Liu 1299e080313cSDave Liu /* DMASR - DMA Status Register 1300e080313cSDave Liu */ 1301e080313cSDave Liu #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 1302e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 13035f820439SDave Liu 1304e080313cSDave Liu /* CONFIG_ADDRESS - PCI Config Address Register 1305e080313cSDave Liu */ 1306e080313cSDave Liu #define PCI_CONFIG_ADDRESS_EN 0x80000000 1307e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1308e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1309e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1310e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1311e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1312e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1313e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1314e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1315e080313cSDave Liu 1316e080313cSDave Liu /* POTAR - PCI Outbound Translation Address Register 1317e080313cSDave Liu */ 1318e080313cSDave Liu #define POTAR_TA_MASK 0x000fffff 1319e080313cSDave Liu 1320e080313cSDave Liu /* POBAR - PCI Outbound Base Address Register 1321e080313cSDave Liu */ 1322e080313cSDave Liu #define POBAR_BA_MASK 0x000fffff 1323e080313cSDave Liu 1324e080313cSDave Liu /* POCMR - PCI Outbound Comparision Mask Register 1325e080313cSDave Liu */ 1326e080313cSDave Liu #define POCMR_EN 0x80000000 1327e080313cSDave Liu #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1328e080313cSDave Liu #define POCMR_SE 0x20000000 /* streaming enable */ 1329e080313cSDave Liu #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1330e080313cSDave Liu #define POCMR_CM_MASK 0x000fffff 1331e080313cSDave Liu #define POCMR_CM_4G 0x00000000 1332e080313cSDave Liu #define POCMR_CM_2G 0x00080000 1333e080313cSDave Liu #define POCMR_CM_1G 0x000C0000 1334e080313cSDave Liu #define POCMR_CM_512M 0x000E0000 1335e080313cSDave Liu #define POCMR_CM_256M 0x000F0000 1336e080313cSDave Liu #define POCMR_CM_128M 0x000F8000 1337e080313cSDave Liu #define POCMR_CM_64M 0x000FC000 1338e080313cSDave Liu #define POCMR_CM_32M 0x000FE000 1339e080313cSDave Liu #define POCMR_CM_16M 0x000FF000 1340e080313cSDave Liu #define POCMR_CM_8M 0x000FF800 1341e080313cSDave Liu #define POCMR_CM_4M 0x000FFC00 1342e080313cSDave Liu #define POCMR_CM_2M 0x000FFE00 1343e080313cSDave Liu #define POCMR_CM_1M 0x000FFF00 1344e080313cSDave Liu #define POCMR_CM_512K 0x000FFF80 1345e080313cSDave Liu #define POCMR_CM_256K 0x000FFFC0 1346e080313cSDave Liu #define POCMR_CM_128K 0x000FFFE0 1347e080313cSDave Liu #define POCMR_CM_64K 0x000FFFF0 1348e080313cSDave Liu #define POCMR_CM_32K 0x000FFFF8 1349e080313cSDave Liu #define POCMR_CM_16K 0x000FFFFC 1350e080313cSDave Liu #define POCMR_CM_8K 0x000FFFFE 1351e080313cSDave Liu #define POCMR_CM_4K 0x000FFFFF 1352e080313cSDave Liu 1353e080313cSDave Liu /* PITAR - PCI Inbound Translation Address Register 1354e080313cSDave Liu */ 1355e080313cSDave Liu #define PITAR_TA_MASK 0x000fffff 1356e080313cSDave Liu 1357e080313cSDave Liu /* PIBAR - PCI Inbound Base/Extended Address Register 1358e080313cSDave Liu */ 1359e080313cSDave Liu #define PIBAR_MASK 0xffffffff 1360e080313cSDave Liu #define PIEBAR_EBA_MASK 0x000fffff 1361e080313cSDave Liu 1362e080313cSDave Liu /* PIWAR - PCI Inbound Windows Attributes Register 1363e080313cSDave Liu */ 1364e080313cSDave Liu #define PIWAR_EN 0x80000000 1365e080313cSDave Liu #define PIWAR_PF 0x20000000 1366e080313cSDave Liu #define PIWAR_RTT_MASK 0x000f0000 1367e080313cSDave Liu #define PIWAR_RTT_NO_SNOOP 0x00040000 1368e080313cSDave Liu #define PIWAR_RTT_SNOOP 0x00050000 1369e080313cSDave Liu #define PIWAR_WTT_MASK 0x0000f000 1370e080313cSDave Liu #define PIWAR_WTT_NO_SNOOP 0x00004000 1371e080313cSDave Liu #define PIWAR_WTT_SNOOP 0x00005000 1372e080313cSDave Liu #define PIWAR_IWS_MASK 0x0000003F 1373e080313cSDave Liu #define PIWAR_IWS_4K 0x0000000B 1374e080313cSDave Liu #define PIWAR_IWS_8K 0x0000000C 1375e080313cSDave Liu #define PIWAR_IWS_16K 0x0000000D 1376e080313cSDave Liu #define PIWAR_IWS_32K 0x0000000E 1377e080313cSDave Liu #define PIWAR_IWS_64K 0x0000000F 1378e080313cSDave Liu #define PIWAR_IWS_128K 0x00000010 1379e080313cSDave Liu #define PIWAR_IWS_256K 0x00000011 1380e080313cSDave Liu #define PIWAR_IWS_512K 0x00000012 1381e080313cSDave Liu #define PIWAR_IWS_1M 0x00000013 1382e080313cSDave Liu #define PIWAR_IWS_2M 0x00000014 1383e080313cSDave Liu #define PIWAR_IWS_4M 0x00000015 1384e080313cSDave Liu #define PIWAR_IWS_8M 0x00000016 1385e080313cSDave Liu #define PIWAR_IWS_16M 0x00000017 1386e080313cSDave Liu #define PIWAR_IWS_32M 0x00000018 1387e080313cSDave Liu #define PIWAR_IWS_64M 0x00000019 1388e080313cSDave Liu #define PIWAR_IWS_128M 0x0000001A 1389e080313cSDave Liu #define PIWAR_IWS_256M 0x0000001B 1390e080313cSDave Liu #define PIWAR_IWS_512M 0x0000001C 1391e080313cSDave Liu #define PIWAR_IWS_1G 0x0000001D 1392e080313cSDave Liu #define PIWAR_IWS_2G 0x0000001E 1393f6eda7f8SDave Liu 1394d87c57b2SScott Wood /* PMCCR1 - PCI Configuration Register 1 1395d87c57b2SScott Wood */ 1396d87c57b2SScott Wood #define PMCCR1_POWER_OFF 0x00000020 1397d87c57b2SScott Wood 1398d87c57b2SScott Wood /* FMR - Flash Mode Register 1399d87c57b2SScott Wood */ 1400d87c57b2SScott Wood #define FMR_CWTO 0x0000F000 1401d87c57b2SScott Wood #define FMR_CWTO_SHIFT 12 1402d87c57b2SScott Wood #define FMR_BOOT 0x00000800 1403d87c57b2SScott Wood #define FMR_ECCM 0x00000100 1404d87c57b2SScott Wood #define FMR_AL 0x00000030 1405d87c57b2SScott Wood #define FMR_AL_SHIFT 4 1406d87c57b2SScott Wood #define FMR_OP 0x00000003 1407d87c57b2SScott Wood #define FMR_OP_SHIFT 0 1408d87c57b2SScott Wood 1409d87c57b2SScott Wood /* FIR - Flash Instruction Register 1410d87c57b2SScott Wood */ 1411d87c57b2SScott Wood #define FIR_OP0 0xF0000000 1412d87c57b2SScott Wood #define FIR_OP0_SHIFT 28 1413d87c57b2SScott Wood #define FIR_OP1 0x0F000000 1414d87c57b2SScott Wood #define FIR_OP1_SHIFT 24 1415d87c57b2SScott Wood #define FIR_OP2 0x00F00000 1416d87c57b2SScott Wood #define FIR_OP2_SHIFT 20 1417d87c57b2SScott Wood #define FIR_OP3 0x000F0000 1418d87c57b2SScott Wood #define FIR_OP3_SHIFT 16 1419d87c57b2SScott Wood #define FIR_OP4 0x0000F000 1420d87c57b2SScott Wood #define FIR_OP4_SHIFT 12 1421d87c57b2SScott Wood #define FIR_OP5 0x00000F00 1422d87c57b2SScott Wood #define FIR_OP5_SHIFT 8 1423d87c57b2SScott Wood #define FIR_OP6 0x000000F0 1424d87c57b2SScott Wood #define FIR_OP6_SHIFT 4 1425d87c57b2SScott Wood #define FIR_OP7 0x0000000F 1426d87c57b2SScott Wood #define FIR_OP7_SHIFT 0 1427d87c57b2SScott Wood #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 1428d87c57b2SScott Wood #define FIR_OP_CA 0x1 /* Issue current column address */ 1429d87c57b2SScott Wood #define FIR_OP_PA 0x2 /* Issue current block+page address */ 1430d87c57b2SScott Wood #define FIR_OP_UA 0x3 /* Issue user defined address */ 1431d87c57b2SScott Wood #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 1432d87c57b2SScott Wood #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 1433d87c57b2SScott Wood #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 1434d87c57b2SScott Wood #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 1435d87c57b2SScott Wood #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 1436d87c57b2SScott Wood #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 1437d87c57b2SScott Wood #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 1438d87c57b2SScott Wood #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 1439d87c57b2SScott Wood #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 1440d87c57b2SScott Wood #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 1441d87c57b2SScott Wood #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 1442d87c57b2SScott Wood #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 1443d87c57b2SScott Wood 1444d87c57b2SScott Wood /* FCR - Flash Command Register 1445d87c57b2SScott Wood */ 1446d87c57b2SScott Wood #define FCR_CMD0 0xFF000000 1447d87c57b2SScott Wood #define FCR_CMD0_SHIFT 24 1448d87c57b2SScott Wood #define FCR_CMD1 0x00FF0000 1449d87c57b2SScott Wood #define FCR_CMD1_SHIFT 16 1450d87c57b2SScott Wood #define FCR_CMD2 0x0000FF00 1451d87c57b2SScott Wood #define FCR_CMD2_SHIFT 8 1452d87c57b2SScott Wood #define FCR_CMD3 0x000000FF 1453d87c57b2SScott Wood #define FCR_CMD3_SHIFT 0 1454d87c57b2SScott Wood 1455d87c57b2SScott Wood /* FBAR - Flash Block Address Register 1456d87c57b2SScott Wood */ 1457d87c57b2SScott Wood #define FBAR_BLK 0x00FFFFFF 1458d87c57b2SScott Wood 1459d87c57b2SScott Wood /* FPAR - Flash Page Address Register 1460d87c57b2SScott Wood */ 1461d87c57b2SScott Wood #define FPAR_SP_PI 0x00007C00 1462d87c57b2SScott Wood #define FPAR_SP_PI_SHIFT 10 1463d87c57b2SScott Wood #define FPAR_SP_MS 0x00000200 1464d87c57b2SScott Wood #define FPAR_SP_CI 0x000001FF 1465d87c57b2SScott Wood #define FPAR_SP_CI_SHIFT 0 1466d87c57b2SScott Wood #define FPAR_LP_PI 0x0003F000 1467d87c57b2SScott Wood #define FPAR_LP_PI_SHIFT 12 1468d87c57b2SScott Wood #define FPAR_LP_MS 0x00000800 1469d87c57b2SScott Wood #define FPAR_LP_CI 0x000007FF 1470d87c57b2SScott Wood #define FPAR_LP_CI_SHIFT 0 1471d87c57b2SScott Wood 1472d87c57b2SScott Wood /* LTESR - Transfer Error Status Register 1473d87c57b2SScott Wood */ 1474d87c57b2SScott Wood #define LTESR_BM 0x80000000 1475d87c57b2SScott Wood #define LTESR_FCT 0x40000000 1476d87c57b2SScott Wood #define LTESR_PAR 0x20000000 1477d87c57b2SScott Wood #define LTESR_WP 0x04000000 1478d87c57b2SScott Wood #define LTESR_ATMW 0x00800000 1479d87c57b2SScott Wood #define LTESR_ATMR 0x00400000 1480d87c57b2SScott Wood #define LTESR_CS 0x00080000 1481d87c57b2SScott Wood #define LTESR_CC 0x00000001 1482d87c57b2SScott Wood 148303051c3dSDave Liu /* DDRCDR - DDR Control Driver Register 1484d87c57b2SScott Wood */ 14859e896478SKim Phillips #define DDRCDR_DHC_EN 0x80000000 1486d87c57b2SScott Wood #define DDRCDR_EN 0x40000000 1487d87c57b2SScott Wood #define DDRCDR_PZ 0x3C000000 1488d87c57b2SScott Wood #define DDRCDR_PZ_MAXZ 0x00000000 1489d87c57b2SScott Wood #define DDRCDR_PZ_HIZ 0x20000000 1490d87c57b2SScott Wood #define DDRCDR_PZ_NOMZ 0x30000000 1491d87c57b2SScott Wood #define DDRCDR_PZ_LOZ 0x38000000 1492d87c57b2SScott Wood #define DDRCDR_PZ_MINZ 0x3C000000 1493d87c57b2SScott Wood #define DDRCDR_NZ 0x3C000000 1494d87c57b2SScott Wood #define DDRCDR_NZ_MAXZ 0x00000000 1495d87c57b2SScott Wood #define DDRCDR_NZ_HIZ 0x02000000 1496d87c57b2SScott Wood #define DDRCDR_NZ_NOMZ 0x03000000 1497d87c57b2SScott Wood #define DDRCDR_NZ_LOZ 0x03800000 1498d87c57b2SScott Wood #define DDRCDR_NZ_MINZ 0x03C00000 1499d87c57b2SScott Wood #define DDRCDR_ODT 0x00080000 1500d87c57b2SScott Wood #define DDRCDR_DDR_CFG 0x00040000 1501d87c57b2SScott Wood #define DDRCDR_M_ODR 0x00000002 1502d87c57b2SScott Wood #define DDRCDR_Q_DRN 0x00000001 1503d87c57b2SScott Wood 150449ea3b6eSScott Wood #ifndef __ASSEMBLY__ 150549ea3b6eSScott Wood struct pci_region; 150649ea3b6eSScott Wood void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 150749ea3b6eSScott Wood #endif 150849ea3b6eSScott Wood 1509f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 1510