1f046ccd1SEran Liberty /* 27c619ddcSIlya Yanok * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty */ 12f046ccd1SEran Liberty 13f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 14f046ccd1SEran Liberty #define __MPC83XX_H__ 15f046ccd1SEran Liberty 16f6eda7f8SDave Liu #include <config.h> 17bf30bb1fSAnton Vorontsov #include <asm/fsl_lbc.h> 18f046ccd1SEran Liberty #if defined(CONFIG_E300) 19f046ccd1SEran Liberty #include <asm/e300.h> 20f046ccd1SEran Liberty #endif 21f046ccd1SEran Liberty 224e8b750cSHeiko Schocher /* 234e8b750cSHeiko Schocher * MPC83xx cpu provide RCR register to do reset thing specially 24f046ccd1SEran Liberty */ 25f046ccd1SEran Liberty #define MPC83xx_RESET 26f046ccd1SEran Liberty 274e8b750cSHeiko Schocher /* 284e8b750cSHeiko Schocher * System reset offset (PowerPC standard) 29f046ccd1SEran Liberty */ 30f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 3102032e8fSRafal Jaworowski #define _START_OFFSET EXC_OFF_SYS_RESET 32f046ccd1SEran Liberty 334e8b750cSHeiko Schocher /* 344e8b750cSHeiko Schocher * IMMRBAR - Internal Memory Register Base Address 35f046ccd1SEran Liberty */ 36e4c09508SScott Wood #ifndef CONFIG_DEFAULT_IMMR 374e8b750cSHeiko Schocher /* Default IMMR base address */ 384e8b750cSHeiko Schocher #define CONFIG_DEFAULT_IMMR 0xFF400000 39e4c09508SScott Wood #endif 404e8b750cSHeiko Schocher /* Register offset to immr */ 414e8b750cSHeiko Schocher #define IMMRBAR 0x0000 424e8b750cSHeiko Schocher #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */ 43f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 44f046ccd1SEran Liberty 454e8b750cSHeiko Schocher /* 464e8b750cSHeiko Schocher * LAWBAR - Local Access Window Base Address Register 47f046ccd1SEran Liberty */ 484e8b750cSHeiko Schocher /* Register offset to immr */ 494e8b750cSHeiko Schocher #define LBLAWBAR0 0x0020 50f046ccd1SEran Liberty #define LBLAWAR0 0x0024 51f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 52f046ccd1SEran Liberty #define LBLAWAR1 0x002C 53f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 54f046ccd1SEran Liberty #define LBLAWAR2 0x0034 55f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 56f046ccd1SEran Liberty #define LBLAWAR3 0x003C 574e8b750cSHeiko Schocher #define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */ 58f046ccd1SEran Liberty 594e8b750cSHeiko Schocher /* 604e8b750cSHeiko Schocher * SPRIDR - System Part and Revision ID Register 61f6eda7f8SDave Liu */ 62e5c4ade4SKim Phillips #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ 63e5c4ade4SKim Phillips #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ 64e080313cSDave Liu 652c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 66e5c4ade4SKim Phillips #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) 67e5c4ade4SKim Phillips #define REVID_MINOR(spridr) (spridr & 0x000000FF) 68e5c4ade4SKim Phillips #else 69e5c4ade4SKim Phillips #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) 70e5c4ade4SKim Phillips #define REVID_MINOR(spridr) (spridr & 0x0000000F) 71e5c4ade4SKim Phillips #endif 725f820439SDave Liu 73e5c4ade4SKim Phillips #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) 746b70ffb9SKim Phillips #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) 755f820439SDave Liu 767c619ddcSIlya Yanok #define SPR_8308 0x8100 77*a88731a6SGerlando Falauto #define SPR_8309 0x8110 786b70ffb9SKim Phillips #define SPR_831X_FAMILY 0x80B 79e5c4ade4SKim Phillips #define SPR_8311 0x80B2 80e5c4ade4SKim Phillips #define SPR_8313 0x80B0 81e5c4ade4SKim Phillips #define SPR_8314 0x80B6 82e5c4ade4SKim Phillips #define SPR_8315 0x80B4 836b70ffb9SKim Phillips #define SPR_832X_FAMILY 0x806 84e5c4ade4SKim Phillips #define SPR_8321 0x8066 85e5c4ade4SKim Phillips #define SPR_8323 0x8062 866b70ffb9SKim Phillips #define SPR_834X_FAMILY 0x803 87e5c4ade4SKim Phillips #define SPR_8343 0x8036 88e5c4ade4SKim Phillips #define SPR_8347_TBGA_ 0x8032 89e5c4ade4SKim Phillips #define SPR_8347_PBGA_ 0x8034 90e5c4ade4SKim Phillips #define SPR_8349 0x8030 916b70ffb9SKim Phillips #define SPR_836X_FAMILY 0x804 92e5c4ade4SKim Phillips #define SPR_8358_TBGA_ 0x804A 93e5c4ade4SKim Phillips #define SPR_8358_PBGA_ 0x804E 94e5c4ade4SKim Phillips #define SPR_8360 0x8048 956b70ffb9SKim Phillips #define SPR_837X_FAMILY 0x80C 96e5c4ade4SKim Phillips #define SPR_8377 0x80C6 97e5c4ade4SKim Phillips #define SPR_8378 0x80C4 98e5c4ade4SKim Phillips #define SPR_8379 0x80C2 99d87c57b2SScott Wood 1004e8b750cSHeiko Schocher /* 1014e8b750cSHeiko Schocher * SPCR - System Priority Configuration Register 102f046ccd1SEran Liberty */ 1034e8b750cSHeiko Schocher /* PCI Highest Priority Enable */ 1044e8b750cSHeiko Schocher #define SPCR_PCIHPE 0x10000000 105e080313cSDave Liu #define SPCR_PCIHPE_SHIFT (31-3) 1064e8b750cSHeiko Schocher /* PCI bridge system bus request priority */ 1074e8b750cSHeiko Schocher #define SPCR_PCIPR 0x03000000 108e080313cSDave Liu #define SPCR_PCIPR_SHIFT (31-7) 109e080313cSDave Liu #define SPCR_OPT 0x00800000 /* Optimize */ 1105bbeea86SMichael Barkowski #define SPCR_OPT_SHIFT (31-8) 1114e8b750cSHeiko Schocher /* E300 PowerPC core time base unit enable */ 1124e8b750cSHeiko Schocher #define SPCR_TBEN 0x00400000 113e080313cSDave Liu #define SPCR_TBEN_SHIFT (31-9) 1144e8b750cSHeiko Schocher /* E300 PowerPC Core system bus request priority */ 1154e8b750cSHeiko Schocher #define SPCR_COREPR 0x00300000 116e080313cSDave Liu #define SPCR_COREPR_SHIFT (31-11) 117e080313cSDave Liu 1182c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 119e080313cSDave Liu /* SPCR bits - MPC8349 specific */ 1204e8b750cSHeiko Schocher /* TSEC1 data priority */ 1214e8b750cSHeiko Schocher #define SPCR_TSEC1DP 0x00003000 122e080313cSDave Liu #define SPCR_TSEC1DP_SHIFT (31-19) 1234e8b750cSHeiko Schocher /* TSEC1 buffer descriptor priority */ 1244e8b750cSHeiko Schocher #define SPCR_TSEC1BDP 0x00000C00 125e080313cSDave Liu #define SPCR_TSEC1BDP_SHIFT (31-21) 1264e8b750cSHeiko Schocher /* TSEC1 emergency priority */ 1274e8b750cSHeiko Schocher #define SPCR_TSEC1EP 0x00000300 128e080313cSDave Liu #define SPCR_TSEC1EP_SHIFT (31-23) 1294e8b750cSHeiko Schocher /* TSEC2 data priority */ 1304e8b750cSHeiko Schocher #define SPCR_TSEC2DP 0x00000030 131e080313cSDave Liu #define SPCR_TSEC2DP_SHIFT (31-27) 1324e8b750cSHeiko Schocher /* TSEC2 buffer descriptor priority */ 1334e8b750cSHeiko Schocher #define SPCR_TSEC2BDP 0x0000000C 134e080313cSDave Liu #define SPCR_TSEC2BDP_SHIFT (31-29) 1354e8b750cSHeiko Schocher /* TSEC2 emergency priority */ 1364e8b750cSHeiko Schocher #define SPCR_TSEC2EP 0x00000003 137e080313cSDave Liu #define SPCR_TSEC2EP_SHIFT (31-31) 138d87c57b2SScott Wood 1397c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 1407c619ddcSIlya Yanok defined(CONFIG_MPC837x) 1417c619ddcSIlya Yanok /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ 1424e8b750cSHeiko Schocher /* TSEC data priority */ 1434e8b750cSHeiko Schocher #define SPCR_TSECDP 0x00003000 144d87c57b2SScott Wood #define SPCR_TSECDP_SHIFT (31-19) 1454e8b750cSHeiko Schocher /* TSEC buffer descriptor priority */ 1464e8b750cSHeiko Schocher #define SPCR_TSECBDP 0x00000C00 147ec2638eaSDave Liu #define SPCR_TSECBDP_SHIFT (31-21) 1484e8b750cSHeiko Schocher /* TSEC emergency priority */ 1494e8b750cSHeiko Schocher #define SPCR_TSECEP 0x00000300 150ec2638eaSDave Liu #define SPCR_TSECEP_SHIFT (31-23) 151e080313cSDave Liu #endif 152e080313cSDave Liu 153e080313cSDave Liu /* SICRL/H - System I/O Configuration Register Low/High 154e080313cSDave Liu */ 1552c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 156e080313cSDave Liu /* SICRL bits - MPC8349 specific */ 157e080313cSDave Liu #define SICRL_LDP_A 0x80000000 158e080313cSDave Liu #define SICRL_USB1 0x40000000 159e080313cSDave Liu #define SICRL_USB0 0x20000000 160e080313cSDave Liu #define SICRL_UART 0x0C000000 161e080313cSDave Liu #define SICRL_GPIO1_A 0x02000000 162e080313cSDave Liu #define SICRL_GPIO1_B 0x01000000 163e080313cSDave Liu #define SICRL_GPIO1_C 0x00800000 164e080313cSDave Liu #define SICRL_GPIO1_D 0x00400000 165e080313cSDave Liu #define SICRL_GPIO1_E 0x00200000 166e080313cSDave Liu #define SICRL_GPIO1_F 0x00180000 167e080313cSDave Liu #define SICRL_GPIO1_G 0x00040000 168e080313cSDave Liu #define SICRL_GPIO1_H 0x00020000 169e080313cSDave Liu #define SICRL_GPIO1_I 0x00010000 170e080313cSDave Liu #define SICRL_GPIO1_J 0x00008000 171e080313cSDave Liu #define SICRL_GPIO1_K 0x00004000 172e080313cSDave Liu #define SICRL_GPIO1_L 0x00003000 173e080313cSDave Liu 174e080313cSDave Liu /* SICRH bits - MPC8349 specific */ 175e080313cSDave Liu #define SICRH_DDR 0x80000000 176e080313cSDave Liu #define SICRH_TSEC1_A 0x10000000 177e080313cSDave Liu #define SICRH_TSEC1_B 0x08000000 178e080313cSDave Liu #define SICRH_TSEC1_C 0x04000000 179e080313cSDave Liu #define SICRH_TSEC1_D 0x02000000 180e080313cSDave Liu #define SICRH_TSEC1_E 0x01000000 181e080313cSDave Liu #define SICRH_TSEC1_F 0x00800000 182e080313cSDave Liu #define SICRH_TSEC2_A 0x00400000 183e080313cSDave Liu #define SICRH_TSEC2_B 0x00200000 184e080313cSDave Liu #define SICRH_TSEC2_C 0x00100000 185e080313cSDave Liu #define SICRH_TSEC2_D 0x00080000 186e080313cSDave Liu #define SICRH_TSEC2_E 0x00040000 187e080313cSDave Liu #define SICRH_TSEC2_F 0x00020000 188e080313cSDave Liu #define SICRH_TSEC2_G 0x00010000 189e080313cSDave Liu #define SICRH_TSEC2_H 0x00008000 190e080313cSDave Liu #define SICRH_GPIO2_A 0x00004000 191e080313cSDave Liu #define SICRH_GPIO2_B 0x00002000 192e080313cSDave Liu #define SICRH_GPIO2_C 0x00001000 193e080313cSDave Liu #define SICRH_GPIO2_D 0x00000800 194e080313cSDave Liu #define SICRH_GPIO2_E 0x00000400 195e080313cSDave Liu #define SICRH_GPIO2_F 0x00000200 196e080313cSDave Liu #define SICRH_GPIO2_G 0x00000180 197e080313cSDave Liu #define SICRH_GPIO2_H 0x00000060 198e080313cSDave Liu #define SICRH_TSOBI1 0x00000002 199e080313cSDave Liu #define SICRH_TSOBI2 0x00000001 200e080313cSDave Liu 201e080313cSDave Liu #elif defined(CONFIG_MPC8360) 202e080313cSDave Liu /* SICRL bits - MPC8360 specific */ 203e080313cSDave Liu #define SICRL_LDP_A 0xC0000000 204e080313cSDave Liu #define SICRL_LCLK_1 0x10000000 205e080313cSDave Liu #define SICRL_LCLK_2 0x08000000 206e080313cSDave Liu #define SICRL_SRCID_A 0x03000000 207e080313cSDave Liu #define SICRL_IRQ_CKSTP_A 0x00C00000 208e080313cSDave Liu 209e080313cSDave Liu /* SICRH bits - MPC8360 specific */ 210e080313cSDave Liu #define SICRH_DDR 0x80000000 211e080313cSDave Liu #define SICRH_SECONDARY_DDR 0x40000000 212e080313cSDave Liu #define SICRH_SDDROE 0x20000000 213e080313cSDave Liu #define SICRH_IRQ3 0x10000000 214e080313cSDave Liu #define SICRH_UC1EOBI 0x00000004 215e080313cSDave Liu #define SICRH_UC2E1OBI 0x00000002 216e080313cSDave Liu #define SICRH_UC2E2OBI 0x00000001 21724c3aca3SDave Liu 2182c7920afSPeter Tyser #elif defined(CONFIG_MPC832x) 2192c7920afSPeter Tyser /* SICRL bits - MPC832x specific */ 22024c3aca3SDave Liu #define SICRL_LDP_LCS_A 0x80000000 22124c3aca3SDave Liu #define SICRL_IRQ_CKS 0x20000000 22224c3aca3SDave Liu #define SICRL_PCI_MSRC 0x10000000 22324c3aca3SDave Liu #define SICRL_URT_CTPR 0x06000000 22424c3aca3SDave Liu #define SICRL_IRQ_CTPR 0x00C00000 225d87c57b2SScott Wood 226555da617SDave Liu #elif defined(CONFIG_MPC8313) 227555da617SDave Liu /* SICRL bits - MPC8313 specific */ 228d87c57b2SScott Wood #define SICRL_LBC 0x30000000 229d87c57b2SScott Wood #define SICRL_UART 0x0C000000 230d87c57b2SScott Wood #define SICRL_SPI_A 0x03000000 231d87c57b2SScott Wood #define SICRL_SPI_B 0x00C00000 232d87c57b2SScott Wood #define SICRL_SPI_C 0x00300000 233d87c57b2SScott Wood #define SICRL_SPI_D 0x000C0000 234f986325dSRon Madrid #define SICRL_USBDR_11 0x00000C00 235f986325dSRon Madrid #define SICRL_USBDR_10 0x00000800 236f986325dSRon Madrid #define SICRL_USBDR_01 0x00000400 237f986325dSRon Madrid #define SICRL_USBDR_00 0x00000000 238d87c57b2SScott Wood #define SICRL_ETSEC1_A 0x0000000C 239d87c57b2SScott Wood #define SICRL_ETSEC2_A 0x00000003 240d87c57b2SScott Wood 241555da617SDave Liu /* SICRH bits - MPC8313 specific */ 242d87c57b2SScott Wood #define SICRH_INTR_A 0x02000000 243d87c57b2SScott Wood #define SICRH_INTR_B 0x00C00000 244d87c57b2SScott Wood #define SICRH_IIC 0x00300000 245d87c57b2SScott Wood #define SICRH_ETSEC2_B 0x000C0000 246d87c57b2SScott Wood #define SICRH_ETSEC2_C 0x00030000 247d87c57b2SScott Wood #define SICRH_ETSEC2_D 0x0000C000 248d87c57b2SScott Wood #define SICRH_ETSEC2_E 0x00003000 249d87c57b2SScott Wood #define SICRH_ETSEC2_F 0x00000C00 250d87c57b2SScott Wood #define SICRH_ETSEC2_G 0x00000300 251d87c57b2SScott Wood #define SICRH_ETSEC1_B 0x00000080 252d87c57b2SScott Wood #define SICRH_ETSEC1_C 0x00000060 253d87c57b2SScott Wood #define SICRH_GTX1_DLY 0x00000008 254d87c57b2SScott Wood #define SICRH_GTX2_DLY 0x00000004 255d87c57b2SScott Wood #define SICRH_TSOBI1 0x00000002 256d87c57b2SScott Wood #define SICRH_TSOBI2 0x00000001 257d87c57b2SScott Wood 258555da617SDave Liu #elif defined(CONFIG_MPC8315) 259555da617SDave Liu /* SICRL bits - MPC8315 specific */ 260555da617SDave Liu #define SICRL_DMA_CH0 0xc0000000 261555da617SDave Liu #define SICRL_DMA_SPI 0x30000000 262555da617SDave Liu #define SICRL_UART 0x0c000000 263555da617SDave Liu #define SICRL_IRQ4 0x02000000 264555da617SDave Liu #define SICRL_IRQ5 0x01800000 265555da617SDave Liu #define SICRL_IRQ6_7 0x00400000 266555da617SDave Liu #define SICRL_IIC1 0x00300000 267555da617SDave Liu #define SICRL_TDM 0x000c0000 268555da617SDave Liu #define SICRL_TDM_SHARED 0x00030000 269555da617SDave Liu #define SICRL_PCI_A 0x0000c000 270555da617SDave Liu #define SICRL_ELBC_A 0x00003000 271555da617SDave Liu #define SICRL_ETSEC1_A 0x000000c0 272555da617SDave Liu #define SICRL_ETSEC1_B 0x00000030 273555da617SDave Liu #define SICRL_ETSEC1_C 0x0000000c 274555da617SDave Liu #define SICRL_TSEXPOBI 0x00000001 275555da617SDave Liu 276555da617SDave Liu /* SICRH bits - MPC8315 specific */ 277555da617SDave Liu #define SICRH_GPIO_0 0xc0000000 278555da617SDave Liu #define SICRH_GPIO_1 0x30000000 279555da617SDave Liu #define SICRH_GPIO_2 0x0c000000 280555da617SDave Liu #define SICRH_GPIO_3 0x03000000 281555da617SDave Liu #define SICRH_GPIO_4 0x00c00000 282555da617SDave Liu #define SICRH_GPIO_5 0x00300000 283555da617SDave Liu #define SICRH_GPIO_6 0x000c0000 284555da617SDave Liu #define SICRH_GPIO_7 0x00030000 285555da617SDave Liu #define SICRH_GPIO_8 0x0000c000 286555da617SDave Liu #define SICRH_GPIO_9 0x00003000 287555da617SDave Liu #define SICRH_GPIO_10 0x00000c00 288555da617SDave Liu #define SICRH_GPIO_11 0x00000300 289555da617SDave Liu #define SICRH_ETSEC2_A 0x000000c0 290555da617SDave Liu #define SICRH_TSOBI1 0x00000002 291555da617SDave Liu #define SICRH_TSOBI2 0x00000001 292555da617SDave Liu 2932c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 29403051c3dSDave Liu /* SICRL bits - MPC837x specific */ 29503051c3dSDave Liu #define SICRL_USB_A 0xC0000000 29603051c3dSDave Liu #define SICRL_USB_B 0x30000000 297e1ac387fSAndy Fleming #define SICRL_USB_B_SD 0x20000000 29803051c3dSDave Liu #define SICRL_UART 0x0C000000 29903051c3dSDave Liu #define SICRL_GPIO_A 0x02000000 30003051c3dSDave Liu #define SICRL_GPIO_B 0x01000000 30103051c3dSDave Liu #define SICRL_GPIO_C 0x00800000 30203051c3dSDave Liu #define SICRL_GPIO_D 0x00400000 30303051c3dSDave Liu #define SICRL_GPIO_E 0x00200000 30403051c3dSDave Liu #define SICRL_GPIO_F 0x00180000 30503051c3dSDave Liu #define SICRL_GPIO_G 0x00040000 30603051c3dSDave Liu #define SICRL_GPIO_H 0x00020000 30703051c3dSDave Liu #define SICRL_GPIO_I 0x00010000 30803051c3dSDave Liu #define SICRL_GPIO_J 0x00008000 30903051c3dSDave Liu #define SICRL_GPIO_K 0x00004000 31003051c3dSDave Liu #define SICRL_GPIO_L 0x00003000 31103051c3dSDave Liu #define SICRL_DMA_A 0x00000800 31203051c3dSDave Liu #define SICRL_DMA_B 0x00000400 31303051c3dSDave Liu #define SICRL_DMA_C 0x00000200 31403051c3dSDave Liu #define SICRL_DMA_D 0x00000100 31503051c3dSDave Liu #define SICRL_DMA_E 0x00000080 31603051c3dSDave Liu #define SICRL_DMA_F 0x00000040 31703051c3dSDave Liu #define SICRL_DMA_G 0x00000020 31803051c3dSDave Liu #define SICRL_DMA_H 0x00000010 31903051c3dSDave Liu #define SICRL_DMA_I 0x00000008 32003051c3dSDave Liu #define SICRL_DMA_J 0x00000004 32103051c3dSDave Liu #define SICRL_LDP_A 0x00000002 32203051c3dSDave Liu #define SICRL_LDP_B 0x00000001 32303051c3dSDave Liu 32403051c3dSDave Liu /* SICRH bits - MPC837x specific */ 32503051c3dSDave Liu #define SICRH_DDR 0x80000000 32603051c3dSDave Liu #define SICRH_TSEC1_A 0x10000000 32703051c3dSDave Liu #define SICRH_TSEC1_B 0x08000000 32803051c3dSDave Liu #define SICRH_TSEC2_A 0x00400000 32903051c3dSDave Liu #define SICRH_TSEC2_B 0x00200000 33003051c3dSDave Liu #define SICRH_TSEC2_C 0x00100000 33103051c3dSDave Liu #define SICRH_TSEC2_D 0x00080000 33203051c3dSDave Liu #define SICRH_TSEC2_E 0x00040000 33303051c3dSDave Liu #define SICRH_TMR 0x00010000 33403051c3dSDave Liu #define SICRH_GPIO2_A 0x00008000 33503051c3dSDave Liu #define SICRH_GPIO2_B 0x00004000 33603051c3dSDave Liu #define SICRH_GPIO2_C 0x00002000 33703051c3dSDave Liu #define SICRH_GPIO2_D 0x00001000 33803051c3dSDave Liu #define SICRH_GPIO2_E 0x00000C00 339e1ac387fSAndy Fleming #define SICRH_GPIO2_E_SD 0x00000800 34003051c3dSDave Liu #define SICRH_GPIO2_F 0x00000300 34103051c3dSDave Liu #define SICRH_GPIO2_G 0x000000C0 34203051c3dSDave Liu #define SICRH_GPIO2_H 0x00000030 34303051c3dSDave Liu #define SICRH_SPI 0x00000003 344e1ac387fSAndy Fleming #define SICRH_SPI_SD 0x00000001 345f3ce250dSIlya Yanok 346f3ce250dSIlya Yanok #elif defined(CONFIG_MPC8308) 347f3ce250dSIlya Yanok /* SICRL bits - MPC8308 specific */ 348f3ce250dSIlya Yanok #define SICRL_SPI_PF0 (0 << 28) 349f3ce250dSIlya Yanok #define SICRL_SPI_PF1 (1 << 28) 350f3ce250dSIlya Yanok #define SICRL_SPI_PF3 (3 << 28) 351f3ce250dSIlya Yanok #define SICRL_UART_PF0 (0 << 26) 352f3ce250dSIlya Yanok #define SICRL_UART_PF1 (1 << 26) 353f3ce250dSIlya Yanok #define SICRL_UART_PF3 (3 << 26) 354f3ce250dSIlya Yanok #define SICRL_IRQ_PF0 (0 << 24) 355f3ce250dSIlya Yanok #define SICRL_IRQ_PF1 (1 << 24) 356f3ce250dSIlya Yanok #define SICRL_I2C2_PF0 (0 << 20) 357f3ce250dSIlya Yanok #define SICRL_I2C2_PF1 (1 << 20) 358f3ce250dSIlya Yanok #define SICRL_ETSEC1_TX_CLK (0 << 6) 359f3ce250dSIlya Yanok #define SICRL_ETSEC1_GTX_CLK125 (1 << 6) 360f3ce250dSIlya Yanok 361f3ce250dSIlya Yanok /* SICRH bits - MPC8308 specific */ 362f3ce250dSIlya Yanok #define SICRH_ESDHC_A_SD (0 << 30) 363f3ce250dSIlya Yanok #define SICRH_ESDHC_A_GTM (1 << 30) 364f3ce250dSIlya Yanok #define SICRH_ESDHC_A_GPIO (3 << 30) 365f3ce250dSIlya Yanok #define SICRH_ESDHC_B_SD (0 << 28) 366f3ce250dSIlya Yanok #define SICRH_ESDHC_B_GTM (1 << 28) 367f3ce250dSIlya Yanok #define SICRH_ESDHC_B_GPIO (3 << 28) 368f3ce250dSIlya Yanok #define SICRH_ESDHC_C_SD (0 << 26) 369f3ce250dSIlya Yanok #define SICRH_ESDHC_C_GTM (1 << 26) 370f3ce250dSIlya Yanok #define SICRH_ESDHC_C_GPIO (3 << 26) 371f3ce250dSIlya Yanok #define SICRH_GPIO_A_GPIO (0 << 24) 372f3ce250dSIlya Yanok #define SICRH_GPIO_A_TSEC2 (1 << 24) 373f3ce250dSIlya Yanok #define SICRH_GPIO_B_GPIO (0 << 22) 374f3ce250dSIlya Yanok #define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22) 375f3ce250dSIlya Yanok #define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22) 376f3ce250dSIlya Yanok #define SICRH_IEEE1588_A_TMR (1 << 20) 377f3ce250dSIlya Yanok #define SICRH_IEEE1588_A_GPIO (3 << 20) 378f3ce250dSIlya Yanok #define SICRH_USB (1 << 18) 379f3ce250dSIlya Yanok #define SICRH_GTM_GTM (1 << 16) 380f3ce250dSIlya Yanok #define SICRH_GTM_GPIO (3 << 16) 381f3ce250dSIlya Yanok #define SICRH_IEEE1588_B_TMR (1 << 14) 382f3ce250dSIlya Yanok #define SICRH_IEEE1588_B_GPIO (3 << 14) 383f3ce250dSIlya Yanok #define SICRH_ETSEC2_CRS (1 << 12) 384f3ce250dSIlya Yanok #define SICRH_ETSEC2_GPIO (3 << 12) 385f3ce250dSIlya Yanok #define SICRH_GPIOSEL_0 (0 << 8) 386f3ce250dSIlya Yanok #define SICRH_GPIOSEL_1 (1 << 8) 387f3ce250dSIlya Yanok #define SICRH_TMROBI_V3P3 (0 << 4) 388f3ce250dSIlya Yanok #define SICRH_TMROBI_V2P5 (1 << 4) 389f3ce250dSIlya Yanok #define SICRH_TSOBI1_V3P3 (0 << 1) 390f3ce250dSIlya Yanok #define SICRH_TSOBI1_V2P5 (1 << 1) 391f3ce250dSIlya Yanok #define SICRH_TSOBI2_V3P3 (0 << 0) 392f3ce250dSIlya Yanok #define SICRH_TSOBI2_V2P5 (1 << 0) 393*a88731a6SGerlando Falauto 394*a88731a6SGerlando Falauto #elif defined(CONFIG_MPC8309) 395*a88731a6SGerlando Falauto /* SICR_1 */ 396*a88731a6SGerlando Falauto #define SICR_1_UART1_UART1S (0 << (30-2)) 397*a88731a6SGerlando Falauto #define SICR_1_UART1_UART1RTS (1 << (30-2)) 398*a88731a6SGerlando Falauto #define SICR_1_I2C_I2C (0 << (30-4)) 399*a88731a6SGerlando Falauto #define SICR_1_I2C_CKSTOP (1 << (30-4)) 400*a88731a6SGerlando Falauto #define SICR_1_IRQ_A_IRQ (0 << (30-6)) 401*a88731a6SGerlando Falauto #define SICR_1_IRQ_A_MCP (1 << (30-6)) 402*a88731a6SGerlando Falauto #define SICR_1_IRQ_B_IRQ (0 << (30-8)) 403*a88731a6SGerlando Falauto #define SICR_1_IRQ_B_CKSTOP (1 << (30-8)) 404*a88731a6SGerlando Falauto #define SICR_1_GPIO_A_GPIO (0 << (30-10)) 405*a88731a6SGerlando Falauto #define SICR_1_GPIO_A_SD (2 << (30-10)) 406*a88731a6SGerlando Falauto #define SICR_1_GPIO_A_DDR (3 << (30-10)) 407*a88731a6SGerlando Falauto #define SICR_1_GPIO_B_GPIO (0 << (30-12)) 408*a88731a6SGerlando Falauto #define SICR_1_GPIO_B_SD (2 << (30-12)) 409*a88731a6SGerlando Falauto #define SICR_1_GPIO_B_QE (3 << (30-12)) 410*a88731a6SGerlando Falauto #define SICR_1_GPIO_C_GPIO (0 << (30-14)) 411*a88731a6SGerlando Falauto #define SICR_1_GPIO_C_CAN (1 << (30-14)) 412*a88731a6SGerlando Falauto #define SICR_1_GPIO_C_DDR (2 << (30-14)) 413*a88731a6SGerlando Falauto #define SICR_1_GPIO_C_LCS (3 << (30-14)) 414*a88731a6SGerlando Falauto #define SICR_1_GPIO_D_GPIO (0 << (30-16)) 415*a88731a6SGerlando Falauto #define SICR_1_GPIO_D_CAN (1 << (30-16)) 416*a88731a6SGerlando Falauto #define SICR_1_GPIO_D_DDR (2 << (30-16)) 417*a88731a6SGerlando Falauto #define SICR_1_GPIO_D_LCS (3 << (30-16)) 418*a88731a6SGerlando Falauto #define SICR_1_GPIO_E_GPIO (0 << (30-18)) 419*a88731a6SGerlando Falauto #define SICR_1_GPIO_E_CAN (1 << (30-18)) 420*a88731a6SGerlando Falauto #define SICR_1_GPIO_E_DDR (2 << (30-18)) 421*a88731a6SGerlando Falauto #define SICR_1_GPIO_E_LCS (3 << (30-18)) 422*a88731a6SGerlando Falauto #define SICR_1_GPIO_F_GPIO (0 << (30-20)) 423*a88731a6SGerlando Falauto #define SICR_1_GPIO_F_CAN (1 << (30-20)) 424*a88731a6SGerlando Falauto #define SICR_1_GPIO_F_CK (2 << (30-20)) 425*a88731a6SGerlando Falauto #define SICR_1_USB_A_USBDR (0 << (30-22)) 426*a88731a6SGerlando Falauto #define SICR_1_USB_A_UART2S (1 << (30-22)) 427*a88731a6SGerlando Falauto #define SICR_1_USB_B_USBDR (0 << (30-24)) 428*a88731a6SGerlando Falauto #define SICR_1_USB_B_UART2S (1 << (30-24)) 429*a88731a6SGerlando Falauto #define SICR_1_USB_B_UART2RTS (2 << (30-24)) 430*a88731a6SGerlando Falauto #define SICR_1_USB_C_USBDR (0 << (30-26)) 431*a88731a6SGerlando Falauto #define SICR_1_USB_C_QE_EXT (3 << (30-26)) 432*a88731a6SGerlando Falauto #define SICR_1_FEC1_FEC1 (0 << (30-28)) 433*a88731a6SGerlando Falauto #define SICR_1_FEC1_GTM (1 << (30-28)) 434*a88731a6SGerlando Falauto #define SICR_1_FEC1_GPIO (2 << (30-28)) 435*a88731a6SGerlando Falauto #define SICR_1_FEC2_FEC2 (0 << (30-30)) 436*a88731a6SGerlando Falauto #define SICR_1_FEC2_GTM (1 << (30-30)) 437*a88731a6SGerlando Falauto #define SICR_1_FEC2_GPIO (2 << (30-30)) 438*a88731a6SGerlando Falauto /* SICR_2 */ 439*a88731a6SGerlando Falauto #define SICR_2_FEC3_FEC3 (0 << (30-0)) 440*a88731a6SGerlando Falauto #define SICR_2_FEC3_TMR (1 << (30-0)) 441*a88731a6SGerlando Falauto #define SICR_2_FEC3_GPIO (2 << (30-0)) 442*a88731a6SGerlando Falauto #define SICR_2_HDLC1_A_HDLC1 (0 << (30-2)) 443*a88731a6SGerlando Falauto #define SICR_2_HDLC1_A_GPIO (1 << (30-2)) 444*a88731a6SGerlando Falauto #define SICR_2_HDLC1_A_TDM1 (2 << (30-2)) 445*a88731a6SGerlando Falauto #define SICR_2_ELBC_A_LA (0 << (30-4)) 446*a88731a6SGerlando Falauto #define SICR_2_ELBC_B_LCLK (0 << (30-6)) 447*a88731a6SGerlando Falauto #define SICR_2_HDLC2_A_HDLC2 (0 << (30-8)) 448*a88731a6SGerlando Falauto #define SICR_2_HDLC2_A_GPIO (0 << (30-8)) 449*a88731a6SGerlando Falauto #define SICR_2_HDLC2_A_TDM2 (0 << (30-8)) 450*a88731a6SGerlando Falauto /* bits 10-11 unused */ 451*a88731a6SGerlando Falauto #define SICR_2_USB_D_USBDR (0 << (30-12)) 452*a88731a6SGerlando Falauto #define SICR_2_USB_D_GPIO (2 << (30-12)) 453*a88731a6SGerlando Falauto #define SICR_2_USB_D_QE_BRG (3 << (30-12)) 454*a88731a6SGerlando Falauto #define SICR_2_PCI_PCI (0 << (30-14)) 455*a88731a6SGerlando Falauto #define SICR_2_PCI_CPCI_HS (2 << (30-14)) 456*a88731a6SGerlando Falauto #define SICR_2_HDLC1_B_HDLC1 (0 << (30-16)) 457*a88731a6SGerlando Falauto #define SICR_2_HDLC1_B_GPIO (1 << (30-16)) 458*a88731a6SGerlando Falauto #define SICR_2_HDLC1_B_QE_BRG (2 << (30-16)) 459*a88731a6SGerlando Falauto #define SICR_2_HDLC1_B_TDM1 (3 << (30-16)) 460*a88731a6SGerlando Falauto #define SICR_2_HDLC1_C_HDLC1 (0 << (30-18)) 461*a88731a6SGerlando Falauto #define SICR_2_HDLC1_C_GPIO (1 << (30-18)) 462*a88731a6SGerlando Falauto #define SICR_2_HDLC1_C_TDM1 (2 << (30-18)) 463*a88731a6SGerlando Falauto #define SICR_2_HDLC2_B_HDLC2 (0 << (30-20)) 464*a88731a6SGerlando Falauto #define SICR_2_HDLC2_B_GPIO (1 << (30-20)) 465*a88731a6SGerlando Falauto #define SICR_2_HDLC2_B_QE_BRG (2 << (30-20)) 466*a88731a6SGerlando Falauto #define SICR_2_HDLC2_B_TDM2 (3 << (30-20)) 467*a88731a6SGerlando Falauto #define SICR_2_HDLC2_C_HDLC2 (0 << (30-22)) 468*a88731a6SGerlando Falauto #define SICR_2_HDLC2_C_GPIO (1 << (30-22)) 469*a88731a6SGerlando Falauto #define SICR_2_HDLC2_C_TDM2 (2 << (30-22)) 470*a88731a6SGerlando Falauto #define SICR_2_HDLC2_C_QE_BRG (3 << (30-22)) 471*a88731a6SGerlando Falauto #define SICR_2_QUIESCE_B (0 << (30-24)) 472*a88731a6SGerlando Falauto 473e080313cSDave Liu #endif 474e080313cSDave Liu 4754e8b750cSHeiko Schocher /* 4764e8b750cSHeiko Schocher * SWCRR - System Watchdog Control Register 477e080313cSDave Liu */ 4784e8b750cSHeiko Schocher /* Register offset to immr */ 4794e8b750cSHeiko Schocher #define SWCRR 0x0204 4804e8b750cSHeiko Schocher /* Software Watchdog Time Count */ 4814e8b750cSHeiko Schocher #define SWCRR_SWTC 0xFFFF0000 4824e8b750cSHeiko Schocher /* Watchdog Enable bit */ 4834e8b750cSHeiko Schocher #define SWCRR_SWEN 0x00000004 4844e8b750cSHeiko Schocher /* Software Watchdog Reset/Interrupt Select bit */ 4854e8b750cSHeiko Schocher #define SWCRR_SWRI 0x00000002 4864e8b750cSHeiko Schocher /* Software Watchdog Counter Prescale bit */ 4874e8b750cSHeiko Schocher #define SWCRR_SWPR 0x00000001 4884e8b750cSHeiko Schocher #define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \ 4894e8b750cSHeiko Schocher SWCRR_SWRI | SWCRR_SWPR)) 490e080313cSDave Liu 4914e8b750cSHeiko Schocher /* 4924e8b750cSHeiko Schocher * SWCNR - System Watchdog Counter Register 493e080313cSDave Liu */ 4944e8b750cSHeiko Schocher /* Register offset to immr */ 4954e8b750cSHeiko Schocher #define SWCNR 0x0208 4964e8b750cSHeiko Schocher /* Software Watchdog Count mask */ 4974e8b750cSHeiko Schocher #define SWCNR_SWCN 0x0000FFFF 498e080313cSDave Liu #define SWCNR_RES ~(SWCNR_SWCN) 499e080313cSDave Liu 5004e8b750cSHeiko Schocher /* 5014e8b750cSHeiko Schocher * SWSRR - System Watchdog Service Register 502e080313cSDave Liu */ 5034e8b750cSHeiko Schocher /* Register offset to immr */ 5044e8b750cSHeiko Schocher #define SWSRR 0x020E 505e080313cSDave Liu 5064e8b750cSHeiko Schocher /* 5074e8b750cSHeiko Schocher * ACR - Arbiter Configuration Register 508e080313cSDave Liu */ 509e080313cSDave Liu #define ACR_COREDIS 0x10000000 /* Core disable */ 510e080313cSDave Liu #define ACR_COREDIS_SHIFT (31-7) 511e080313cSDave Liu #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 512e080313cSDave Liu #define ACR_PIPE_DEP_SHIFT (31-15) 513e080313cSDave Liu #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 514e080313cSDave Liu #define ACR_PCI_RPTCNT_SHIFT (31-19) 515e080313cSDave Liu #define ACR_RPTCNT 0x00000700 /* Repeat count */ 516e080313cSDave Liu #define ACR_RPTCNT_SHIFT (31-23) 517e080313cSDave Liu #define ACR_APARK 0x00000030 /* Address parking */ 518e080313cSDave Liu #define ACR_APARK_SHIFT (31-27) 519e080313cSDave Liu #define ACR_PARKM 0x0000000F /* Parking master */ 520e080313cSDave Liu #define ACR_PARKM_SHIFT (31-31) 521e080313cSDave Liu 5224e8b750cSHeiko Schocher /* 5234e8b750cSHeiko Schocher * ATR - Arbiter Timers Register 524e080313cSDave Liu */ 525e080313cSDave Liu #define ATR_DTO 0x00FF0000 /* Data time out */ 526002d27caSNick Spence #define ATR_DTO_SHIFT 16 527e080313cSDave Liu #define ATR_ATO 0x000000FF /* Address time out */ 528002d27caSNick Spence #define ATR_ATO_SHIFT 0 529e080313cSDave Liu 5304e8b750cSHeiko Schocher /* 5314e8b750cSHeiko Schocher * AER - Arbiter Event Register 532e080313cSDave Liu */ 533e080313cSDave Liu #define AER_ETEA 0x00000020 /* Transfer error */ 5344e8b750cSHeiko Schocher /* Reserved transfer type */ 5354e8b750cSHeiko Schocher #define AER_RES 0x00000010 5364e8b750cSHeiko Schocher /* External control word transfer type */ 5374e8b750cSHeiko Schocher #define AER_ECW 0x00000008 5384e8b750cSHeiko Schocher /* Address Only transfer type */ 5394e8b750cSHeiko Schocher #define AER_AO 0x00000004 540e080313cSDave Liu #define AER_DTO 0x00000002 /* Data time out */ 541e080313cSDave Liu #define AER_ATO 0x00000001 /* Address time out */ 542e080313cSDave Liu 5434e8b750cSHeiko Schocher /* 5444e8b750cSHeiko Schocher * AEATR - Arbiter Event Address Register 545e080313cSDave Liu */ 546e080313cSDave Liu #define AEATR_EVENT 0x07000000 /* Event type */ 547002d27caSNick Spence #define AEATR_EVENT_SHIFT 24 548e080313cSDave Liu #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 549002d27caSNick Spence #define AEATR_MSTR_ID_SHIFT 16 550e080313cSDave Liu #define AEATR_TBST 0x00000800 /* Transfer burst */ 551002d27caSNick Spence #define AEATR_TBST_SHIFT 11 552e080313cSDave Liu #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 553002d27caSNick Spence #define AEATR_TSIZE_SHIFT 8 554e080313cSDave Liu #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 555002d27caSNick Spence #define AEATR_TTYPE_SHIFT 0 556e080313cSDave Liu 5574e8b750cSHeiko Schocher /* 5584e8b750cSHeiko Schocher * HRCWL - Hard Reset Configuration Word Low 559e080313cSDave Liu */ 560e080313cSDave Liu #define HRCWL_LBIUCM 0x80000000 561e080313cSDave Liu #define HRCWL_LBIUCM_SHIFT 31 562e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 563e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 564e080313cSDave Liu 565e080313cSDave Liu #define HRCWL_DDRCM 0x40000000 566e080313cSDave Liu #define HRCWL_DDRCM_SHIFT 30 567e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 568e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 569e080313cSDave Liu 570e080313cSDave Liu #define HRCWL_SPMF 0x0f000000 571e080313cSDave Liu #define HRCWL_SPMF_SHIFT 24 572e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 573e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 574e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 575e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 576e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 577e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 578e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 579e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 580e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 581e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 582e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 583e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 584e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 585e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 586e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 587e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 588e080313cSDave Liu 589e080313cSDave Liu #define HRCWL_VCO_BYPASS 0x00000000 590e080313cSDave Liu #define HRCWL_VCO_1X2 0x00000000 591e080313cSDave Liu #define HRCWL_VCO_1X4 0x00200000 592e080313cSDave Liu #define HRCWL_VCO_1X8 0x00400000 593e080313cSDave Liu 594e080313cSDave Liu #define HRCWL_COREPLL 0x007F0000 595e080313cSDave Liu #define HRCWL_COREPLL_SHIFT 16 596e080313cSDave Liu #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 597e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1X1 0x00020000 598e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 599e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2X1 0x00040000 600e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 601e080313cSDave Liu #define HRCWL_CORE_TO_CSB_3X1 0x00060000 602e080313cSDave Liu 6032c7920afSPeter Tyser #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 604e080313cSDave Liu #define HRCWL_CEVCOD 0x000000C0 605e080313cSDave Liu #define HRCWL_CEVCOD_SHIFT 6 606e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 607e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 608e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 609e080313cSDave Liu 610e080313cSDave Liu #define HRCWL_CEPDF 0x00000020 611e080313cSDave Liu #define HRCWL_CEPDF_SHIFT 5 612e080313cSDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 613e080313cSDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 614e080313cSDave Liu 615e080313cSDave Liu #define HRCWL_CEPMF 0x0000001F 616e080313cSDave Liu #define HRCWL_CEPMF_SHIFT 0 617e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 618e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 619e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 620e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 621e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 622e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 623e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 624e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 625e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 626e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 627e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 628e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 629e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 630e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 631e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 632e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 633e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 634e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 635e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 636e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 637e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 638e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 639e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 640e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 641e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 642e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 643e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 644e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 645e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 646e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 647e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 64803051c3dSDave Liu 6497c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 6506f3931a2SDave Liu #define HRCWL_SVCOD 0x30000000 6516f3931a2SDave Liu #define HRCWL_SVCOD_SHIFT 28 6526f3931a2SDave Liu #define HRCWL_SVCOD_DIV_2 0x00000000 6536f3931a2SDave Liu #define HRCWL_SVCOD_DIV_4 0x10000000 6546f3931a2SDave Liu #define HRCWL_SVCOD_DIV_8 0x20000000 6556f3931a2SDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 6566f3931a2SDave Liu 6572c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 65803051c3dSDave Liu #define HRCWL_SVCOD 0x30000000 65903051c3dSDave Liu #define HRCWL_SVCOD_SHIFT 28 66003051c3dSDave Liu #define HRCWL_SVCOD_DIV_4 0x00000000 66103051c3dSDave Liu #define HRCWL_SVCOD_DIV_8 0x10000000 66203051c3dSDave Liu #define HRCWL_SVCOD_DIV_2 0x20000000 66303051c3dSDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 664*a88731a6SGerlando Falauto #elif defined(CONFIG_MPC8309) 665*a88731a6SGerlando Falauto 666*a88731a6SGerlando Falauto #define HRCWL_CEVCOD 0x000000C0 667*a88731a6SGerlando Falauto #define HRCWL_CEVCOD_SHIFT 6 668*a88731a6SGerlando Falauto /* 669*a88731a6SGerlando Falauto * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012 670*a88731a6SGerlando Falauto * these are different than with 8360, 832x 671*a88731a6SGerlando Falauto */ 672*a88731a6SGerlando Falauto #define HRCWL_CE_PLL_VCO_DIV_2 0x00000000 673*a88731a6SGerlando Falauto #define HRCWL_CE_PLL_VCO_DIV_4 0x00000040 674*a88731a6SGerlando Falauto #define HRCWL_CE_PLL_VCO_DIV_8 0x00000080 675*a88731a6SGerlando Falauto 676*a88731a6SGerlando Falauto #define HRCWL_CEPDF 0x00000020 677*a88731a6SGerlando Falauto #define HRCWL_CEPDF_SHIFT 5 678*a88731a6SGerlando Falauto #define HRCWL_CE_PLL_DIV_1X1 0x00000000 679*a88731a6SGerlando Falauto #define HRCWL_CE_PLL_DIV_2X1 0x00000020 680*a88731a6SGerlando Falauto 681*a88731a6SGerlando Falauto #define HRCWL_CEPMF 0x0000001F 682*a88731a6SGerlando Falauto #define HRCWL_CEPMF_SHIFT 0 683*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 684*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X2 0x00000002 685*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X3 0x00000003 686*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X4 0x00000004 687*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X5 0x00000005 688*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X6 0x00000006 689*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X7 0x00000007 690*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X8 0x00000008 691*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X9 0x00000009 692*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X10 0x0000000A 693*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X11 0x0000000B 694*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X12 0x0000000C 695*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X13 0x0000000D 696*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X14 0x0000000E 697*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X15 0x0000000F 698*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X16 0x00000010 699*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X17 0x00000011 700*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X18 0x00000012 701*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X19 0x00000013 702*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X20 0x00000014 703*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X21 0x00000015 704*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X22 0x00000016 705*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X23 0x00000017 706*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X24 0x00000018 707*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X25 0x00000019 708*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X26 0x0000001A 709*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X27 0x0000001B 710*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X28 0x0000001C 711*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X29 0x0000001D 712*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X30 0x0000001E 713*a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X31 0x0000001F 714*a88731a6SGerlando Falauto 715*a88731a6SGerlando Falauto #define HRCWL_SVCOD 0x30000000 716*a88731a6SGerlando Falauto #define HRCWL_SVCOD_SHIFT 28 717*a88731a6SGerlando Falauto #define HRCWL_SVCOD_DIV_2 0x00000000 718*a88731a6SGerlando Falauto #define HRCWL_SVCOD_DIV_4 0x10000000 719*a88731a6SGerlando Falauto #define HRCWL_SVCOD_DIV_8 0x20000000 720*a88731a6SGerlando Falauto #define HRCWL_SVCOD_DIV_1 0x30000000 721e080313cSDave Liu #endif 722e080313cSDave Liu 7234e8b750cSHeiko Schocher /* 7244e8b750cSHeiko Schocher * HRCWH - Hardware Reset Configuration Word High 725e080313cSDave Liu */ 726e080313cSDave Liu #define HRCWH_PCI_HOST 0x80000000 727e080313cSDave Liu #define HRCWH_PCI_HOST_SHIFT 31 728e080313cSDave Liu #define HRCWH_PCI_AGENT 0x00000000 729e080313cSDave Liu 7302c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 731e080313cSDave Liu #define HRCWH_32_BIT_PCI 0x00000000 732e080313cSDave Liu #define HRCWH_64_BIT_PCI 0x40000000 733e080313cSDave Liu #endif 734e080313cSDave Liu 735e080313cSDave Liu #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 736e080313cSDave Liu #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 737e080313cSDave Liu 738e080313cSDave Liu #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 739e080313cSDave Liu #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 740e080313cSDave Liu 7412c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 742e080313cSDave Liu #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 743e080313cSDave Liu #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 744e080313cSDave Liu 745e080313cSDave Liu #elif defined(CONFIG_MPC8360) 746e080313cSDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 747e080313cSDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 748e080313cSDave Liu #endif 749e080313cSDave Liu 750e080313cSDave Liu #define HRCWH_CORE_DISABLE 0x08000000 751e080313cSDave Liu #define HRCWH_CORE_ENABLE 0x00000000 752e080313cSDave Liu 753e080313cSDave Liu #define HRCWH_FROM_0X00000100 0x00000000 754e080313cSDave Liu #define HRCWH_FROM_0XFFF00100 0x04000000 755e080313cSDave Liu 756e080313cSDave Liu #define HRCWH_BOOTSEQ_DISABLE 0x00000000 757e080313cSDave Liu #define HRCWH_BOOTSEQ_NORMAL 0x01000000 758e080313cSDave Liu #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 759e080313cSDave Liu 760e080313cSDave Liu #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 761e080313cSDave Liu #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 762e080313cSDave Liu 763e080313cSDave Liu #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 764e080313cSDave Liu #define HRCWH_ROM_LOC_PCI1 0x00100000 7652c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 766e080313cSDave Liu #define HRCWH_ROM_LOC_PCI2 0x00200000 767e080313cSDave Liu #endif 7682c7920afSPeter Tyser #if defined(CONFIG_MPC837x) 76903051c3dSDave Liu #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 77003051c3dSDave Liu #endif 771e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 772e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 773e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 774e080313cSDave Liu 7757c619ddcSIlya Yanok #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 7767c619ddcSIlya Yanok defined(CONFIG_MPC837x) 777d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 778d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 779d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 780d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 781d87c57b2SScott Wood 782d87c57b2SScott Wood #define HRCWH_RL_EXT_LEGACY 0x00000000 783d87c57b2SScott Wood #define HRCWH_RL_EXT_NAND 0x00040000 784d87c57b2SScott Wood 785e6d9c891SAnton Vorontsov #define HRCWH_TSEC1M_MASK 0x0000E000 786d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_MII 0x00000000 787d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RMII 0x00002000 788d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RGMII 0x00006000 789d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 790d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 791d87c57b2SScott Wood 792e6d9c891SAnton Vorontsov #define HRCWH_TSEC2M_MASK 0x00001C00 793d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_MII 0x00000000 794d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RMII 0x00000400 795d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 796d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RTBI 0x00001400 797d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_SGMII 0x00001800 798d87c57b2SScott Wood #endif 799d87c57b2SScott Wood 8002c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 801e080313cSDave Liu #define HRCWH_TSEC1M_IN_RGMII 0x00000000 802e080313cSDave Liu #define HRCWH_TSEC1M_IN_RTBI 0x00004000 803e080313cSDave Liu #define HRCWH_TSEC1M_IN_GMII 0x00008000 804e080313cSDave Liu #define HRCWH_TSEC1M_IN_TBI 0x0000C000 805e080313cSDave Liu #define HRCWH_TSEC2M_IN_RGMII 0x00000000 806e080313cSDave Liu #define HRCWH_TSEC2M_IN_RTBI 0x00001000 807e080313cSDave Liu #define HRCWH_TSEC2M_IN_GMII 0x00002000 808e080313cSDave Liu #define HRCWH_TSEC2M_IN_TBI 0x00003000 809e080313cSDave Liu #endif 810e080313cSDave Liu 811e080313cSDave Liu #if defined(CONFIG_MPC8360) 812e080313cSDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 813e080313cSDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 814e080313cSDave Liu #endif 815e080313cSDave Liu 816e080313cSDave Liu #define HRCWH_BIG_ENDIAN 0x00000000 817e080313cSDave Liu #define HRCWH_LITTLE_ENDIAN 0x00000008 818e080313cSDave Liu 819e080313cSDave Liu #define HRCWH_LALE_NORMAL 0x00000000 820e080313cSDave Liu #define HRCWH_LALE_EARLY 0x00000004 821e080313cSDave Liu 822e080313cSDave Liu #define HRCWH_LDP_SET 0x00000000 823e080313cSDave Liu #define HRCWH_LDP_CLEAR 0x00000002 824e080313cSDave Liu 8254e8b750cSHeiko Schocher /* 8264e8b750cSHeiko Schocher * RSR - Reset Status Register 827e080313cSDave Liu */ 8287c619ddcSIlya Yanok #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 8297c619ddcSIlya Yanok defined(CONFIG_MPC837x) 83003051c3dSDave Liu #define RSR_RSTSRC 0xF0000000 /* Reset source */ 83103051c3dSDave Liu #define RSR_RSTSRC_SHIFT 28 83203051c3dSDave Liu #else 833e080313cSDave Liu #define RSR_RSTSRC 0xE0000000 /* Reset source */ 834e080313cSDave Liu #define RSR_RSTSRC_SHIFT 29 83503051c3dSDave Liu #endif 836e080313cSDave Liu #define RSR_BSF 0x00010000 /* Boot seq. fail */ 837e080313cSDave Liu #define RSR_BSF_SHIFT 16 8384e8b750cSHeiko Schocher /* software soft reset */ 8394e8b750cSHeiko Schocher #define RSR_SWSR 0x00002000 840e080313cSDave Liu #define RSR_SWSR_SHIFT 13 8414e8b750cSHeiko Schocher /* software hard reset */ 8424e8b750cSHeiko Schocher #define RSR_SWHR 0x00001000 843e080313cSDave Liu #define RSR_SWHR_SHIFT 12 844e080313cSDave Liu #define RSR_JHRS 0x00000200 /* jtag hreset */ 845e080313cSDave Liu #define RSR_JHRS_SHIFT 9 8464e8b750cSHeiko Schocher /* jtag sreset status */ 8474e8b750cSHeiko Schocher #define RSR_JSRS 0x00000100 848e080313cSDave Liu #define RSR_JSRS_SHIFT 8 8494e8b750cSHeiko Schocher /* checkstop reset status */ 8504e8b750cSHeiko Schocher #define RSR_CSHR 0x00000010 851e080313cSDave Liu #define RSR_CSHR_SHIFT 4 8524e8b750cSHeiko Schocher /* software watchdog reset status */ 8534e8b750cSHeiko Schocher #define RSR_SWRS 0x00000008 854e080313cSDave Liu #define RSR_SWRS_SHIFT 3 8554e8b750cSHeiko Schocher /* bus monitop reset status */ 8564e8b750cSHeiko Schocher #define RSR_BMRS 0x00000004 857e080313cSDave Liu #define RSR_BMRS_SHIFT 2 858e080313cSDave Liu #define RSR_SRS 0x00000002 /* soft reset status */ 859e080313cSDave Liu #define RSR_SRS_SHIFT 1 860e080313cSDave Liu #define RSR_HRS 0x00000001 /* hard reset status */ 861e080313cSDave Liu #define RSR_HRS_SHIFT 0 8624e8b750cSHeiko Schocher #define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \ 8634e8b750cSHeiko Schocher RSR_SWHR | RSR_JHRS | \ 8644e8b750cSHeiko Schocher RSR_JSRS | RSR_CSHR | \ 8654e8b750cSHeiko Schocher RSR_SWRS | RSR_BMRS | \ 8664e8b750cSHeiko Schocher RSR_SRS | RSR_HRS)) 8674e8b750cSHeiko Schocher /* 8684e8b750cSHeiko Schocher * RMR - Reset Mode Register 869e080313cSDave Liu */ 8704e8b750cSHeiko Schocher /* checkstop reset enable */ 8714e8b750cSHeiko Schocher #define RMR_CSRE 0x00000001 872e080313cSDave Liu #define RMR_CSRE_SHIFT 0 873e080313cSDave Liu #define RMR_RES ~(RMR_CSRE) 874e080313cSDave Liu 8754e8b750cSHeiko Schocher /* 8764e8b750cSHeiko Schocher * RCR - Reset Control Register 877e080313cSDave Liu */ 8784e8b750cSHeiko Schocher /* software hard reset */ 8794e8b750cSHeiko Schocher #define RCR_SWHR 0x00000002 8804e8b750cSHeiko Schocher /* software soft reset */ 8814e8b750cSHeiko Schocher #define RCR_SWSR 0x00000001 882e080313cSDave Liu #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 883e080313cSDave Liu 8844e8b750cSHeiko Schocher /* 8854e8b750cSHeiko Schocher * RCER - Reset Control Enable Register 886e080313cSDave Liu */ 8874e8b750cSHeiko Schocher /* software hard reset */ 8884e8b750cSHeiko Schocher #define RCER_CRE 0x00000001 889e080313cSDave Liu #define RCER_RES ~(RCER_CRE) 890e080313cSDave Liu 8914e8b750cSHeiko Schocher /* 8924e8b750cSHeiko Schocher * SPMR - System PLL Mode Register 893e080313cSDave Liu */ 894e080313cSDave Liu #define SPMR_LBIUCM 0x80000000 89526e5f794SJoakim Tjernlund #define SPMR_LBIUCM_SHIFT 31 896e080313cSDave Liu #define SPMR_DDRCM 0x40000000 89726e5f794SJoakim Tjernlund #define SPMR_DDRCM_SHIFT 30 898e080313cSDave Liu #define SPMR_SPMF 0x0F000000 89926e5f794SJoakim Tjernlund #define SPMR_SPMF_SHIFT 24 900e080313cSDave Liu #define SPMR_CKID 0x00800000 901e080313cSDave Liu #define SPMR_CKID_SHIFT 23 902e080313cSDave Liu #define SPMR_COREPLL 0x007F0000 90326e5f794SJoakim Tjernlund #define SPMR_COREPLL_SHIFT 16 904e080313cSDave Liu #define SPMR_CEVCOD 0x000000C0 90526e5f794SJoakim Tjernlund #define SPMR_CEVCOD_SHIFT 6 906e080313cSDave Liu #define SPMR_CEPDF 0x00000020 90726e5f794SJoakim Tjernlund #define SPMR_CEPDF_SHIFT 5 908e080313cSDave Liu #define SPMR_CEPMF 0x0000001F 90926e5f794SJoakim Tjernlund #define SPMR_CEPMF_SHIFT 0 910e080313cSDave Liu 9114e8b750cSHeiko Schocher /* 9124e8b750cSHeiko Schocher * OCCR - Output Clock Control Register 913e080313cSDave Liu */ 914e080313cSDave Liu #define OCCR_PCICOE0 0x80000000 915e080313cSDave Liu #define OCCR_PCICOE1 0x40000000 916e080313cSDave Liu #define OCCR_PCICOE2 0x20000000 917e080313cSDave Liu #define OCCR_PCICOE3 0x10000000 918e080313cSDave Liu #define OCCR_PCICOE4 0x08000000 919e080313cSDave Liu #define OCCR_PCICOE5 0x04000000 920e080313cSDave Liu #define OCCR_PCICOE6 0x02000000 921e080313cSDave Liu #define OCCR_PCICOE7 0x01000000 922e080313cSDave Liu #define OCCR_PCICD0 0x00800000 923e080313cSDave Liu #define OCCR_PCICD1 0x00400000 924e080313cSDave Liu #define OCCR_PCICD2 0x00200000 925e080313cSDave Liu #define OCCR_PCICD3 0x00100000 926e080313cSDave Liu #define OCCR_PCICD4 0x00080000 927e080313cSDave Liu #define OCCR_PCICD5 0x00040000 928e080313cSDave Liu #define OCCR_PCICD6 0x00020000 929e080313cSDave Liu #define OCCR_PCICD7 0x00010000 930e080313cSDave Liu #define OCCR_PCI1CR 0x00000002 931e080313cSDave Liu #define OCCR_PCI2CR 0x00000001 932e080313cSDave Liu #define OCCR_PCICR OCCR_PCI1CR 933e080313cSDave Liu 9344e8b750cSHeiko Schocher /* 9354e8b750cSHeiko Schocher * SCCR - System Clock Control Register 936e080313cSDave Liu */ 937e080313cSDave Liu #define SCCR_ENCCM 0x03000000 938e080313cSDave Liu #define SCCR_ENCCM_SHIFT 24 939e080313cSDave Liu #define SCCR_ENCCM_0 0x00000000 940e080313cSDave Liu #define SCCR_ENCCM_1 0x01000000 941e080313cSDave Liu #define SCCR_ENCCM_2 0x02000000 942e080313cSDave Liu #define SCCR_ENCCM_3 0x03000000 943e080313cSDave Liu 944e080313cSDave Liu #define SCCR_PCICM 0x00010000 945e080313cSDave Liu #define SCCR_PCICM_SHIFT 16 946e080313cSDave Liu 9472c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 94803051c3dSDave Liu /* SCCR bits - MPC834x specific */ 949e080313cSDave Liu #define SCCR_TSEC1CM 0xc0000000 950e080313cSDave Liu #define SCCR_TSEC1CM_SHIFT 30 951e080313cSDave Liu #define SCCR_TSEC1CM_0 0x00000000 952e080313cSDave Liu #define SCCR_TSEC1CM_1 0x40000000 953e080313cSDave Liu #define SCCR_TSEC1CM_2 0x80000000 954e080313cSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 955e080313cSDave Liu 956e080313cSDave Liu #define SCCR_TSEC2CM 0x30000000 957e080313cSDave Liu #define SCCR_TSEC2CM_SHIFT 28 958e080313cSDave Liu #define SCCR_TSEC2CM_0 0x00000000 959e080313cSDave Liu #define SCCR_TSEC2CM_1 0x10000000 960e080313cSDave Liu #define SCCR_TSEC2CM_2 0x20000000 961e080313cSDave Liu #define SCCR_TSEC2CM_3 0x30000000 962d87c57b2SScott Wood 96303051c3dSDave Liu /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 96403051c3dSDave Liu #define SCCR_USBMPHCM 0x00c00000 96503051c3dSDave Liu #define SCCR_USBMPHCM_SHIFT 22 96603051c3dSDave Liu #define SCCR_USBDRCM 0x00300000 96703051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 20 96803051c3dSDave Liu #define SCCR_USBCM 0x00f00000 96903051c3dSDave Liu #define SCCR_USBCM_SHIFT 20 97003051c3dSDave Liu #define SCCR_USBCM_0 0x00000000 97103051c3dSDave Liu #define SCCR_USBCM_1 0x00500000 97203051c3dSDave Liu #define SCCR_USBCM_2 0x00A00000 97303051c3dSDave Liu #define SCCR_USBCM_3 0x00F00000 97403051c3dSDave Liu 975555da617SDave Liu #elif defined(CONFIG_MPC8313) 976a8cb43a8SDave Liu /* TSEC1 bits are for TSEC2 as well */ 977d87c57b2SScott Wood #define SCCR_TSEC1CM 0xc0000000 978d87c57b2SScott Wood #define SCCR_TSEC1CM_SHIFT 30 9799e896478SKim Phillips #define SCCR_TSEC1CM_0 0x00000000 980d87c57b2SScott Wood #define SCCR_TSEC1CM_1 0x40000000 981d87c57b2SScott Wood #define SCCR_TSEC1CM_2 0x80000000 982d87c57b2SScott Wood #define SCCR_TSEC1CM_3 0xC0000000 983d87c57b2SScott Wood 984d87c57b2SScott Wood #define SCCR_TSEC1ON 0x20000000 985df33f6b4STimur Tabi #define SCCR_TSEC1ON_SHIFT 29 986d87c57b2SScott Wood #define SCCR_TSEC2ON 0x10000000 987df33f6b4STimur Tabi #define SCCR_TSEC2ON_SHIFT 28 988d87c57b2SScott Wood 989e080313cSDave Liu #define SCCR_USBDRCM 0x00300000 990e080313cSDave Liu #define SCCR_USBDRCM_SHIFT 20 99103051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 99203051c3dSDave Liu #define SCCR_USBDRCM_1 0x00100000 99303051c3dSDave Liu #define SCCR_USBDRCM_2 0x00200000 99403051c3dSDave Liu #define SCCR_USBDRCM_3 0x00300000 995e080313cSDave Liu 9967c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 9977c619ddcSIlya Yanok /* SCCR bits - MPC8315/MPC8308 specific */ 998555da617SDave Liu #define SCCR_TSEC1CM 0xc0000000 999555da617SDave Liu #define SCCR_TSEC1CM_SHIFT 30 1000555da617SDave Liu #define SCCR_TSEC1CM_0 0x00000000 1001555da617SDave Liu #define SCCR_TSEC1CM_1 0x40000000 1002555da617SDave Liu #define SCCR_TSEC1CM_2 0x80000000 1003555da617SDave Liu #define SCCR_TSEC1CM_3 0xC0000000 1004555da617SDave Liu 1005555da617SDave Liu #define SCCR_TSEC2CM 0x30000000 1006555da617SDave Liu #define SCCR_TSEC2CM_SHIFT 28 1007555da617SDave Liu #define SCCR_TSEC2CM_0 0x00000000 1008555da617SDave Liu #define SCCR_TSEC2CM_1 0x10000000 1009555da617SDave Liu #define SCCR_TSEC2CM_2 0x20000000 1010555da617SDave Liu #define SCCR_TSEC2CM_3 0x30000000 1011555da617SDave Liu 10127c619ddcSIlya Yanok #define SCCR_SDHCCM 0x0c000000 10137c619ddcSIlya Yanok #define SCCR_SDHCCM_SHIFT 26 10147c619ddcSIlya Yanok #define SCCR_SDHCCM_0 0x00000000 10157c619ddcSIlya Yanok #define SCCR_SDHCCM_1 0x04000000 10167c619ddcSIlya Yanok #define SCCR_SDHCCM_2 0x08000000 10177c619ddcSIlya Yanok #define SCCR_SDHCCM_3 0x0c000000 10187c619ddcSIlya Yanok 10196f3931a2SDave Liu #define SCCR_USBDRCM 0x00c00000 10206f3931a2SDave Liu #define SCCR_USBDRCM_SHIFT 22 1021555da617SDave Liu #define SCCR_USBDRCM_0 0x00000000 10226f3931a2SDave Liu #define SCCR_USBDRCM_1 0x00400000 10236f3931a2SDave Liu #define SCCR_USBDRCM_2 0x00800000 10246f3931a2SDave Liu #define SCCR_USBDRCM_3 0x00c00000 1025555da617SDave Liu 10266f3931a2SDave Liu #define SCCR_SATA1CM 0x00003000 10276f3931a2SDave Liu #define SCCR_SATA1CM_SHIFT 12 10286f3931a2SDave Liu #define SCCR_SATACM 0x00003c00 10296f3931a2SDave Liu #define SCCR_SATACM_SHIFT 10 1030555da617SDave Liu #define SCCR_SATACM_0 0x00000000 10316f3931a2SDave Liu #define SCCR_SATACM_1 0x00001400 10326f3931a2SDave Liu #define SCCR_SATACM_2 0x00002800 10336f3931a2SDave Liu #define SCCR_SATACM_3 0x00003c00 1034555da617SDave Liu 10356f3931a2SDave Liu #define SCCR_TDMCM 0x00000030 10366f3931a2SDave Liu #define SCCR_TDMCM_SHIFT 4 1037555da617SDave Liu #define SCCR_TDMCM_0 0x00000000 10386f3931a2SDave Liu #define SCCR_TDMCM_1 0x00000010 10396f3931a2SDave Liu #define SCCR_TDMCM_2 0x00000020 10406f3931a2SDave Liu #define SCCR_TDMCM_3 0x00000030 1041555da617SDave Liu 10422c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 104303051c3dSDave Liu /* SCCR bits - MPC837x specific */ 104403051c3dSDave Liu #define SCCR_TSEC1CM 0xc0000000 104503051c3dSDave Liu #define SCCR_TSEC1CM_SHIFT 30 104603051c3dSDave Liu #define SCCR_TSEC1CM_0 0x00000000 104703051c3dSDave Liu #define SCCR_TSEC1CM_1 0x40000000 104803051c3dSDave Liu #define SCCR_TSEC1CM_2 0x80000000 104903051c3dSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 105003051c3dSDave Liu 105103051c3dSDave Liu #define SCCR_TSEC2CM 0x30000000 105203051c3dSDave Liu #define SCCR_TSEC2CM_SHIFT 28 105303051c3dSDave Liu #define SCCR_TSEC2CM_0 0x00000000 105403051c3dSDave Liu #define SCCR_TSEC2CM_1 0x10000000 105503051c3dSDave Liu #define SCCR_TSEC2CM_2 0x20000000 105603051c3dSDave Liu #define SCCR_TSEC2CM_3 0x30000000 105703051c3dSDave Liu 105803051c3dSDave Liu #define SCCR_SDHCCM 0x0c000000 105903051c3dSDave Liu #define SCCR_SDHCCM_SHIFT 26 106003051c3dSDave Liu #define SCCR_SDHCCM_0 0x00000000 106103051c3dSDave Liu #define SCCR_SDHCCM_1 0x04000000 106203051c3dSDave Liu #define SCCR_SDHCCM_2 0x08000000 106303051c3dSDave Liu #define SCCR_SDHCCM_3 0x0c000000 106403051c3dSDave Liu 106503051c3dSDave Liu #define SCCR_USBDRCM 0x00c00000 106603051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 22 106703051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 106803051c3dSDave Liu #define SCCR_USBDRCM_1 0x00400000 106903051c3dSDave Liu #define SCCR_USBDRCM_2 0x00800000 107003051c3dSDave Liu #define SCCR_USBDRCM_3 0x00c00000 107103051c3dSDave Liu 1072fd6646c0SAnton Vorontsov /* All of the four SATA controllers must have the same clock ratio */ 1073fd6646c0SAnton Vorontsov #define SCCR_SATA1CM 0x000000c0 1074fd6646c0SAnton Vorontsov #define SCCR_SATA1CM_SHIFT 6 1075fd6646c0SAnton Vorontsov #define SCCR_SATACM 0x000000ff 1076fd6646c0SAnton Vorontsov #define SCCR_SATACM_SHIFT 0 1077fd6646c0SAnton Vorontsov #define SCCR_SATACM_0 0x00000000 1078fd6646c0SAnton Vorontsov #define SCCR_SATACM_1 0x00000055 1079fd6646c0SAnton Vorontsov #define SCCR_SATACM_2 0x000000aa 1080fd6646c0SAnton Vorontsov #define SCCR_SATACM_3 0x000000ff 1081*a88731a6SGerlando Falauto #elif defined(CONFIG_MPC8309) 1082*a88731a6SGerlando Falauto /* SCCR bits - MPC8309 specific */ 1083*a88731a6SGerlando Falauto #define SCCR_SDHCCM 0x0c000000 1084*a88731a6SGerlando Falauto #define SCCR_SDHCCM_SHIFT 26 1085*a88731a6SGerlando Falauto #define SCCR_SDHCCM_0 0x00000000 1086*a88731a6SGerlando Falauto #define SCCR_SDHCCM_1 0x04000000 1087*a88731a6SGerlando Falauto #define SCCR_SDHCCM_2 0x08000000 1088*a88731a6SGerlando Falauto #define SCCR_SDHCCM_3 0x0c000000 1089*a88731a6SGerlando Falauto 1090*a88731a6SGerlando Falauto #define SCCR_USBDRCM 0x00c00000 1091*a88731a6SGerlando Falauto #define SCCR_USBDRCM_SHIFT 22 1092*a88731a6SGerlando Falauto #define SCCR_USBDRCM_0 0x00000000 1093*a88731a6SGerlando Falauto #define SCCR_USBDRCM_1 0x00400000 1094*a88731a6SGerlando Falauto #define SCCR_USBDRCM_2 0x00800000 1095*a88731a6SGerlando Falauto #define SCCR_USBDRCM_3 0x00c00000 1096fd6646c0SAnton Vorontsov #endif 1097fd6646c0SAnton Vorontsov 109803051c3dSDave Liu #define SCCR_PCIEXP1CM 0x00300000 109903051c3dSDave Liu #define SCCR_PCIEXP1CM_SHIFT 20 110003051c3dSDave Liu #define SCCR_PCIEXP1CM_0 0x00000000 110103051c3dSDave Liu #define SCCR_PCIEXP1CM_1 0x00100000 110203051c3dSDave Liu #define SCCR_PCIEXP1CM_2 0x00200000 110303051c3dSDave Liu #define SCCR_PCIEXP1CM_3 0x00300000 110403051c3dSDave Liu 110503051c3dSDave Liu #define SCCR_PCIEXP2CM 0x000c0000 110603051c3dSDave Liu #define SCCR_PCIEXP2CM_SHIFT 18 110703051c3dSDave Liu #define SCCR_PCIEXP2CM_0 0x00000000 110803051c3dSDave Liu #define SCCR_PCIEXP2CM_1 0x00040000 110903051c3dSDave Liu #define SCCR_PCIEXP2CM_2 0x00080000 111003051c3dSDave Liu #define SCCR_PCIEXP2CM_3 0x000c0000 111103051c3dSDave Liu 11124e8b750cSHeiko Schocher /* 11134e8b750cSHeiko Schocher * CSn_BDNS - Chip Select memory Bounds Register 1114e080313cSDave Liu */ 1115e080313cSDave Liu #define CSBNDS_SA 0x00FF0000 1116e080313cSDave Liu #define CSBNDS_SA_SHIFT 8 1117e080313cSDave Liu #define CSBNDS_EA 0x000000FF 1118e080313cSDave Liu #define CSBNDS_EA_SHIFT 24 1119e080313cSDave Liu 11204e8b750cSHeiko Schocher /* 11214e8b750cSHeiko Schocher * CSn_CONFIG - Chip Select Configuration Register 1122e080313cSDave Liu */ 1123e080313cSDave Liu #define CSCONFIG_EN 0x80000000 1124e080313cSDave Liu #define CSCONFIG_AP 0x00800000 11258afad91fSGerlando Falauto #if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) 11262fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_NEVER 0x00000000 11272fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 11282fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 11292fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ALL 0x00400000 11302fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_NEVER 0x00000000 11312fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 11322fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 11332fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ALL 0x00040000 11342fef4020SJoe Hershberger #elif defined(CONFIG_MPC832x) 11352fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_CFG 0x00400000 11366d2c26acSHeiko Schocher #define CSCONFIG_ODT_WR_CFG 0x00040000 11372fef4020SJoe Hershberger #elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x) 11382fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_NEVER 0x00000000 11392fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 11402fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 11412fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000 11422fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ALL 0x00400000 11432fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_NEVER 0x00000000 11442fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 11452fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 11462fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000 11472fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ALL 0x00040000 11486d2c26acSHeiko Schocher #endif 1149d82b4fc0STor Krill #define CSCONFIG_BANK_BIT_3 0x00004000 1150e080313cSDave Liu #define CSCONFIG_ROW_BIT 0x00000700 1151e080313cSDave Liu #define CSCONFIG_ROW_BIT_12 0x00000000 1152e080313cSDave Liu #define CSCONFIG_ROW_BIT_13 0x00000100 1153e080313cSDave Liu #define CSCONFIG_ROW_BIT_14 0x00000200 1154e080313cSDave Liu #define CSCONFIG_COL_BIT 0x00000007 1155e080313cSDave Liu #define CSCONFIG_COL_BIT_8 0x00000000 1156e080313cSDave Liu #define CSCONFIG_COL_BIT_9 0x00000001 1157e080313cSDave Liu #define CSCONFIG_COL_BIT_10 0x00000002 1158e080313cSDave Liu #define CSCONFIG_COL_BIT_11 0x00000003 1159e080313cSDave Liu 11604e8b750cSHeiko Schocher /* 11614e8b750cSHeiko Schocher * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 1162d87c57b2SScott Wood */ 1163d87c57b2SScott Wood #define TIMING_CFG0_RWT 0xC0000000 1164d87c57b2SScott Wood #define TIMING_CFG0_RWT_SHIFT 30 1165d87c57b2SScott Wood #define TIMING_CFG0_WRT 0x30000000 1166d87c57b2SScott Wood #define TIMING_CFG0_WRT_SHIFT 28 1167d87c57b2SScott Wood #define TIMING_CFG0_RRT 0x0C000000 1168d87c57b2SScott Wood #define TIMING_CFG0_RRT_SHIFT 26 1169d87c57b2SScott Wood #define TIMING_CFG0_WWT 0x03000000 1170d87c57b2SScott Wood #define TIMING_CFG0_WWT_SHIFT 24 1171d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 1172d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 1173d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 1174d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 1175d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 1176d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 1177d892b2dbSAnton Vorontsov #define TIMING_CFG0_MRS_CYC 0x0000000F 1178d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC_SHIFT 0 1179d87c57b2SScott Wood 11804e8b750cSHeiko Schocher /* 11814e8b750cSHeiko Schocher * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 1182e080313cSDave Liu */ 1183e080313cSDave Liu #define TIMING_CFG1_PRETOACT 0x70000000 1184e080313cSDave Liu #define TIMING_CFG1_PRETOACT_SHIFT 28 1185e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE 0x0F000000 1186e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE_SHIFT 24 1187e080313cSDave Liu #define TIMING_CFG1_ACTTORW 0x00700000 1188e080313cSDave Liu #define TIMING_CFG1_ACTTORW_SHIFT 20 1189e080313cSDave Liu #define TIMING_CFG1_CASLAT 0x00070000 1190e080313cSDave Liu #define TIMING_CFG1_CASLAT_SHIFT 16 1191e080313cSDave Liu #define TIMING_CFG1_REFREC 0x0000F000 1192e080313cSDave Liu #define TIMING_CFG1_REFREC_SHIFT 12 1193e080313cSDave Liu #define TIMING_CFG1_WRREC 0x00000700 1194e080313cSDave Liu #define TIMING_CFG1_WRREC_SHIFT 8 1195e080313cSDave Liu #define TIMING_CFG1_ACTTOACT 0x00000070 1196e080313cSDave Liu #define TIMING_CFG1_ACTTOACT_SHIFT 4 1197e080313cSDave Liu #define TIMING_CFG1_WRTORD 0x00000007 1198e080313cSDave Liu #define TIMING_CFG1_WRTORD_SHIFT 0 1199e080313cSDave Liu #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 1200e080313cSDave Liu #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 1201facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ 1202facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ 1203facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ 12042b68b233SHeiko Schocher #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ 12052b68b233SHeiko Schocher #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ 1206e080313cSDave Liu 12074e8b750cSHeiko Schocher /* 12084e8b750cSHeiko Schocher * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 1209e080313cSDave Liu */ 12108d172c0fSXie Xiaobo #define TIMING_CFG2_CPO 0x0F800000 12118d172c0fSXie Xiaobo #define TIMING_CFG2_CPO_SHIFT 23 1212e080313cSDave Liu #define TIMING_CFG2_ACSM 0x00080000 1213e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 1214e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 12154e8b750cSHeiko Schocher /* default (= CASLAT + 1) */ 12164e8b750cSHeiko Schocher #define TIMING_CFG2_CPO_DEF 0x00000000 1217e080313cSDave Liu 1218d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT 0x70000000 1219d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT_SHIFT 28 1220d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 1221d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 1222d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE 0x0000E000 1223d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 1224d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS 0x000001C0 1225d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS_SHIFT 6 1226d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT 0x0000003F 1227d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT_SHIFT 0 1228d87c57b2SScott Wood 12294e8b750cSHeiko Schocher /* 1230f1ccd106SHeiko Schocher * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 1231f1ccd106SHeiko Schocher */ 1232f1ccd106SHeiko Schocher #define TIMING_CFG3_EXT_REFREC 0x00070000 1233f1ccd106SHeiko Schocher #define TIMING_CFG3_EXT_REFREC_SHIFT 16 1234f1ccd106SHeiko Schocher 1235f1ccd106SHeiko Schocher /* 12364e8b750cSHeiko Schocher * DDR_SDRAM_CFG - DDR SDRAM Control Configuration 1237e080313cSDave Liu */ 1238e080313cSDave Liu #define SDRAM_CFG_MEM_EN 0x80000000 1239e080313cSDave Liu #define SDRAM_CFG_SREN 0x40000000 1240e080313cSDave Liu #define SDRAM_CFG_ECC_EN 0x20000000 1241e080313cSDave Liu #define SDRAM_CFG_RD_EN 0x10000000 1242bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 1243bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 1244bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 1245e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 1246e080313cSDave Liu #define SDRAM_CFG_DYN_PWR 0x00200000 12472fef4020SJoe Hershberger #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) 12482fef4020SJoe Hershberger #define SDRAM_CFG_DBW_MASK 0x00180000 12492fef4020SJoe Hershberger #define SDRAM_CFG_DBW_16 0x00100000 12502fef4020SJoe Hershberger #define SDRAM_CFG_DBW_32 0x00080000 12512fef4020SJoe Hershberger #else 1252e080313cSDave Liu #define SDRAM_CFG_32_BE 0x00080000 12532fef4020SJoe Hershberger #endif 12542fef4020SJoe Hershberger #if !defined(CONFIG_MPC8308) 1255e080313cSDave Liu #define SDRAM_CFG_8_BE 0x00040000 12562fef4020SJoe Hershberger #endif 1257e080313cSDave Liu #define SDRAM_CFG_NCAP 0x00020000 1258e080313cSDave Liu #define SDRAM_CFG_2T_EN 0x00008000 1259a7b8126eSAndre Schwarz #define SDRAM_CFG_HSE 0x00000008 1260d87c57b2SScott Wood #define SDRAM_CFG_BI 0x00000001 1261e080313cSDave Liu 12624e8b750cSHeiko Schocher /* 12634e8b750cSHeiko Schocher * DDR_SDRAM_MODE - DDR SDRAM Mode Register 1264e080313cSDave Liu */ 1265e080313cSDave Liu #define SDRAM_MODE_ESD 0xFFFF0000 1266e080313cSDave Liu #define SDRAM_MODE_ESD_SHIFT 16 1267e080313cSDave Liu #define SDRAM_MODE_SD 0x0000FFFF 1268e080313cSDave Liu #define SDRAM_MODE_SD_SHIFT 0 12694e8b750cSHeiko Schocher /* select extended mode reg */ 12704e8b750cSHeiko Schocher #define DDR_MODE_EXT_MODEREG 0x4000 12714e8b750cSHeiko Schocher /* operating mode, mask */ 12724e8b750cSHeiko Schocher #define DDR_MODE_EXT_OPMODE 0x3FF8 1273e080313cSDave Liu #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 12744e8b750cSHeiko Schocher /* QFC / compatibility, mask */ 12754e8b750cSHeiko Schocher #define DDR_MODE_QFC 0x0004 12764e8b750cSHeiko Schocher /* compatible to older SDRAMs */ 12774e8b750cSHeiko Schocher #define DDR_MODE_QFC_COMP 0x0000 12784e8b750cSHeiko Schocher /* weak drivers */ 12794e8b750cSHeiko Schocher #define DDR_MODE_WEAK 0x0002 12804e8b750cSHeiko Schocher /* disable DLL */ 12814e8b750cSHeiko Schocher #define DDR_MODE_DLL_DIS 0x0001 12824e8b750cSHeiko Schocher /* CAS latency, mask */ 12834e8b750cSHeiko Schocher #define DDR_MODE_CASLAT 0x0070 1284e080313cSDave Liu #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 1285e080313cSDave Liu #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 1286e080313cSDave Liu #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 1287e080313cSDave Liu #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 12884e8b750cSHeiko Schocher /* sequential burst */ 12894e8b750cSHeiko Schocher #define DDR_MODE_BTYPE_SEQ 0x0000 12904e8b750cSHeiko Schocher /* interleaved burst */ 12914e8b750cSHeiko Schocher #define DDR_MODE_BTYPE_ILVD 0x0008 1292e080313cSDave Liu #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 1293e080313cSDave Liu #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 12944e8b750cSHeiko Schocher /* exact value for 7.8125us */ 12954e8b750cSHeiko Schocher #define DDR_REFINT_166MHZ_7US 1302 12964e8b750cSHeiko Schocher /* use 256 cycles as a starting point */ 12974e8b750cSHeiko Schocher #define DDR_BSTOPRE 256 12984e8b750cSHeiko Schocher /* select mode register */ 12994e8b750cSHeiko Schocher #define DDR_MODE_MODEREG 0x0000 1300e080313cSDave Liu 13014e8b750cSHeiko Schocher /* 13024e8b750cSHeiko Schocher * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 1303e080313cSDave Liu */ 1304e080313cSDave Liu #define SDRAM_INTERVAL_REFINT 0x3FFF0000 1305e080313cSDave Liu #define SDRAM_INTERVAL_REFINT_SHIFT 16 1306e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 1307e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 1308e080313cSDave Liu 13094e8b750cSHeiko Schocher /* 13104e8b750cSHeiko Schocher * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 1311e080313cSDave Liu */ 1312e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 1313e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 1314e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 1315e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 1316e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 1317e080313cSDave Liu 13184e8b750cSHeiko Schocher /* 13194e8b750cSHeiko Schocher * ECC_ERR_INJECT - Memory data path error injection mask ECC 1320e080313cSDave Liu */ 13214e8b750cSHeiko Schocher /* ECC Mirror Byte */ 13224e8b750cSHeiko Schocher #define ECC_ERR_INJECT_EMB (0x80000000 >> 22) 13234e8b750cSHeiko Schocher /* Error Injection Enable */ 13244e8b750cSHeiko Schocher #define ECC_ERR_INJECT_EIEN (0x80000000 >> 23) 13254e8b750cSHeiko Schocher /* ECC Erroe Injection Enable */ 13264e8b750cSHeiko Schocher #define ECC_ERR_INJECT_EEIM (0xff000000 >> 24) 1327e080313cSDave Liu #define ECC_ERR_INJECT_EEIM_SHIFT 0 1328e080313cSDave Liu 13294e8b750cSHeiko Schocher /* 13304e8b750cSHeiko Schocher * CAPTURE_ECC - Memory data path read capture ECC 1331e080313cSDave Liu */ 1332e080313cSDave Liu #define CAPTURE_ECC_ECE (0xff000000 >> 24) 1333e080313cSDave Liu #define CAPTURE_ECC_ECE_SHIFT 0 1334e080313cSDave Liu 13354e8b750cSHeiko Schocher /* 13364e8b750cSHeiko Schocher * ERR_DETECT - Memory error detect 1337e080313cSDave Liu */ 13384e8b750cSHeiko Schocher /* Multiple Memory Errors */ 13394e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_MME (0x80000000 >> 0) 13404e8b750cSHeiko Schocher /* Multiple-Bit Error */ 13414e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_MBE (0x80000000 >> 28) 13424e8b750cSHeiko Schocher /* Single-Bit ECC Error Pickup */ 13434e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_SBE (0x80000000 >> 29) 13444e8b750cSHeiko Schocher /* Memory Select Error */ 13454e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_MSE (0x80000000 >> 31) 1346e080313cSDave Liu 13474e8b750cSHeiko Schocher /* 13484e8b750cSHeiko Schocher * ERR_DISABLE - Memory error disable 1349e080313cSDave Liu */ 13504e8b750cSHeiko Schocher /* Multiple-Bit ECC Error Disable */ 13514e8b750cSHeiko Schocher #define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28) 13524e8b750cSHeiko Schocher /* Sinle-Bit ECC Error disable */ 13534e8b750cSHeiko Schocher #define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29) 13544e8b750cSHeiko Schocher /* Memory Select Error Disable */ 13554e8b750cSHeiko Schocher #define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31) 13564e8b750cSHeiko Schocher #define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \ 13574e8b750cSHeiko Schocher ECC_ERROR_DISABLE_SBED | \ 13584e8b750cSHeiko Schocher ECC_ERROR_DISABLE_MBED)) 13594e8b750cSHeiko Schocher 13604e8b750cSHeiko Schocher /* 13614e8b750cSHeiko Schocher * ERR_INT_EN - Memory error interrupt enable 1362e080313cSDave Liu */ 13634e8b750cSHeiko Schocher /* Multiple-Bit ECC Error Interrupt Enable */ 13644e8b750cSHeiko Schocher #define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28) 13654e8b750cSHeiko Schocher /* Single-Bit ECC Error Interrupt Enable */ 13664e8b750cSHeiko Schocher #define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29) 13674e8b750cSHeiko Schocher /* Memory Select Error Interrupt Enable */ 13684e8b750cSHeiko Schocher #define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31) 13694e8b750cSHeiko Schocher #define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \ 13704e8b750cSHeiko Schocher ECC_ERR_INT_EN_SBEE | \ 13714e8b750cSHeiko Schocher ECC_ERR_INT_EN_MSEE)) 13724e8b750cSHeiko Schocher 13734e8b750cSHeiko Schocher /* 13744e8b750cSHeiko Schocher * CAPTURE_ATTRIBUTES - Memory error attributes capture 1375e080313cSDave Liu */ 13764e8b750cSHeiko Schocher /* Data Beat Num */ 13774e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1) 1378e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM_SHIFT 28 13794e8b750cSHeiko Schocher /* Transaction Size */ 13804e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6) 1381e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 1382e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 1383e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1384e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1385e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 13864e8b750cSHeiko Schocher /* Transaction Source */ 13874e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11) 1388e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1389e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1390e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1391e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1392e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1393e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1394e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1395e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1396e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1397e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1398e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1399e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_SHIFT 16 14004e8b750cSHeiko Schocher /* Transaction Type */ 14014e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18) 1402e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1403e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_READ 0x2 1404e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1405e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1406e080313cSDave Liu #define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */ 1407e080313cSDave Liu 14084e8b750cSHeiko Schocher /* 14094e8b750cSHeiko Schocher * ERR_SBE - Single bit ECC memory error management 1410e080313cSDave Liu */ 14114e8b750cSHeiko Schocher /* Single-Bit Error Threshold 0..255 */ 14124e8b750cSHeiko Schocher #define ECC_ERROR_MAN_SBET (0xff000000 >> 8) 1413e080313cSDave Liu #define ECC_ERROR_MAN_SBET_SHIFT 16 14144e8b750cSHeiko Schocher /* Single Bit Error Counter 0..255 */ 14154e8b750cSHeiko Schocher #define ECC_ERROR_MAN_SBEC (0xff000000 >> 24) 1416e080313cSDave Liu #define ECC_ERROR_MAN_SBEC_SHIFT 0 1417e080313cSDave Liu 14184e8b750cSHeiko Schocher /* 14194e8b750cSHeiko Schocher * CONFIG_ADDRESS - PCI Config Address Register 1420e080313cSDave Liu */ 1421e080313cSDave Liu #define PCI_CONFIG_ADDRESS_EN 0x80000000 1422e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1423e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1424e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1425e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1426e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1427e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1428e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1429e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1430e080313cSDave Liu 14314e8b750cSHeiko Schocher /* 14324e8b750cSHeiko Schocher * POTAR - PCI Outbound Translation Address Register 1433e080313cSDave Liu */ 1434e080313cSDave Liu #define POTAR_TA_MASK 0x000fffff 1435e080313cSDave Liu 14364e8b750cSHeiko Schocher /* 14374e8b750cSHeiko Schocher * POBAR - PCI Outbound Base Address Register 1438e080313cSDave Liu */ 1439e080313cSDave Liu #define POBAR_BA_MASK 0x000fffff 1440e080313cSDave Liu 14414e8b750cSHeiko Schocher /* 14424e8b750cSHeiko Schocher * POCMR - PCI Outbound Comparision Mask Register 1443e080313cSDave Liu */ 1444e080313cSDave Liu #define POCMR_EN 0x80000000 14454e8b750cSHeiko Schocher /* 0-memory space 1-I/O space */ 14464e8b750cSHeiko Schocher #define POCMR_IO 0x40000000 1447e080313cSDave Liu #define POCMR_SE 0x20000000 /* streaming enable */ 1448e080313cSDave Liu #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1449e080313cSDave Liu #define POCMR_CM_MASK 0x000fffff 1450e080313cSDave Liu #define POCMR_CM_4G 0x00000000 1451e080313cSDave Liu #define POCMR_CM_2G 0x00080000 1452e080313cSDave Liu #define POCMR_CM_1G 0x000C0000 1453e080313cSDave Liu #define POCMR_CM_512M 0x000E0000 1454e080313cSDave Liu #define POCMR_CM_256M 0x000F0000 1455e080313cSDave Liu #define POCMR_CM_128M 0x000F8000 1456e080313cSDave Liu #define POCMR_CM_64M 0x000FC000 1457e080313cSDave Liu #define POCMR_CM_32M 0x000FE000 1458e080313cSDave Liu #define POCMR_CM_16M 0x000FF000 1459e080313cSDave Liu #define POCMR_CM_8M 0x000FF800 1460e080313cSDave Liu #define POCMR_CM_4M 0x000FFC00 1461e080313cSDave Liu #define POCMR_CM_2M 0x000FFE00 1462e080313cSDave Liu #define POCMR_CM_1M 0x000FFF00 1463e080313cSDave Liu #define POCMR_CM_512K 0x000FFF80 1464e080313cSDave Liu #define POCMR_CM_256K 0x000FFFC0 1465e080313cSDave Liu #define POCMR_CM_128K 0x000FFFE0 1466e080313cSDave Liu #define POCMR_CM_64K 0x000FFFF0 1467e080313cSDave Liu #define POCMR_CM_32K 0x000FFFF8 1468e080313cSDave Liu #define POCMR_CM_16K 0x000FFFFC 1469e080313cSDave Liu #define POCMR_CM_8K 0x000FFFFE 1470e080313cSDave Liu #define POCMR_CM_4K 0x000FFFFF 1471e080313cSDave Liu 14724e8b750cSHeiko Schocher /* 14734e8b750cSHeiko Schocher * PITAR - PCI Inbound Translation Address Register 1474e080313cSDave Liu */ 1475e080313cSDave Liu #define PITAR_TA_MASK 0x000fffff 1476e080313cSDave Liu 14774e8b750cSHeiko Schocher /* 14784e8b750cSHeiko Schocher * PIBAR - PCI Inbound Base/Extended Address Register 1479e080313cSDave Liu */ 1480e080313cSDave Liu #define PIBAR_MASK 0xffffffff 1481e080313cSDave Liu #define PIEBAR_EBA_MASK 0x000fffff 1482e080313cSDave Liu 14834e8b750cSHeiko Schocher /* 14844e8b750cSHeiko Schocher * PIWAR - PCI Inbound Windows Attributes Register 1485e080313cSDave Liu */ 1486e080313cSDave Liu #define PIWAR_EN 0x80000000 1487e080313cSDave Liu #define PIWAR_PF 0x20000000 1488e080313cSDave Liu #define PIWAR_RTT_MASK 0x000f0000 1489e080313cSDave Liu #define PIWAR_RTT_NO_SNOOP 0x00040000 1490e080313cSDave Liu #define PIWAR_RTT_SNOOP 0x00050000 1491e080313cSDave Liu #define PIWAR_WTT_MASK 0x0000f000 1492e080313cSDave Liu #define PIWAR_WTT_NO_SNOOP 0x00004000 1493e080313cSDave Liu #define PIWAR_WTT_SNOOP 0x00005000 1494e080313cSDave Liu #define PIWAR_IWS_MASK 0x0000003F 1495e080313cSDave Liu #define PIWAR_IWS_4K 0x0000000B 1496e080313cSDave Liu #define PIWAR_IWS_8K 0x0000000C 1497e080313cSDave Liu #define PIWAR_IWS_16K 0x0000000D 1498e080313cSDave Liu #define PIWAR_IWS_32K 0x0000000E 1499e080313cSDave Liu #define PIWAR_IWS_64K 0x0000000F 1500e080313cSDave Liu #define PIWAR_IWS_128K 0x00000010 1501e080313cSDave Liu #define PIWAR_IWS_256K 0x00000011 1502e080313cSDave Liu #define PIWAR_IWS_512K 0x00000012 1503e080313cSDave Liu #define PIWAR_IWS_1M 0x00000013 1504e080313cSDave Liu #define PIWAR_IWS_2M 0x00000014 1505e080313cSDave Liu #define PIWAR_IWS_4M 0x00000015 1506e080313cSDave Liu #define PIWAR_IWS_8M 0x00000016 1507e080313cSDave Liu #define PIWAR_IWS_16M 0x00000017 1508e080313cSDave Liu #define PIWAR_IWS_32M 0x00000018 1509e080313cSDave Liu #define PIWAR_IWS_64M 0x00000019 1510e080313cSDave Liu #define PIWAR_IWS_128M 0x0000001A 1511e080313cSDave Liu #define PIWAR_IWS_256M 0x0000001B 1512e080313cSDave Liu #define PIWAR_IWS_512M 0x0000001C 1513e080313cSDave Liu #define PIWAR_IWS_1G 0x0000001D 1514e080313cSDave Liu #define PIWAR_IWS_2G 0x0000001E 1515f6eda7f8SDave Liu 15164e8b750cSHeiko Schocher /* 15174e8b750cSHeiko Schocher * PMCCR1 - PCI Configuration Register 1 1518d87c57b2SScott Wood */ 1519d87c57b2SScott Wood #define PMCCR1_POWER_OFF 0x00000020 1520d87c57b2SScott Wood 15214e8b750cSHeiko Schocher /* 15224e8b750cSHeiko Schocher * DDRCDR - DDR Control Driver Register 1523d87c57b2SScott Wood */ 15249e896478SKim Phillips #define DDRCDR_DHC_EN 0x80000000 1525d87c57b2SScott Wood #define DDRCDR_EN 0x40000000 1526d87c57b2SScott Wood #define DDRCDR_PZ 0x3C000000 1527d87c57b2SScott Wood #define DDRCDR_PZ_MAXZ 0x00000000 1528d87c57b2SScott Wood #define DDRCDR_PZ_HIZ 0x20000000 1529d87c57b2SScott Wood #define DDRCDR_PZ_NOMZ 0x30000000 1530d87c57b2SScott Wood #define DDRCDR_PZ_LOZ 0x38000000 1531d87c57b2SScott Wood #define DDRCDR_PZ_MINZ 0x3C000000 1532d87c57b2SScott Wood #define DDRCDR_NZ 0x3C000000 1533d87c57b2SScott Wood #define DDRCDR_NZ_MAXZ 0x00000000 1534d87c57b2SScott Wood #define DDRCDR_NZ_HIZ 0x02000000 1535d87c57b2SScott Wood #define DDRCDR_NZ_NOMZ 0x03000000 1536d87c57b2SScott Wood #define DDRCDR_NZ_LOZ 0x03800000 1537d87c57b2SScott Wood #define DDRCDR_NZ_MINZ 0x03C00000 1538d87c57b2SScott Wood #define DDRCDR_ODT 0x00080000 1539d87c57b2SScott Wood #define DDRCDR_DDR_CFG 0x00040000 1540d87c57b2SScott Wood #define DDRCDR_M_ODR 0x00000002 1541d87c57b2SScott Wood #define DDRCDR_Q_DRN 0x00000001 1542d87c57b2SScott Wood 15434e8b750cSHeiko Schocher /* 15444e8b750cSHeiko Schocher * PCIE Bridge Register 1545fd6646c0SAnton Vorontsov */ 1546fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_OBPIOE 0x00000001 1547fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_IBPIOE 0x00000002 1548fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_WDMAE 0x00000004 1549fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_RDMAE 0x00000008 1550fd6646c0SAnton Vorontsov 1551fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_PIOE 0x00000001 1552fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_MEMWE 0x00000002 1553fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_IOWE 0x00000004 1554fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_CFGWE 0x00000008 1555fd6646c0SAnton Vorontsov 1556fd6646c0SAnton Vorontsov #define PEX_CSB_IBCTRL_PIOE 0x00000001 1557fd6646c0SAnton Vorontsov 1558fd6646c0SAnton Vorontsov #define PEX_OWAR_EN 0x00000001 1559fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_CFG 0x00000000 1560fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_IO 0x00000002 1561fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_MEM 0x00000004 1562fd6646c0SAnton Vorontsov #define PEX_OWAR_RLXO 0x00000008 1563fd6646c0SAnton Vorontsov #define PEX_OWAR_NANP 0x00000010 1564fd6646c0SAnton Vorontsov #define PEX_OWAR_SIZE 0xFFFFF000 1565fd6646c0SAnton Vorontsov 1566fd6646c0SAnton Vorontsov #define PEX_IWAR_EN 0x00000001 1567fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_INT 0x00000000 1568fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_PF 0x00000004 1569fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_NO_PF 0x00000006 1570fd6646c0SAnton Vorontsov #define PEX_IWAR_NSOV 0x00000008 1571fd6646c0SAnton Vorontsov #define PEX_IWAR_NSNP 0x00000010 1572fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE 0xFFFFF000 1573fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_1M 0x000FF000 1574fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_2M 0x001FF000 1575fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_4M 0x003FF000 1576fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_8M 0x007FF000 1577fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_16M 0x00FFF000 1578fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_32M 0x01FFF000 1579fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_64M 0x03FFF000 1580fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_128M 0x07FFF000 1581fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_256M 0x0FFFF000 1582fd6646c0SAnton Vorontsov 1583fd6646c0SAnton Vorontsov #define PEX_GCLK_RATIO 0x440 1584fd6646c0SAnton Vorontsov 158549ea3b6eSScott Wood #ifndef __ASSEMBLY__ 158649ea3b6eSScott Wood struct pci_region; 15876aa3d3bfSPeter Tyser void mpc83xx_pci_init(int num_buses, struct pci_region **reg); 158875f35209SIra Snyder void mpc83xx_pcislave_unlock(int bus); 15896aa3d3bfSPeter Tyser void mpc83xx_pcie_init(int num_buses, struct pci_region **reg); 159049ea3b6eSScott Wood #endif 159149ea3b6eSScott Wood 1592f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 1593