1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2f046ccd1SEran Liberty /* 37c619ddcSIlya Yanok * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc. 4f046ccd1SEran Liberty */ 5f046ccd1SEran Liberty 6f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 7f046ccd1SEran Liberty #define __MPC83XX_H__ 8f046ccd1SEran Liberty 9f6eda7f8SDave Liu #include <config.h> 10bf30bb1fSAnton Vorontsov #include <asm/fsl_lbc.h> 11f046ccd1SEran Liberty #if defined(CONFIG_E300) 12f046ccd1SEran Liberty #include <asm/e300.h> 13f046ccd1SEran Liberty #endif 14f046ccd1SEran Liberty 154e8b750cSHeiko Schocher /* 164e8b750cSHeiko Schocher * MPC83xx cpu provide RCR register to do reset thing specially 17f046ccd1SEran Liberty */ 18f046ccd1SEran Liberty #define MPC83xx_RESET 19f046ccd1SEran Liberty 204e8b750cSHeiko Schocher /* 214e8b750cSHeiko Schocher * System reset offset (PowerPC standard) 22f046ccd1SEran Liberty */ 23f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 2402032e8fSRafal Jaworowski #define _START_OFFSET EXC_OFF_SYS_RESET 25f046ccd1SEran Liberty 264e8b750cSHeiko Schocher /* 274e8b750cSHeiko Schocher * IMMRBAR - Internal Memory Register Base Address 28f046ccd1SEran Liberty */ 29e4c09508SScott Wood #ifndef CONFIG_DEFAULT_IMMR 304e8b750cSHeiko Schocher /* Default IMMR base address */ 314e8b750cSHeiko Schocher #define CONFIG_DEFAULT_IMMR 0xFF400000 32e4c09508SScott Wood #endif 334e8b750cSHeiko Schocher /* Register offset to immr */ 344e8b750cSHeiko Schocher #define IMMRBAR 0x0000 354e8b750cSHeiko Schocher #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */ 36f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 37f046ccd1SEran Liberty 384e8b750cSHeiko Schocher /* 394e8b750cSHeiko Schocher * LAWBAR - Local Access Window Base Address Register 40f046ccd1SEran Liberty */ 414e8b750cSHeiko Schocher /* Register offset to immr */ 424e8b750cSHeiko Schocher #define LBLAWBAR0 0x0020 43f046ccd1SEran Liberty #define LBLAWAR0 0x0024 44f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 45f046ccd1SEran Liberty #define LBLAWAR1 0x002C 46f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 47f046ccd1SEran Liberty #define LBLAWAR2 0x0034 48f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 49f046ccd1SEran Liberty #define LBLAWAR3 0x003C 504e8b750cSHeiko Schocher #define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */ 51f046ccd1SEran Liberty 524e8b750cSHeiko Schocher /* 534e8b750cSHeiko Schocher * SPRIDR - System Part and Revision ID Register 54f6eda7f8SDave Liu */ 55e5c4ade4SKim Phillips #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ 56e5c4ade4SKim Phillips #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ 57e080313cSDave Liu 582c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 59e5c4ade4SKim Phillips #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) 60e5c4ade4SKim Phillips #define REVID_MINOR(spridr) (spridr & 0x000000FF) 61e5c4ade4SKim Phillips #else 62e5c4ade4SKim Phillips #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) 63e5c4ade4SKim Phillips #define REVID_MINOR(spridr) (spridr & 0x0000000F) 64e5c4ade4SKim Phillips #endif 655f820439SDave Liu 66e5c4ade4SKim Phillips #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) 676b70ffb9SKim Phillips #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) 685f820439SDave Liu 697c619ddcSIlya Yanok #define SPR_8308 0x8100 70a88731a6SGerlando Falauto #define SPR_8309 0x8110 716b70ffb9SKim Phillips #define SPR_831X_FAMILY 0x80B 72e5c4ade4SKim Phillips #define SPR_8311 0x80B2 73e5c4ade4SKim Phillips #define SPR_8313 0x80B0 74e5c4ade4SKim Phillips #define SPR_8314 0x80B6 75e5c4ade4SKim Phillips #define SPR_8315 0x80B4 766b70ffb9SKim Phillips #define SPR_832X_FAMILY 0x806 77e5c4ade4SKim Phillips #define SPR_8321 0x8066 78e5c4ade4SKim Phillips #define SPR_8323 0x8062 796b70ffb9SKim Phillips #define SPR_834X_FAMILY 0x803 80e5c4ade4SKim Phillips #define SPR_8343 0x8036 81e5c4ade4SKim Phillips #define SPR_8347_TBGA_ 0x8032 82e5c4ade4SKim Phillips #define SPR_8347_PBGA_ 0x8034 83e5c4ade4SKim Phillips #define SPR_8349 0x8030 846b70ffb9SKim Phillips #define SPR_836X_FAMILY 0x804 85e5c4ade4SKim Phillips #define SPR_8358_TBGA_ 0x804A 86e5c4ade4SKim Phillips #define SPR_8358_PBGA_ 0x804E 87e5c4ade4SKim Phillips #define SPR_8360 0x8048 886b70ffb9SKim Phillips #define SPR_837X_FAMILY 0x80C 89e5c4ade4SKim Phillips #define SPR_8377 0x80C6 90e5c4ade4SKim Phillips #define SPR_8378 0x80C4 91e5c4ade4SKim Phillips #define SPR_8379 0x80C2 92d87c57b2SScott Wood 934e8b750cSHeiko Schocher /* 944e8b750cSHeiko Schocher * SPCR - System Priority Configuration Register 95f046ccd1SEran Liberty */ 964e8b750cSHeiko Schocher /* PCI Highest Priority Enable */ 974e8b750cSHeiko Schocher #define SPCR_PCIHPE 0x10000000 98e080313cSDave Liu #define SPCR_PCIHPE_SHIFT (31-3) 994e8b750cSHeiko Schocher /* PCI bridge system bus request priority */ 1004e8b750cSHeiko Schocher #define SPCR_PCIPR 0x03000000 101e080313cSDave Liu #define SPCR_PCIPR_SHIFT (31-7) 102e080313cSDave Liu #define SPCR_OPT 0x00800000 /* Optimize */ 1035bbeea86SMichael Barkowski #define SPCR_OPT_SHIFT (31-8) 1044e8b750cSHeiko Schocher /* E300 PowerPC core time base unit enable */ 1054e8b750cSHeiko Schocher #define SPCR_TBEN 0x00400000 106e080313cSDave Liu #define SPCR_TBEN_SHIFT (31-9) 1074e8b750cSHeiko Schocher /* E300 PowerPC Core system bus request priority */ 1084e8b750cSHeiko Schocher #define SPCR_COREPR 0x00300000 109e080313cSDave Liu #define SPCR_COREPR_SHIFT (31-11) 110e080313cSDave Liu 1112c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 112e080313cSDave Liu /* SPCR bits - MPC8349 specific */ 1134e8b750cSHeiko Schocher /* TSEC1 data priority */ 1144e8b750cSHeiko Schocher #define SPCR_TSEC1DP 0x00003000 115e080313cSDave Liu #define SPCR_TSEC1DP_SHIFT (31-19) 1164e8b750cSHeiko Schocher /* TSEC1 buffer descriptor priority */ 1174e8b750cSHeiko Schocher #define SPCR_TSEC1BDP 0x00000C00 118e080313cSDave Liu #define SPCR_TSEC1BDP_SHIFT (31-21) 1194e8b750cSHeiko Schocher /* TSEC1 emergency priority */ 1204e8b750cSHeiko Schocher #define SPCR_TSEC1EP 0x00000300 121e080313cSDave Liu #define SPCR_TSEC1EP_SHIFT (31-23) 1224e8b750cSHeiko Schocher /* TSEC2 data priority */ 1234e8b750cSHeiko Schocher #define SPCR_TSEC2DP 0x00000030 124e080313cSDave Liu #define SPCR_TSEC2DP_SHIFT (31-27) 1254e8b750cSHeiko Schocher /* TSEC2 buffer descriptor priority */ 1264e8b750cSHeiko Schocher #define SPCR_TSEC2BDP 0x0000000C 127e080313cSDave Liu #define SPCR_TSEC2BDP_SHIFT (31-29) 1284e8b750cSHeiko Schocher /* TSEC2 emergency priority */ 1294e8b750cSHeiko Schocher #define SPCR_TSEC2EP 0x00000003 130e080313cSDave Liu #define SPCR_TSEC2EP_SHIFT (31-31) 131d87c57b2SScott Wood 1327c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 1337c619ddcSIlya Yanok defined(CONFIG_MPC837x) 1347c619ddcSIlya Yanok /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ 1354e8b750cSHeiko Schocher /* TSEC data priority */ 1364e8b750cSHeiko Schocher #define SPCR_TSECDP 0x00003000 137d87c57b2SScott Wood #define SPCR_TSECDP_SHIFT (31-19) 1384e8b750cSHeiko Schocher /* TSEC buffer descriptor priority */ 1394e8b750cSHeiko Schocher #define SPCR_TSECBDP 0x00000C00 140ec2638eaSDave Liu #define SPCR_TSECBDP_SHIFT (31-21) 1414e8b750cSHeiko Schocher /* TSEC emergency priority */ 1424e8b750cSHeiko Schocher #define SPCR_TSECEP 0x00000300 143ec2638eaSDave Liu #define SPCR_TSECEP_SHIFT (31-23) 144e080313cSDave Liu #endif 145e080313cSDave Liu 146e080313cSDave Liu /* SICRL/H - System I/O Configuration Register Low/High 147e080313cSDave Liu */ 1482c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 149e080313cSDave Liu /* SICRL bits - MPC8349 specific */ 150e080313cSDave Liu #define SICRL_LDP_A 0x80000000 151e080313cSDave Liu #define SICRL_USB1 0x40000000 152e080313cSDave Liu #define SICRL_USB0 0x20000000 153e080313cSDave Liu #define SICRL_UART 0x0C000000 154e080313cSDave Liu #define SICRL_GPIO1_A 0x02000000 155e080313cSDave Liu #define SICRL_GPIO1_B 0x01000000 156e080313cSDave Liu #define SICRL_GPIO1_C 0x00800000 157e080313cSDave Liu #define SICRL_GPIO1_D 0x00400000 158e080313cSDave Liu #define SICRL_GPIO1_E 0x00200000 159e080313cSDave Liu #define SICRL_GPIO1_F 0x00180000 160e080313cSDave Liu #define SICRL_GPIO1_G 0x00040000 161e080313cSDave Liu #define SICRL_GPIO1_H 0x00020000 162e080313cSDave Liu #define SICRL_GPIO1_I 0x00010000 163e080313cSDave Liu #define SICRL_GPIO1_J 0x00008000 164e080313cSDave Liu #define SICRL_GPIO1_K 0x00004000 165e080313cSDave Liu #define SICRL_GPIO1_L 0x00003000 166e080313cSDave Liu 167e080313cSDave Liu /* SICRH bits - MPC8349 specific */ 168e080313cSDave Liu #define SICRH_DDR 0x80000000 169e080313cSDave Liu #define SICRH_TSEC1_A 0x10000000 170e080313cSDave Liu #define SICRH_TSEC1_B 0x08000000 171e080313cSDave Liu #define SICRH_TSEC1_C 0x04000000 172e080313cSDave Liu #define SICRH_TSEC1_D 0x02000000 173e080313cSDave Liu #define SICRH_TSEC1_E 0x01000000 174e080313cSDave Liu #define SICRH_TSEC1_F 0x00800000 175e080313cSDave Liu #define SICRH_TSEC2_A 0x00400000 176e080313cSDave Liu #define SICRH_TSEC2_B 0x00200000 177e080313cSDave Liu #define SICRH_TSEC2_C 0x00100000 178e080313cSDave Liu #define SICRH_TSEC2_D 0x00080000 179e080313cSDave Liu #define SICRH_TSEC2_E 0x00040000 180e080313cSDave Liu #define SICRH_TSEC2_F 0x00020000 181e080313cSDave Liu #define SICRH_TSEC2_G 0x00010000 182e080313cSDave Liu #define SICRH_TSEC2_H 0x00008000 183e080313cSDave Liu #define SICRH_GPIO2_A 0x00004000 184e080313cSDave Liu #define SICRH_GPIO2_B 0x00002000 185e080313cSDave Liu #define SICRH_GPIO2_C 0x00001000 186e080313cSDave Liu #define SICRH_GPIO2_D 0x00000800 187e080313cSDave Liu #define SICRH_GPIO2_E 0x00000400 188e080313cSDave Liu #define SICRH_GPIO2_F 0x00000200 189e080313cSDave Liu #define SICRH_GPIO2_G 0x00000180 190e080313cSDave Liu #define SICRH_GPIO2_H 0x00000060 191e080313cSDave Liu #define SICRH_TSOBI1 0x00000002 192e080313cSDave Liu #define SICRH_TSOBI2 0x00000001 193e080313cSDave Liu 194e080313cSDave Liu #elif defined(CONFIG_MPC8360) 195e080313cSDave Liu /* SICRL bits - MPC8360 specific */ 196e080313cSDave Liu #define SICRL_LDP_A 0xC0000000 197e080313cSDave Liu #define SICRL_LCLK_1 0x10000000 198e080313cSDave Liu #define SICRL_LCLK_2 0x08000000 199e080313cSDave Liu #define SICRL_SRCID_A 0x03000000 200e080313cSDave Liu #define SICRL_IRQ_CKSTP_A 0x00C00000 201e080313cSDave Liu 202e080313cSDave Liu /* SICRH bits - MPC8360 specific */ 203e080313cSDave Liu #define SICRH_DDR 0x80000000 204e080313cSDave Liu #define SICRH_SECONDARY_DDR 0x40000000 205e080313cSDave Liu #define SICRH_SDDROE 0x20000000 206e080313cSDave Liu #define SICRH_IRQ3 0x10000000 207e080313cSDave Liu #define SICRH_UC1EOBI 0x00000004 208e080313cSDave Liu #define SICRH_UC2E1OBI 0x00000002 209e080313cSDave Liu #define SICRH_UC2E2OBI 0x00000001 21024c3aca3SDave Liu 2112c7920afSPeter Tyser #elif defined(CONFIG_MPC832x) 2122c7920afSPeter Tyser /* SICRL bits - MPC832x specific */ 21324c3aca3SDave Liu #define SICRL_LDP_LCS_A 0x80000000 21424c3aca3SDave Liu #define SICRL_IRQ_CKS 0x20000000 21524c3aca3SDave Liu #define SICRL_PCI_MSRC 0x10000000 21624c3aca3SDave Liu #define SICRL_URT_CTPR 0x06000000 21724c3aca3SDave Liu #define SICRL_IRQ_CTPR 0x00C00000 218d87c57b2SScott Wood 219555da617SDave Liu #elif defined(CONFIG_MPC8313) 220555da617SDave Liu /* SICRL bits - MPC8313 specific */ 221d87c57b2SScott Wood #define SICRL_LBC 0x30000000 222d87c57b2SScott Wood #define SICRL_UART 0x0C000000 223d87c57b2SScott Wood #define SICRL_SPI_A 0x03000000 224d87c57b2SScott Wood #define SICRL_SPI_B 0x00C00000 225d87c57b2SScott Wood #define SICRL_SPI_C 0x00300000 226d87c57b2SScott Wood #define SICRL_SPI_D 0x000C0000 227f986325dSRon Madrid #define SICRL_USBDR_11 0x00000C00 228f986325dSRon Madrid #define SICRL_USBDR_10 0x00000800 229f986325dSRon Madrid #define SICRL_USBDR_01 0x00000400 230f986325dSRon Madrid #define SICRL_USBDR_00 0x00000000 231d87c57b2SScott Wood #define SICRL_ETSEC1_A 0x0000000C 232d87c57b2SScott Wood #define SICRL_ETSEC2_A 0x00000003 233d87c57b2SScott Wood 234555da617SDave Liu /* SICRH bits - MPC8313 specific */ 235d87c57b2SScott Wood #define SICRH_INTR_A 0x02000000 236d87c57b2SScott Wood #define SICRH_INTR_B 0x00C00000 237d87c57b2SScott Wood #define SICRH_IIC 0x00300000 238d87c57b2SScott Wood #define SICRH_ETSEC2_B 0x000C0000 239d87c57b2SScott Wood #define SICRH_ETSEC2_C 0x00030000 240d87c57b2SScott Wood #define SICRH_ETSEC2_D 0x0000C000 241d87c57b2SScott Wood #define SICRH_ETSEC2_E 0x00003000 242d87c57b2SScott Wood #define SICRH_ETSEC2_F 0x00000C00 243d87c57b2SScott Wood #define SICRH_ETSEC2_G 0x00000300 244d87c57b2SScott Wood #define SICRH_ETSEC1_B 0x00000080 245d87c57b2SScott Wood #define SICRH_ETSEC1_C 0x00000060 246d87c57b2SScott Wood #define SICRH_GTX1_DLY 0x00000008 247d87c57b2SScott Wood #define SICRH_GTX2_DLY 0x00000004 248d87c57b2SScott Wood #define SICRH_TSOBI1 0x00000002 249d87c57b2SScott Wood #define SICRH_TSOBI2 0x00000001 250d87c57b2SScott Wood 251555da617SDave Liu #elif defined(CONFIG_MPC8315) 252555da617SDave Liu /* SICRL bits - MPC8315 specific */ 253555da617SDave Liu #define SICRL_DMA_CH0 0xc0000000 254555da617SDave Liu #define SICRL_DMA_SPI 0x30000000 255555da617SDave Liu #define SICRL_UART 0x0c000000 256555da617SDave Liu #define SICRL_IRQ4 0x02000000 257555da617SDave Liu #define SICRL_IRQ5 0x01800000 258555da617SDave Liu #define SICRL_IRQ6_7 0x00400000 259555da617SDave Liu #define SICRL_IIC1 0x00300000 260555da617SDave Liu #define SICRL_TDM 0x000c0000 261555da617SDave Liu #define SICRL_TDM_SHARED 0x00030000 262555da617SDave Liu #define SICRL_PCI_A 0x0000c000 263555da617SDave Liu #define SICRL_ELBC_A 0x00003000 264555da617SDave Liu #define SICRL_ETSEC1_A 0x000000c0 265555da617SDave Liu #define SICRL_ETSEC1_B 0x00000030 266555da617SDave Liu #define SICRL_ETSEC1_C 0x0000000c 267555da617SDave Liu #define SICRL_TSEXPOBI 0x00000001 268555da617SDave Liu 269555da617SDave Liu /* SICRH bits - MPC8315 specific */ 270555da617SDave Liu #define SICRH_GPIO_0 0xc0000000 271555da617SDave Liu #define SICRH_GPIO_1 0x30000000 272555da617SDave Liu #define SICRH_GPIO_2 0x0c000000 273555da617SDave Liu #define SICRH_GPIO_3 0x03000000 274555da617SDave Liu #define SICRH_GPIO_4 0x00c00000 275555da617SDave Liu #define SICRH_GPIO_5 0x00300000 276555da617SDave Liu #define SICRH_GPIO_6 0x000c0000 277555da617SDave Liu #define SICRH_GPIO_7 0x00030000 278555da617SDave Liu #define SICRH_GPIO_8 0x0000c000 279555da617SDave Liu #define SICRH_GPIO_9 0x00003000 280555da617SDave Liu #define SICRH_GPIO_10 0x00000c00 281555da617SDave Liu #define SICRH_GPIO_11 0x00000300 282555da617SDave Liu #define SICRH_ETSEC2_A 0x000000c0 283555da617SDave Liu #define SICRH_TSOBI1 0x00000002 284555da617SDave Liu #define SICRH_TSOBI2 0x00000001 285555da617SDave Liu 2862c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 28703051c3dSDave Liu /* SICRL bits - MPC837x specific */ 28803051c3dSDave Liu #define SICRL_USB_A 0xC0000000 28903051c3dSDave Liu #define SICRL_USB_B 0x30000000 290e1ac387fSAndy Fleming #define SICRL_USB_B_SD 0x20000000 29103051c3dSDave Liu #define SICRL_UART 0x0C000000 29203051c3dSDave Liu #define SICRL_GPIO_A 0x02000000 29303051c3dSDave Liu #define SICRL_GPIO_B 0x01000000 29403051c3dSDave Liu #define SICRL_GPIO_C 0x00800000 29503051c3dSDave Liu #define SICRL_GPIO_D 0x00400000 29603051c3dSDave Liu #define SICRL_GPIO_E 0x00200000 29703051c3dSDave Liu #define SICRL_GPIO_F 0x00180000 29803051c3dSDave Liu #define SICRL_GPIO_G 0x00040000 29903051c3dSDave Liu #define SICRL_GPIO_H 0x00020000 30003051c3dSDave Liu #define SICRL_GPIO_I 0x00010000 30103051c3dSDave Liu #define SICRL_GPIO_J 0x00008000 30203051c3dSDave Liu #define SICRL_GPIO_K 0x00004000 30303051c3dSDave Liu #define SICRL_GPIO_L 0x00003000 30403051c3dSDave Liu #define SICRL_DMA_A 0x00000800 30503051c3dSDave Liu #define SICRL_DMA_B 0x00000400 30603051c3dSDave Liu #define SICRL_DMA_C 0x00000200 30703051c3dSDave Liu #define SICRL_DMA_D 0x00000100 30803051c3dSDave Liu #define SICRL_DMA_E 0x00000080 30903051c3dSDave Liu #define SICRL_DMA_F 0x00000040 31003051c3dSDave Liu #define SICRL_DMA_G 0x00000020 31103051c3dSDave Liu #define SICRL_DMA_H 0x00000010 31203051c3dSDave Liu #define SICRL_DMA_I 0x00000008 31303051c3dSDave Liu #define SICRL_DMA_J 0x00000004 31403051c3dSDave Liu #define SICRL_LDP_A 0x00000002 31503051c3dSDave Liu #define SICRL_LDP_B 0x00000001 31603051c3dSDave Liu 31703051c3dSDave Liu /* SICRH bits - MPC837x specific */ 31803051c3dSDave Liu #define SICRH_DDR 0x80000000 31903051c3dSDave Liu #define SICRH_TSEC1_A 0x10000000 32003051c3dSDave Liu #define SICRH_TSEC1_B 0x08000000 32103051c3dSDave Liu #define SICRH_TSEC2_A 0x00400000 32203051c3dSDave Liu #define SICRH_TSEC2_B 0x00200000 32303051c3dSDave Liu #define SICRH_TSEC2_C 0x00100000 32403051c3dSDave Liu #define SICRH_TSEC2_D 0x00080000 32503051c3dSDave Liu #define SICRH_TSEC2_E 0x00040000 32603051c3dSDave Liu #define SICRH_TMR 0x00010000 32703051c3dSDave Liu #define SICRH_GPIO2_A 0x00008000 32803051c3dSDave Liu #define SICRH_GPIO2_B 0x00004000 32903051c3dSDave Liu #define SICRH_GPIO2_C 0x00002000 33003051c3dSDave Liu #define SICRH_GPIO2_D 0x00001000 33103051c3dSDave Liu #define SICRH_GPIO2_E 0x00000C00 332e1ac387fSAndy Fleming #define SICRH_GPIO2_E_SD 0x00000800 33303051c3dSDave Liu #define SICRH_GPIO2_F 0x00000300 33403051c3dSDave Liu #define SICRH_GPIO2_G 0x000000C0 33503051c3dSDave Liu #define SICRH_GPIO2_H 0x00000030 33603051c3dSDave Liu #define SICRH_SPI 0x00000003 337e1ac387fSAndy Fleming #define SICRH_SPI_SD 0x00000001 338f3ce250dSIlya Yanok 339f3ce250dSIlya Yanok #elif defined(CONFIG_MPC8308) 340f3ce250dSIlya Yanok /* SICRL bits - MPC8308 specific */ 341f3ce250dSIlya Yanok #define SICRL_SPI_PF0 (0 << 28) 342f3ce250dSIlya Yanok #define SICRL_SPI_PF1 (1 << 28) 343f3ce250dSIlya Yanok #define SICRL_SPI_PF3 (3 << 28) 344f3ce250dSIlya Yanok #define SICRL_UART_PF0 (0 << 26) 345f3ce250dSIlya Yanok #define SICRL_UART_PF1 (1 << 26) 346f3ce250dSIlya Yanok #define SICRL_UART_PF3 (3 << 26) 347f3ce250dSIlya Yanok #define SICRL_IRQ_PF0 (0 << 24) 348f3ce250dSIlya Yanok #define SICRL_IRQ_PF1 (1 << 24) 349f3ce250dSIlya Yanok #define SICRL_I2C2_PF0 (0 << 20) 350f3ce250dSIlya Yanok #define SICRL_I2C2_PF1 (1 << 20) 351f3ce250dSIlya Yanok #define SICRL_ETSEC1_TX_CLK (0 << 6) 352f3ce250dSIlya Yanok #define SICRL_ETSEC1_GTX_CLK125 (1 << 6) 353f3ce250dSIlya Yanok 354f3ce250dSIlya Yanok /* SICRH bits - MPC8308 specific */ 355f3ce250dSIlya Yanok #define SICRH_ESDHC_A_SD (0 << 30) 356f3ce250dSIlya Yanok #define SICRH_ESDHC_A_GTM (1 << 30) 357f3ce250dSIlya Yanok #define SICRH_ESDHC_A_GPIO (3 << 30) 358f3ce250dSIlya Yanok #define SICRH_ESDHC_B_SD (0 << 28) 359f3ce250dSIlya Yanok #define SICRH_ESDHC_B_GTM (1 << 28) 360f3ce250dSIlya Yanok #define SICRH_ESDHC_B_GPIO (3 << 28) 361f3ce250dSIlya Yanok #define SICRH_ESDHC_C_SD (0 << 26) 362f3ce250dSIlya Yanok #define SICRH_ESDHC_C_GTM (1 << 26) 363f3ce250dSIlya Yanok #define SICRH_ESDHC_C_GPIO (3 << 26) 364f3ce250dSIlya Yanok #define SICRH_GPIO_A_GPIO (0 << 24) 365f3ce250dSIlya Yanok #define SICRH_GPIO_A_TSEC2 (1 << 24) 366f3ce250dSIlya Yanok #define SICRH_GPIO_B_GPIO (0 << 22) 367f3ce250dSIlya Yanok #define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22) 368f3ce250dSIlya Yanok #define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22) 369f3ce250dSIlya Yanok #define SICRH_IEEE1588_A_TMR (1 << 20) 370f3ce250dSIlya Yanok #define SICRH_IEEE1588_A_GPIO (3 << 20) 371f3ce250dSIlya Yanok #define SICRH_USB (1 << 18) 372f3ce250dSIlya Yanok #define SICRH_GTM_GTM (1 << 16) 373f3ce250dSIlya Yanok #define SICRH_GTM_GPIO (3 << 16) 374f3ce250dSIlya Yanok #define SICRH_IEEE1588_B_TMR (1 << 14) 375f3ce250dSIlya Yanok #define SICRH_IEEE1588_B_GPIO (3 << 14) 376f3ce250dSIlya Yanok #define SICRH_ETSEC2_CRS (1 << 12) 377f3ce250dSIlya Yanok #define SICRH_ETSEC2_GPIO (3 << 12) 378f3ce250dSIlya Yanok #define SICRH_GPIOSEL_0 (0 << 8) 379f3ce250dSIlya Yanok #define SICRH_GPIOSEL_1 (1 << 8) 380f3ce250dSIlya Yanok #define SICRH_TMROBI_V3P3 (0 << 4) 381f3ce250dSIlya Yanok #define SICRH_TMROBI_V2P5 (1 << 4) 382f3ce250dSIlya Yanok #define SICRH_TSOBI1_V3P3 (0 << 1) 383f3ce250dSIlya Yanok #define SICRH_TSOBI1_V2P5 (1 << 1) 384f3ce250dSIlya Yanok #define SICRH_TSOBI2_V3P3 (0 << 0) 385f3ce250dSIlya Yanok #define SICRH_TSOBI2_V2P5 (1 << 0) 386a88731a6SGerlando Falauto 387a88731a6SGerlando Falauto #elif defined(CONFIG_MPC8309) 388a88731a6SGerlando Falauto /* SICR_1 */ 389a88731a6SGerlando Falauto #define SICR_1_UART1_UART1S (0 << (30-2)) 390a88731a6SGerlando Falauto #define SICR_1_UART1_UART1RTS (1 << (30-2)) 391a88731a6SGerlando Falauto #define SICR_1_I2C_I2C (0 << (30-4)) 392a88731a6SGerlando Falauto #define SICR_1_I2C_CKSTOP (1 << (30-4)) 393a88731a6SGerlando Falauto #define SICR_1_IRQ_A_IRQ (0 << (30-6)) 394a88731a6SGerlando Falauto #define SICR_1_IRQ_A_MCP (1 << (30-6)) 395a88731a6SGerlando Falauto #define SICR_1_IRQ_B_IRQ (0 << (30-8)) 396a88731a6SGerlando Falauto #define SICR_1_IRQ_B_CKSTOP (1 << (30-8)) 397a88731a6SGerlando Falauto #define SICR_1_GPIO_A_GPIO (0 << (30-10)) 398a88731a6SGerlando Falauto #define SICR_1_GPIO_A_SD (2 << (30-10)) 399a88731a6SGerlando Falauto #define SICR_1_GPIO_A_DDR (3 << (30-10)) 400a88731a6SGerlando Falauto #define SICR_1_GPIO_B_GPIO (0 << (30-12)) 401a88731a6SGerlando Falauto #define SICR_1_GPIO_B_SD (2 << (30-12)) 402a88731a6SGerlando Falauto #define SICR_1_GPIO_B_QE (3 << (30-12)) 403a88731a6SGerlando Falauto #define SICR_1_GPIO_C_GPIO (0 << (30-14)) 404a88731a6SGerlando Falauto #define SICR_1_GPIO_C_CAN (1 << (30-14)) 405a88731a6SGerlando Falauto #define SICR_1_GPIO_C_DDR (2 << (30-14)) 406a88731a6SGerlando Falauto #define SICR_1_GPIO_C_LCS (3 << (30-14)) 407a88731a6SGerlando Falauto #define SICR_1_GPIO_D_GPIO (0 << (30-16)) 408a88731a6SGerlando Falauto #define SICR_1_GPIO_D_CAN (1 << (30-16)) 409a88731a6SGerlando Falauto #define SICR_1_GPIO_D_DDR (2 << (30-16)) 410a88731a6SGerlando Falauto #define SICR_1_GPIO_D_LCS (3 << (30-16)) 411a88731a6SGerlando Falauto #define SICR_1_GPIO_E_GPIO (0 << (30-18)) 412a88731a6SGerlando Falauto #define SICR_1_GPIO_E_CAN (1 << (30-18)) 413a88731a6SGerlando Falauto #define SICR_1_GPIO_E_DDR (2 << (30-18)) 414a88731a6SGerlando Falauto #define SICR_1_GPIO_E_LCS (3 << (30-18)) 415a88731a6SGerlando Falauto #define SICR_1_GPIO_F_GPIO (0 << (30-20)) 416a88731a6SGerlando Falauto #define SICR_1_GPIO_F_CAN (1 << (30-20)) 417a88731a6SGerlando Falauto #define SICR_1_GPIO_F_CK (2 << (30-20)) 418a88731a6SGerlando Falauto #define SICR_1_USB_A_USBDR (0 << (30-22)) 419a88731a6SGerlando Falauto #define SICR_1_USB_A_UART2S (1 << (30-22)) 420a88731a6SGerlando Falauto #define SICR_1_USB_B_USBDR (0 << (30-24)) 421a88731a6SGerlando Falauto #define SICR_1_USB_B_UART2S (1 << (30-24)) 422a88731a6SGerlando Falauto #define SICR_1_USB_B_UART2RTS (2 << (30-24)) 423a88731a6SGerlando Falauto #define SICR_1_USB_C_USBDR (0 << (30-26)) 424a88731a6SGerlando Falauto #define SICR_1_USB_C_QE_EXT (3 << (30-26)) 425a88731a6SGerlando Falauto #define SICR_1_FEC1_FEC1 (0 << (30-28)) 426a88731a6SGerlando Falauto #define SICR_1_FEC1_GTM (1 << (30-28)) 427a88731a6SGerlando Falauto #define SICR_1_FEC1_GPIO (2 << (30-28)) 428a88731a6SGerlando Falauto #define SICR_1_FEC2_FEC2 (0 << (30-30)) 429a88731a6SGerlando Falauto #define SICR_1_FEC2_GTM (1 << (30-30)) 430a88731a6SGerlando Falauto #define SICR_1_FEC2_GPIO (2 << (30-30)) 431a88731a6SGerlando Falauto /* SICR_2 */ 432a88731a6SGerlando Falauto #define SICR_2_FEC3_FEC3 (0 << (30-0)) 433a88731a6SGerlando Falauto #define SICR_2_FEC3_TMR (1 << (30-0)) 434a88731a6SGerlando Falauto #define SICR_2_FEC3_GPIO (2 << (30-0)) 435a88731a6SGerlando Falauto #define SICR_2_HDLC1_A_HDLC1 (0 << (30-2)) 436a88731a6SGerlando Falauto #define SICR_2_HDLC1_A_GPIO (1 << (30-2)) 437a88731a6SGerlando Falauto #define SICR_2_HDLC1_A_TDM1 (2 << (30-2)) 438a88731a6SGerlando Falauto #define SICR_2_ELBC_A_LA (0 << (30-4)) 439a88731a6SGerlando Falauto #define SICR_2_ELBC_B_LCLK (0 << (30-6)) 440a88731a6SGerlando Falauto #define SICR_2_HDLC2_A_HDLC2 (0 << (30-8)) 441a88731a6SGerlando Falauto #define SICR_2_HDLC2_A_GPIO (0 << (30-8)) 442a88731a6SGerlando Falauto #define SICR_2_HDLC2_A_TDM2 (0 << (30-8)) 443a88731a6SGerlando Falauto /* bits 10-11 unused */ 444a88731a6SGerlando Falauto #define SICR_2_USB_D_USBDR (0 << (30-12)) 445a88731a6SGerlando Falauto #define SICR_2_USB_D_GPIO (2 << (30-12)) 446a88731a6SGerlando Falauto #define SICR_2_USB_D_QE_BRG (3 << (30-12)) 447a88731a6SGerlando Falauto #define SICR_2_PCI_PCI (0 << (30-14)) 448a88731a6SGerlando Falauto #define SICR_2_PCI_CPCI_HS (2 << (30-14)) 449a88731a6SGerlando Falauto #define SICR_2_HDLC1_B_HDLC1 (0 << (30-16)) 450a88731a6SGerlando Falauto #define SICR_2_HDLC1_B_GPIO (1 << (30-16)) 451a88731a6SGerlando Falauto #define SICR_2_HDLC1_B_QE_BRG (2 << (30-16)) 452a88731a6SGerlando Falauto #define SICR_2_HDLC1_B_TDM1 (3 << (30-16)) 453a88731a6SGerlando Falauto #define SICR_2_HDLC1_C_HDLC1 (0 << (30-18)) 454a88731a6SGerlando Falauto #define SICR_2_HDLC1_C_GPIO (1 << (30-18)) 455a88731a6SGerlando Falauto #define SICR_2_HDLC1_C_TDM1 (2 << (30-18)) 456a88731a6SGerlando Falauto #define SICR_2_HDLC2_B_HDLC2 (0 << (30-20)) 457a88731a6SGerlando Falauto #define SICR_2_HDLC2_B_GPIO (1 << (30-20)) 458a88731a6SGerlando Falauto #define SICR_2_HDLC2_B_QE_BRG (2 << (30-20)) 459a88731a6SGerlando Falauto #define SICR_2_HDLC2_B_TDM2 (3 << (30-20)) 460a88731a6SGerlando Falauto #define SICR_2_HDLC2_C_HDLC2 (0 << (30-22)) 461a88731a6SGerlando Falauto #define SICR_2_HDLC2_C_GPIO (1 << (30-22)) 462a88731a6SGerlando Falauto #define SICR_2_HDLC2_C_TDM2 (2 << (30-22)) 463a88731a6SGerlando Falauto #define SICR_2_HDLC2_C_QE_BRG (3 << (30-22)) 464a88731a6SGerlando Falauto #define SICR_2_QUIESCE_B (0 << (30-24)) 465a88731a6SGerlando Falauto 466e080313cSDave Liu #endif 467e080313cSDave Liu 4684e8b750cSHeiko Schocher /* 4694e8b750cSHeiko Schocher * SWCRR - System Watchdog Control Register 470e080313cSDave Liu */ 4714e8b750cSHeiko Schocher /* Register offset to immr */ 4724e8b750cSHeiko Schocher #define SWCRR 0x0204 4734e8b750cSHeiko Schocher /* Software Watchdog Time Count */ 4744e8b750cSHeiko Schocher #define SWCRR_SWTC 0xFFFF0000 4754e8b750cSHeiko Schocher /* Watchdog Enable bit */ 4764e8b750cSHeiko Schocher #define SWCRR_SWEN 0x00000004 4774e8b750cSHeiko Schocher /* Software Watchdog Reset/Interrupt Select bit */ 4784e8b750cSHeiko Schocher #define SWCRR_SWRI 0x00000002 4794e8b750cSHeiko Schocher /* Software Watchdog Counter Prescale bit */ 4804e8b750cSHeiko Schocher #define SWCRR_SWPR 0x00000001 4814e8b750cSHeiko Schocher #define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \ 4824e8b750cSHeiko Schocher SWCRR_SWRI | SWCRR_SWPR)) 483e080313cSDave Liu 4844e8b750cSHeiko Schocher /* 4854e8b750cSHeiko Schocher * SWCNR - System Watchdog Counter Register 486e080313cSDave Liu */ 4874e8b750cSHeiko Schocher /* Register offset to immr */ 4884e8b750cSHeiko Schocher #define SWCNR 0x0208 4894e8b750cSHeiko Schocher /* Software Watchdog Count mask */ 4904e8b750cSHeiko Schocher #define SWCNR_SWCN 0x0000FFFF 491e080313cSDave Liu #define SWCNR_RES ~(SWCNR_SWCN) 492e080313cSDave Liu 4934e8b750cSHeiko Schocher /* 4944e8b750cSHeiko Schocher * SWSRR - System Watchdog Service Register 495e080313cSDave Liu */ 4964e8b750cSHeiko Schocher /* Register offset to immr */ 4974e8b750cSHeiko Schocher #define SWSRR 0x020E 498e080313cSDave Liu 4994e8b750cSHeiko Schocher /* 5004e8b750cSHeiko Schocher * ACR - Arbiter Configuration Register 501e080313cSDave Liu */ 502e080313cSDave Liu #define ACR_COREDIS 0x10000000 /* Core disable */ 503e080313cSDave Liu #define ACR_COREDIS_SHIFT (31-7) 504e080313cSDave Liu #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 505e080313cSDave Liu #define ACR_PIPE_DEP_SHIFT (31-15) 506e080313cSDave Liu #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 507e080313cSDave Liu #define ACR_PCI_RPTCNT_SHIFT (31-19) 508e080313cSDave Liu #define ACR_RPTCNT 0x00000700 /* Repeat count */ 509e080313cSDave Liu #define ACR_RPTCNT_SHIFT (31-23) 510e080313cSDave Liu #define ACR_APARK 0x00000030 /* Address parking */ 511e080313cSDave Liu #define ACR_APARK_SHIFT (31-27) 512e080313cSDave Liu #define ACR_PARKM 0x0000000F /* Parking master */ 513e080313cSDave Liu #define ACR_PARKM_SHIFT (31-31) 514e080313cSDave Liu 5154e8b750cSHeiko Schocher /* 5164e8b750cSHeiko Schocher * ATR - Arbiter Timers Register 517e080313cSDave Liu */ 518e080313cSDave Liu #define ATR_DTO 0x00FF0000 /* Data time out */ 519002d27caSNick Spence #define ATR_DTO_SHIFT 16 520e080313cSDave Liu #define ATR_ATO 0x000000FF /* Address time out */ 521002d27caSNick Spence #define ATR_ATO_SHIFT 0 522e080313cSDave Liu 5234e8b750cSHeiko Schocher /* 5244e8b750cSHeiko Schocher * AER - Arbiter Event Register 525e080313cSDave Liu */ 526e080313cSDave Liu #define AER_ETEA 0x00000020 /* Transfer error */ 5274e8b750cSHeiko Schocher /* Reserved transfer type */ 5284e8b750cSHeiko Schocher #define AER_RES 0x00000010 5294e8b750cSHeiko Schocher /* External control word transfer type */ 5304e8b750cSHeiko Schocher #define AER_ECW 0x00000008 5314e8b750cSHeiko Schocher /* Address Only transfer type */ 5324e8b750cSHeiko Schocher #define AER_AO 0x00000004 533e080313cSDave Liu #define AER_DTO 0x00000002 /* Data time out */ 534e080313cSDave Liu #define AER_ATO 0x00000001 /* Address time out */ 535e080313cSDave Liu 5364e8b750cSHeiko Schocher /* 5374e8b750cSHeiko Schocher * AEATR - Arbiter Event Address Register 538e080313cSDave Liu */ 539e080313cSDave Liu #define AEATR_EVENT 0x07000000 /* Event type */ 540002d27caSNick Spence #define AEATR_EVENT_SHIFT 24 541e080313cSDave Liu #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 542002d27caSNick Spence #define AEATR_MSTR_ID_SHIFT 16 543e080313cSDave Liu #define AEATR_TBST 0x00000800 /* Transfer burst */ 544002d27caSNick Spence #define AEATR_TBST_SHIFT 11 545e080313cSDave Liu #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 546002d27caSNick Spence #define AEATR_TSIZE_SHIFT 8 547e080313cSDave Liu #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 548002d27caSNick Spence #define AEATR_TTYPE_SHIFT 0 549e080313cSDave Liu 5504e8b750cSHeiko Schocher /* 5514e8b750cSHeiko Schocher * HRCWL - Hard Reset Configuration Word Low 552e080313cSDave Liu */ 553e080313cSDave Liu #define HRCWL_LBIUCM 0x80000000 554e080313cSDave Liu #define HRCWL_LBIUCM_SHIFT 31 555e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 556e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 557e080313cSDave Liu 558e080313cSDave Liu #define HRCWL_DDRCM 0x40000000 559e080313cSDave Liu #define HRCWL_DDRCM_SHIFT 30 560e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 561e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 562e080313cSDave Liu 563e080313cSDave Liu #define HRCWL_SPMF 0x0f000000 564e080313cSDave Liu #define HRCWL_SPMF_SHIFT 24 565e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 566e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 567e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 568e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 569e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 570e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 571e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 572e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 573e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 574e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 575e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 576e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 577e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 578e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 579e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 580e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 581e080313cSDave Liu 582e080313cSDave Liu #define HRCWL_VCO_BYPASS 0x00000000 583e080313cSDave Liu #define HRCWL_VCO_1X2 0x00000000 584e080313cSDave Liu #define HRCWL_VCO_1X4 0x00200000 585e080313cSDave Liu #define HRCWL_VCO_1X8 0x00400000 586e080313cSDave Liu 587e080313cSDave Liu #define HRCWL_COREPLL 0x007F0000 588e080313cSDave Liu #define HRCWL_COREPLL_SHIFT 16 589e080313cSDave Liu #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 590e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1X1 0x00020000 591e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 592e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2X1 0x00040000 593e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 594e080313cSDave Liu #define HRCWL_CORE_TO_CSB_3X1 0x00060000 595e080313cSDave Liu 5962c7920afSPeter Tyser #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 597e080313cSDave Liu #define HRCWL_CEVCOD 0x000000C0 598e080313cSDave Liu #define HRCWL_CEVCOD_SHIFT 6 599e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 600e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 601e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 602e080313cSDave Liu 603e080313cSDave Liu #define HRCWL_CEPDF 0x00000020 604e080313cSDave Liu #define HRCWL_CEPDF_SHIFT 5 605e080313cSDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 606e080313cSDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 607e080313cSDave Liu 608e080313cSDave Liu #define HRCWL_CEPMF 0x0000001F 609e080313cSDave Liu #define HRCWL_CEPMF_SHIFT 0 610e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 611e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 612e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 613e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 614e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 615e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 616e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 617e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 618e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 619e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 620e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 621e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 622e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 623e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 624e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 625e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 626e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 627e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 628e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 629e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 630e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 631e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 632e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 633e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 634e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 635e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 636e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 637e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 638e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 639e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 640e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 64103051c3dSDave Liu 6427c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 6436f3931a2SDave Liu #define HRCWL_SVCOD 0x30000000 6446f3931a2SDave Liu #define HRCWL_SVCOD_SHIFT 28 6456f3931a2SDave Liu #define HRCWL_SVCOD_DIV_2 0x00000000 6466f3931a2SDave Liu #define HRCWL_SVCOD_DIV_4 0x10000000 6476f3931a2SDave Liu #define HRCWL_SVCOD_DIV_8 0x20000000 6486f3931a2SDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 6496f3931a2SDave Liu 6502c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 65103051c3dSDave Liu #define HRCWL_SVCOD 0x30000000 65203051c3dSDave Liu #define HRCWL_SVCOD_SHIFT 28 65303051c3dSDave Liu #define HRCWL_SVCOD_DIV_4 0x00000000 65403051c3dSDave Liu #define HRCWL_SVCOD_DIV_8 0x10000000 65503051c3dSDave Liu #define HRCWL_SVCOD_DIV_2 0x20000000 65603051c3dSDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 657a88731a6SGerlando Falauto #elif defined(CONFIG_MPC8309) 658a88731a6SGerlando Falauto 659a88731a6SGerlando Falauto #define HRCWL_CEVCOD 0x000000C0 660a88731a6SGerlando Falauto #define HRCWL_CEVCOD_SHIFT 6 661a88731a6SGerlando Falauto /* 662a88731a6SGerlando Falauto * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012 663a88731a6SGerlando Falauto * these are different than with 8360, 832x 664a88731a6SGerlando Falauto */ 665a88731a6SGerlando Falauto #define HRCWL_CE_PLL_VCO_DIV_2 0x00000000 666a88731a6SGerlando Falauto #define HRCWL_CE_PLL_VCO_DIV_4 0x00000040 667a88731a6SGerlando Falauto #define HRCWL_CE_PLL_VCO_DIV_8 0x00000080 668a88731a6SGerlando Falauto 669a88731a6SGerlando Falauto #define HRCWL_CEPDF 0x00000020 670a88731a6SGerlando Falauto #define HRCWL_CEPDF_SHIFT 5 671a88731a6SGerlando Falauto #define HRCWL_CE_PLL_DIV_1X1 0x00000000 672a88731a6SGerlando Falauto #define HRCWL_CE_PLL_DIV_2X1 0x00000020 673a88731a6SGerlando Falauto 674a88731a6SGerlando Falauto #define HRCWL_CEPMF 0x0000001F 675a88731a6SGerlando Falauto #define HRCWL_CEPMF_SHIFT 0 676a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 677a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X2 0x00000002 678a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X3 0x00000003 679a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X4 0x00000004 680a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X5 0x00000005 681a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X6 0x00000006 682a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X7 0x00000007 683a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X8 0x00000008 684a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X9 0x00000009 685a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X10 0x0000000A 686a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X11 0x0000000B 687a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X12 0x0000000C 688a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X13 0x0000000D 689a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X14 0x0000000E 690a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X15 0x0000000F 691a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X16 0x00000010 692a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X17 0x00000011 693a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X18 0x00000012 694a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X19 0x00000013 695a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X20 0x00000014 696a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X21 0x00000015 697a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X22 0x00000016 698a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X23 0x00000017 699a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X24 0x00000018 700a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X25 0x00000019 701a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X26 0x0000001A 702a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X27 0x0000001B 703a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X28 0x0000001C 704a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X29 0x0000001D 705a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X30 0x0000001E 706a88731a6SGerlando Falauto #define HRCWL_CE_TO_PLL_1X31 0x0000001F 707a88731a6SGerlando Falauto 708a88731a6SGerlando Falauto #define HRCWL_SVCOD 0x30000000 709a88731a6SGerlando Falauto #define HRCWL_SVCOD_SHIFT 28 710a88731a6SGerlando Falauto #define HRCWL_SVCOD_DIV_2 0x00000000 711a88731a6SGerlando Falauto #define HRCWL_SVCOD_DIV_4 0x10000000 712a88731a6SGerlando Falauto #define HRCWL_SVCOD_DIV_8 0x20000000 713a88731a6SGerlando Falauto #define HRCWL_SVCOD_DIV_1 0x30000000 714e080313cSDave Liu #endif 715e080313cSDave Liu 7164e8b750cSHeiko Schocher /* 7174e8b750cSHeiko Schocher * HRCWH - Hardware Reset Configuration Word High 718e080313cSDave Liu */ 719e080313cSDave Liu #define HRCWH_PCI_HOST 0x80000000 720e080313cSDave Liu #define HRCWH_PCI_HOST_SHIFT 31 721e080313cSDave Liu #define HRCWH_PCI_AGENT 0x00000000 722e080313cSDave Liu 7232c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 724e080313cSDave Liu #define HRCWH_32_BIT_PCI 0x00000000 725e080313cSDave Liu #define HRCWH_64_BIT_PCI 0x40000000 726e080313cSDave Liu #endif 727e080313cSDave Liu 728e080313cSDave Liu #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 729e080313cSDave Liu #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 730e080313cSDave Liu 731e080313cSDave Liu #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 732e080313cSDave Liu #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 733e080313cSDave Liu 7342c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 735e080313cSDave Liu #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 736e080313cSDave Liu #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 737e080313cSDave Liu 738e080313cSDave Liu #elif defined(CONFIG_MPC8360) 739e080313cSDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 740e080313cSDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 741e080313cSDave Liu #endif 742e080313cSDave Liu 743e080313cSDave Liu #define HRCWH_CORE_DISABLE 0x08000000 744e080313cSDave Liu #define HRCWH_CORE_ENABLE 0x00000000 745e080313cSDave Liu 746e080313cSDave Liu #define HRCWH_FROM_0X00000100 0x00000000 747e080313cSDave Liu #define HRCWH_FROM_0XFFF00100 0x04000000 748e080313cSDave Liu 749e080313cSDave Liu #define HRCWH_BOOTSEQ_DISABLE 0x00000000 750e080313cSDave Liu #define HRCWH_BOOTSEQ_NORMAL 0x01000000 751e080313cSDave Liu #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 752e080313cSDave Liu 753e080313cSDave Liu #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 754e080313cSDave Liu #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 755e080313cSDave Liu 756e080313cSDave Liu #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 757e080313cSDave Liu #define HRCWH_ROM_LOC_PCI1 0x00100000 7582c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 759e080313cSDave Liu #define HRCWH_ROM_LOC_PCI2 0x00200000 760e080313cSDave Liu #endif 7612c7920afSPeter Tyser #if defined(CONFIG_MPC837x) 76203051c3dSDave Liu #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 76303051c3dSDave Liu #endif 764e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 765e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 766e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 767e080313cSDave Liu 7687c619ddcSIlya Yanok #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 7697c619ddcSIlya Yanok defined(CONFIG_MPC837x) 770d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 771d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 772d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 773d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 774d87c57b2SScott Wood 775d87c57b2SScott Wood #define HRCWH_RL_EXT_LEGACY 0x00000000 776d87c57b2SScott Wood #define HRCWH_RL_EXT_NAND 0x00040000 777d87c57b2SScott Wood 778e6d9c891SAnton Vorontsov #define HRCWH_TSEC1M_MASK 0x0000E000 779d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_MII 0x00000000 780d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RMII 0x00002000 781d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RGMII 0x00006000 782d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 783d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 784d87c57b2SScott Wood 785e6d9c891SAnton Vorontsov #define HRCWH_TSEC2M_MASK 0x00001C00 786d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_MII 0x00000000 787d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RMII 0x00000400 788d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 789d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RTBI 0x00001400 790d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_SGMII 0x00001800 791d87c57b2SScott Wood #endif 792d87c57b2SScott Wood 7932c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 794e080313cSDave Liu #define HRCWH_TSEC1M_IN_RGMII 0x00000000 795e080313cSDave Liu #define HRCWH_TSEC1M_IN_RTBI 0x00004000 796e080313cSDave Liu #define HRCWH_TSEC1M_IN_GMII 0x00008000 797e080313cSDave Liu #define HRCWH_TSEC1M_IN_TBI 0x0000C000 798e080313cSDave Liu #define HRCWH_TSEC2M_IN_RGMII 0x00000000 799e080313cSDave Liu #define HRCWH_TSEC2M_IN_RTBI 0x00001000 800e080313cSDave Liu #define HRCWH_TSEC2M_IN_GMII 0x00002000 801e080313cSDave Liu #define HRCWH_TSEC2M_IN_TBI 0x00003000 802e080313cSDave Liu #endif 803e080313cSDave Liu 804e080313cSDave Liu #if defined(CONFIG_MPC8360) 805e080313cSDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 806e080313cSDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 807e080313cSDave Liu #endif 808e080313cSDave Liu 809e080313cSDave Liu #define HRCWH_BIG_ENDIAN 0x00000000 810e080313cSDave Liu #define HRCWH_LITTLE_ENDIAN 0x00000008 811e080313cSDave Liu 812e080313cSDave Liu #define HRCWH_LALE_NORMAL 0x00000000 813e080313cSDave Liu #define HRCWH_LALE_EARLY 0x00000004 814e080313cSDave Liu 815e080313cSDave Liu #define HRCWH_LDP_SET 0x00000000 816e080313cSDave Liu #define HRCWH_LDP_CLEAR 0x00000002 817e080313cSDave Liu 8184e8b750cSHeiko Schocher /* 8194e8b750cSHeiko Schocher * RSR - Reset Status Register 820e080313cSDave Liu */ 8217c619ddcSIlya Yanok #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 8227c619ddcSIlya Yanok defined(CONFIG_MPC837x) 82303051c3dSDave Liu #define RSR_RSTSRC 0xF0000000 /* Reset source */ 82403051c3dSDave Liu #define RSR_RSTSRC_SHIFT 28 82503051c3dSDave Liu #else 826e080313cSDave Liu #define RSR_RSTSRC 0xE0000000 /* Reset source */ 827e080313cSDave Liu #define RSR_RSTSRC_SHIFT 29 82803051c3dSDave Liu #endif 829e080313cSDave Liu #define RSR_BSF 0x00010000 /* Boot seq. fail */ 830e080313cSDave Liu #define RSR_BSF_SHIFT 16 8314e8b750cSHeiko Schocher /* software soft reset */ 8324e8b750cSHeiko Schocher #define RSR_SWSR 0x00002000 833e080313cSDave Liu #define RSR_SWSR_SHIFT 13 8344e8b750cSHeiko Schocher /* software hard reset */ 8354e8b750cSHeiko Schocher #define RSR_SWHR 0x00001000 836e080313cSDave Liu #define RSR_SWHR_SHIFT 12 837e080313cSDave Liu #define RSR_JHRS 0x00000200 /* jtag hreset */ 838e080313cSDave Liu #define RSR_JHRS_SHIFT 9 8394e8b750cSHeiko Schocher /* jtag sreset status */ 8404e8b750cSHeiko Schocher #define RSR_JSRS 0x00000100 841e080313cSDave Liu #define RSR_JSRS_SHIFT 8 8424e8b750cSHeiko Schocher /* checkstop reset status */ 8434e8b750cSHeiko Schocher #define RSR_CSHR 0x00000010 844e080313cSDave Liu #define RSR_CSHR_SHIFT 4 8454e8b750cSHeiko Schocher /* software watchdog reset status */ 8464e8b750cSHeiko Schocher #define RSR_SWRS 0x00000008 847e080313cSDave Liu #define RSR_SWRS_SHIFT 3 8484e8b750cSHeiko Schocher /* bus monitop reset status */ 8494e8b750cSHeiko Schocher #define RSR_BMRS 0x00000004 850e080313cSDave Liu #define RSR_BMRS_SHIFT 2 851e080313cSDave Liu #define RSR_SRS 0x00000002 /* soft reset status */ 852e080313cSDave Liu #define RSR_SRS_SHIFT 1 853e080313cSDave Liu #define RSR_HRS 0x00000001 /* hard reset status */ 854e080313cSDave Liu #define RSR_HRS_SHIFT 0 8554e8b750cSHeiko Schocher #define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \ 8564e8b750cSHeiko Schocher RSR_SWHR | RSR_JHRS | \ 8574e8b750cSHeiko Schocher RSR_JSRS | RSR_CSHR | \ 8584e8b750cSHeiko Schocher RSR_SWRS | RSR_BMRS | \ 8594e8b750cSHeiko Schocher RSR_SRS | RSR_HRS)) 8604e8b750cSHeiko Schocher /* 8614e8b750cSHeiko Schocher * RMR - Reset Mode Register 862e080313cSDave Liu */ 8634e8b750cSHeiko Schocher /* checkstop reset enable */ 8644e8b750cSHeiko Schocher #define RMR_CSRE 0x00000001 865e080313cSDave Liu #define RMR_CSRE_SHIFT 0 866e080313cSDave Liu #define RMR_RES ~(RMR_CSRE) 867e080313cSDave Liu 8684e8b750cSHeiko Schocher /* 8694e8b750cSHeiko Schocher * RCR - Reset Control Register 870e080313cSDave Liu */ 8714e8b750cSHeiko Schocher /* software hard reset */ 8724e8b750cSHeiko Schocher #define RCR_SWHR 0x00000002 8734e8b750cSHeiko Schocher /* software soft reset */ 8744e8b750cSHeiko Schocher #define RCR_SWSR 0x00000001 875e080313cSDave Liu #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 876e080313cSDave Liu 8774e8b750cSHeiko Schocher /* 8784e8b750cSHeiko Schocher * RCER - Reset Control Enable Register 879e080313cSDave Liu */ 8804e8b750cSHeiko Schocher /* software hard reset */ 8814e8b750cSHeiko Schocher #define RCER_CRE 0x00000001 882e080313cSDave Liu #define RCER_RES ~(RCER_CRE) 883e080313cSDave Liu 8844e8b750cSHeiko Schocher /* 8854e8b750cSHeiko Schocher * SPMR - System PLL Mode Register 886e080313cSDave Liu */ 887e080313cSDave Liu #define SPMR_LBIUCM 0x80000000 88826e5f794SJoakim Tjernlund #define SPMR_LBIUCM_SHIFT 31 889e080313cSDave Liu #define SPMR_DDRCM 0x40000000 89026e5f794SJoakim Tjernlund #define SPMR_DDRCM_SHIFT 30 891e080313cSDave Liu #define SPMR_SPMF 0x0F000000 89226e5f794SJoakim Tjernlund #define SPMR_SPMF_SHIFT 24 893e080313cSDave Liu #define SPMR_CKID 0x00800000 894e080313cSDave Liu #define SPMR_CKID_SHIFT 23 895e080313cSDave Liu #define SPMR_COREPLL 0x007F0000 89626e5f794SJoakim Tjernlund #define SPMR_COREPLL_SHIFT 16 897e080313cSDave Liu #define SPMR_CEVCOD 0x000000C0 89826e5f794SJoakim Tjernlund #define SPMR_CEVCOD_SHIFT 6 899e080313cSDave Liu #define SPMR_CEPDF 0x00000020 90026e5f794SJoakim Tjernlund #define SPMR_CEPDF_SHIFT 5 901e080313cSDave Liu #define SPMR_CEPMF 0x0000001F 90226e5f794SJoakim Tjernlund #define SPMR_CEPMF_SHIFT 0 903e080313cSDave Liu 9044e8b750cSHeiko Schocher /* 9054e8b750cSHeiko Schocher * OCCR - Output Clock Control Register 906e080313cSDave Liu */ 907e080313cSDave Liu #define OCCR_PCICOE0 0x80000000 908e080313cSDave Liu #define OCCR_PCICOE1 0x40000000 909e080313cSDave Liu #define OCCR_PCICOE2 0x20000000 910e080313cSDave Liu #define OCCR_PCICOE3 0x10000000 911e080313cSDave Liu #define OCCR_PCICOE4 0x08000000 912e080313cSDave Liu #define OCCR_PCICOE5 0x04000000 913e080313cSDave Liu #define OCCR_PCICOE6 0x02000000 914e080313cSDave Liu #define OCCR_PCICOE7 0x01000000 915e080313cSDave Liu #define OCCR_PCICD0 0x00800000 916e080313cSDave Liu #define OCCR_PCICD1 0x00400000 917e080313cSDave Liu #define OCCR_PCICD2 0x00200000 918e080313cSDave Liu #define OCCR_PCICD3 0x00100000 919e080313cSDave Liu #define OCCR_PCICD4 0x00080000 920e080313cSDave Liu #define OCCR_PCICD5 0x00040000 921e080313cSDave Liu #define OCCR_PCICD6 0x00020000 922e080313cSDave Liu #define OCCR_PCICD7 0x00010000 923e080313cSDave Liu #define OCCR_PCI1CR 0x00000002 924e080313cSDave Liu #define OCCR_PCI2CR 0x00000001 925e080313cSDave Liu #define OCCR_PCICR OCCR_PCI1CR 926e080313cSDave Liu 9274e8b750cSHeiko Schocher /* 9284e8b750cSHeiko Schocher * SCCR - System Clock Control Register 929e080313cSDave Liu */ 930e080313cSDave Liu #define SCCR_ENCCM 0x03000000 931e080313cSDave Liu #define SCCR_ENCCM_SHIFT 24 932e080313cSDave Liu #define SCCR_ENCCM_0 0x00000000 933e080313cSDave Liu #define SCCR_ENCCM_1 0x01000000 934e080313cSDave Liu #define SCCR_ENCCM_2 0x02000000 935e080313cSDave Liu #define SCCR_ENCCM_3 0x03000000 936e080313cSDave Liu 937e080313cSDave Liu #define SCCR_PCICM 0x00010000 938e080313cSDave Liu #define SCCR_PCICM_SHIFT 16 939e080313cSDave Liu 9402c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 94103051c3dSDave Liu /* SCCR bits - MPC834x specific */ 942e080313cSDave Liu #define SCCR_TSEC1CM 0xc0000000 943e080313cSDave Liu #define SCCR_TSEC1CM_SHIFT 30 944e080313cSDave Liu #define SCCR_TSEC1CM_0 0x00000000 945e080313cSDave Liu #define SCCR_TSEC1CM_1 0x40000000 946e080313cSDave Liu #define SCCR_TSEC1CM_2 0x80000000 947e080313cSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 948e080313cSDave Liu 949e080313cSDave Liu #define SCCR_TSEC2CM 0x30000000 950e080313cSDave Liu #define SCCR_TSEC2CM_SHIFT 28 951e080313cSDave Liu #define SCCR_TSEC2CM_0 0x00000000 952e080313cSDave Liu #define SCCR_TSEC2CM_1 0x10000000 953e080313cSDave Liu #define SCCR_TSEC2CM_2 0x20000000 954e080313cSDave Liu #define SCCR_TSEC2CM_3 0x30000000 955d87c57b2SScott Wood 95603051c3dSDave Liu /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 95703051c3dSDave Liu #define SCCR_USBMPHCM 0x00c00000 95803051c3dSDave Liu #define SCCR_USBMPHCM_SHIFT 22 95903051c3dSDave Liu #define SCCR_USBDRCM 0x00300000 96003051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 20 96103051c3dSDave Liu #define SCCR_USBCM 0x00f00000 96203051c3dSDave Liu #define SCCR_USBCM_SHIFT 20 96303051c3dSDave Liu #define SCCR_USBCM_0 0x00000000 96403051c3dSDave Liu #define SCCR_USBCM_1 0x00500000 96503051c3dSDave Liu #define SCCR_USBCM_2 0x00A00000 96603051c3dSDave Liu #define SCCR_USBCM_3 0x00F00000 96703051c3dSDave Liu 968555da617SDave Liu #elif defined(CONFIG_MPC8313) 969a8cb43a8SDave Liu /* TSEC1 bits are for TSEC2 as well */ 970d87c57b2SScott Wood #define SCCR_TSEC1CM 0xc0000000 971d87c57b2SScott Wood #define SCCR_TSEC1CM_SHIFT 30 9729e896478SKim Phillips #define SCCR_TSEC1CM_0 0x00000000 973d87c57b2SScott Wood #define SCCR_TSEC1CM_1 0x40000000 974d87c57b2SScott Wood #define SCCR_TSEC1CM_2 0x80000000 975d87c57b2SScott Wood #define SCCR_TSEC1CM_3 0xC0000000 976d87c57b2SScott Wood 977d87c57b2SScott Wood #define SCCR_TSEC1ON 0x20000000 978df33f6b4STimur Tabi #define SCCR_TSEC1ON_SHIFT 29 979d87c57b2SScott Wood #define SCCR_TSEC2ON 0x10000000 980df33f6b4STimur Tabi #define SCCR_TSEC2ON_SHIFT 28 981d87c57b2SScott Wood 982e080313cSDave Liu #define SCCR_USBDRCM 0x00300000 983e080313cSDave Liu #define SCCR_USBDRCM_SHIFT 20 98403051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 98503051c3dSDave Liu #define SCCR_USBDRCM_1 0x00100000 98603051c3dSDave Liu #define SCCR_USBDRCM_2 0x00200000 98703051c3dSDave Liu #define SCCR_USBDRCM_3 0x00300000 988e080313cSDave Liu 9897c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 9907c619ddcSIlya Yanok /* SCCR bits - MPC8315/MPC8308 specific */ 991555da617SDave Liu #define SCCR_TSEC1CM 0xc0000000 992555da617SDave Liu #define SCCR_TSEC1CM_SHIFT 30 993555da617SDave Liu #define SCCR_TSEC1CM_0 0x00000000 994555da617SDave Liu #define SCCR_TSEC1CM_1 0x40000000 995555da617SDave Liu #define SCCR_TSEC1CM_2 0x80000000 996555da617SDave Liu #define SCCR_TSEC1CM_3 0xC0000000 997555da617SDave Liu 998555da617SDave Liu #define SCCR_TSEC2CM 0x30000000 999555da617SDave Liu #define SCCR_TSEC2CM_SHIFT 28 1000555da617SDave Liu #define SCCR_TSEC2CM_0 0x00000000 1001555da617SDave Liu #define SCCR_TSEC2CM_1 0x10000000 1002555da617SDave Liu #define SCCR_TSEC2CM_2 0x20000000 1003555da617SDave Liu #define SCCR_TSEC2CM_3 0x30000000 1004555da617SDave Liu 10057c619ddcSIlya Yanok #define SCCR_SDHCCM 0x0c000000 10067c619ddcSIlya Yanok #define SCCR_SDHCCM_SHIFT 26 10077c619ddcSIlya Yanok #define SCCR_SDHCCM_0 0x00000000 10087c619ddcSIlya Yanok #define SCCR_SDHCCM_1 0x04000000 10097c619ddcSIlya Yanok #define SCCR_SDHCCM_2 0x08000000 10107c619ddcSIlya Yanok #define SCCR_SDHCCM_3 0x0c000000 10117c619ddcSIlya Yanok 10126f3931a2SDave Liu #define SCCR_USBDRCM 0x00c00000 10136f3931a2SDave Liu #define SCCR_USBDRCM_SHIFT 22 1014555da617SDave Liu #define SCCR_USBDRCM_0 0x00000000 10156f3931a2SDave Liu #define SCCR_USBDRCM_1 0x00400000 10166f3931a2SDave Liu #define SCCR_USBDRCM_2 0x00800000 10176f3931a2SDave Liu #define SCCR_USBDRCM_3 0x00c00000 1018555da617SDave Liu 10196f3931a2SDave Liu #define SCCR_SATA1CM 0x00003000 10206f3931a2SDave Liu #define SCCR_SATA1CM_SHIFT 12 10216f3931a2SDave Liu #define SCCR_SATACM 0x00003c00 10226f3931a2SDave Liu #define SCCR_SATACM_SHIFT 10 1023555da617SDave Liu #define SCCR_SATACM_0 0x00000000 10246f3931a2SDave Liu #define SCCR_SATACM_1 0x00001400 10256f3931a2SDave Liu #define SCCR_SATACM_2 0x00002800 10266f3931a2SDave Liu #define SCCR_SATACM_3 0x00003c00 1027555da617SDave Liu 10286f3931a2SDave Liu #define SCCR_TDMCM 0x00000030 10296f3931a2SDave Liu #define SCCR_TDMCM_SHIFT 4 1030555da617SDave Liu #define SCCR_TDMCM_0 0x00000000 10316f3931a2SDave Liu #define SCCR_TDMCM_1 0x00000010 10326f3931a2SDave Liu #define SCCR_TDMCM_2 0x00000020 10336f3931a2SDave Liu #define SCCR_TDMCM_3 0x00000030 1034555da617SDave Liu 10352c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 103603051c3dSDave Liu /* SCCR bits - MPC837x specific */ 103703051c3dSDave Liu #define SCCR_TSEC1CM 0xc0000000 103803051c3dSDave Liu #define SCCR_TSEC1CM_SHIFT 30 103903051c3dSDave Liu #define SCCR_TSEC1CM_0 0x00000000 104003051c3dSDave Liu #define SCCR_TSEC1CM_1 0x40000000 104103051c3dSDave Liu #define SCCR_TSEC1CM_2 0x80000000 104203051c3dSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 104303051c3dSDave Liu 104403051c3dSDave Liu #define SCCR_TSEC2CM 0x30000000 104503051c3dSDave Liu #define SCCR_TSEC2CM_SHIFT 28 104603051c3dSDave Liu #define SCCR_TSEC2CM_0 0x00000000 104703051c3dSDave Liu #define SCCR_TSEC2CM_1 0x10000000 104803051c3dSDave Liu #define SCCR_TSEC2CM_2 0x20000000 104903051c3dSDave Liu #define SCCR_TSEC2CM_3 0x30000000 105003051c3dSDave Liu 105103051c3dSDave Liu #define SCCR_SDHCCM 0x0c000000 105203051c3dSDave Liu #define SCCR_SDHCCM_SHIFT 26 105303051c3dSDave Liu #define SCCR_SDHCCM_0 0x00000000 105403051c3dSDave Liu #define SCCR_SDHCCM_1 0x04000000 105503051c3dSDave Liu #define SCCR_SDHCCM_2 0x08000000 105603051c3dSDave Liu #define SCCR_SDHCCM_3 0x0c000000 105703051c3dSDave Liu 105803051c3dSDave Liu #define SCCR_USBDRCM 0x00c00000 105903051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 22 106003051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 106103051c3dSDave Liu #define SCCR_USBDRCM_1 0x00400000 106203051c3dSDave Liu #define SCCR_USBDRCM_2 0x00800000 106303051c3dSDave Liu #define SCCR_USBDRCM_3 0x00c00000 106403051c3dSDave Liu 1065fd6646c0SAnton Vorontsov /* All of the four SATA controllers must have the same clock ratio */ 1066fd6646c0SAnton Vorontsov #define SCCR_SATA1CM 0x000000c0 1067fd6646c0SAnton Vorontsov #define SCCR_SATA1CM_SHIFT 6 1068fd6646c0SAnton Vorontsov #define SCCR_SATACM 0x000000ff 1069fd6646c0SAnton Vorontsov #define SCCR_SATACM_SHIFT 0 1070fd6646c0SAnton Vorontsov #define SCCR_SATACM_0 0x00000000 1071fd6646c0SAnton Vorontsov #define SCCR_SATACM_1 0x00000055 1072fd6646c0SAnton Vorontsov #define SCCR_SATACM_2 0x000000aa 1073fd6646c0SAnton Vorontsov #define SCCR_SATACM_3 0x000000ff 1074a88731a6SGerlando Falauto #elif defined(CONFIG_MPC8309) 1075a88731a6SGerlando Falauto /* SCCR bits - MPC8309 specific */ 1076a88731a6SGerlando Falauto #define SCCR_SDHCCM 0x0c000000 1077a88731a6SGerlando Falauto #define SCCR_SDHCCM_SHIFT 26 1078a88731a6SGerlando Falauto #define SCCR_SDHCCM_0 0x00000000 1079a88731a6SGerlando Falauto #define SCCR_SDHCCM_1 0x04000000 1080a88731a6SGerlando Falauto #define SCCR_SDHCCM_2 0x08000000 1081a88731a6SGerlando Falauto #define SCCR_SDHCCM_3 0x0c000000 1082a88731a6SGerlando Falauto 1083a88731a6SGerlando Falauto #define SCCR_USBDRCM 0x00c00000 1084a88731a6SGerlando Falauto #define SCCR_USBDRCM_SHIFT 22 1085a88731a6SGerlando Falauto #define SCCR_USBDRCM_0 0x00000000 1086a88731a6SGerlando Falauto #define SCCR_USBDRCM_1 0x00400000 1087a88731a6SGerlando Falauto #define SCCR_USBDRCM_2 0x00800000 1088a88731a6SGerlando Falauto #define SCCR_USBDRCM_3 0x00c00000 1089fd6646c0SAnton Vorontsov #endif 1090fd6646c0SAnton Vorontsov 109103051c3dSDave Liu #define SCCR_PCIEXP1CM 0x00300000 109203051c3dSDave Liu #define SCCR_PCIEXP1CM_SHIFT 20 109303051c3dSDave Liu #define SCCR_PCIEXP1CM_0 0x00000000 109403051c3dSDave Liu #define SCCR_PCIEXP1CM_1 0x00100000 109503051c3dSDave Liu #define SCCR_PCIEXP1CM_2 0x00200000 109603051c3dSDave Liu #define SCCR_PCIEXP1CM_3 0x00300000 109703051c3dSDave Liu 109803051c3dSDave Liu #define SCCR_PCIEXP2CM 0x000c0000 109903051c3dSDave Liu #define SCCR_PCIEXP2CM_SHIFT 18 110003051c3dSDave Liu #define SCCR_PCIEXP2CM_0 0x00000000 110103051c3dSDave Liu #define SCCR_PCIEXP2CM_1 0x00040000 110203051c3dSDave Liu #define SCCR_PCIEXP2CM_2 0x00080000 110303051c3dSDave Liu #define SCCR_PCIEXP2CM_3 0x000c0000 110403051c3dSDave Liu 11054e8b750cSHeiko Schocher /* 11064e8b750cSHeiko Schocher * CSn_BDNS - Chip Select memory Bounds Register 1107e080313cSDave Liu */ 1108e080313cSDave Liu #define CSBNDS_SA 0x00FF0000 1109e080313cSDave Liu #define CSBNDS_SA_SHIFT 8 1110e080313cSDave Liu #define CSBNDS_EA 0x000000FF 1111e080313cSDave Liu #define CSBNDS_EA_SHIFT 24 1112e080313cSDave Liu 11134e8b750cSHeiko Schocher /* 11144e8b750cSHeiko Schocher * CSn_CONFIG - Chip Select Configuration Register 1115e080313cSDave Liu */ 1116e080313cSDave Liu #define CSCONFIG_EN 0x80000000 1117e080313cSDave Liu #define CSCONFIG_AP 0x00800000 11188afad91fSGerlando Falauto #if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) 11192fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_NEVER 0x00000000 11202fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 11212fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 11222fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ALL 0x00400000 11232fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_NEVER 0x00000000 11242fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 11252fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 11262fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ALL 0x00040000 11272fef4020SJoe Hershberger #elif defined(CONFIG_MPC832x) 11282fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_CFG 0x00400000 11296d2c26acSHeiko Schocher #define CSCONFIG_ODT_WR_CFG 0x00040000 11302fef4020SJoe Hershberger #elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x) 11312fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_NEVER 0x00000000 11322fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 11332fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 11342fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000 11352fef4020SJoe Hershberger #define CSCONFIG_ODT_RD_ALL 0x00400000 11362fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_NEVER 0x00000000 11372fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 11382fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 11392fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000 11402fef4020SJoe Hershberger #define CSCONFIG_ODT_WR_ALL 0x00040000 11416d2c26acSHeiko Schocher #endif 1142d82b4fc0STor Krill #define CSCONFIG_BANK_BIT_3 0x00004000 1143e080313cSDave Liu #define CSCONFIG_ROW_BIT 0x00000700 1144e080313cSDave Liu #define CSCONFIG_ROW_BIT_12 0x00000000 1145e080313cSDave Liu #define CSCONFIG_ROW_BIT_13 0x00000100 1146e080313cSDave Liu #define CSCONFIG_ROW_BIT_14 0x00000200 1147e080313cSDave Liu #define CSCONFIG_COL_BIT 0x00000007 1148e080313cSDave Liu #define CSCONFIG_COL_BIT_8 0x00000000 1149e080313cSDave Liu #define CSCONFIG_COL_BIT_9 0x00000001 1150e080313cSDave Liu #define CSCONFIG_COL_BIT_10 0x00000002 1151e080313cSDave Liu #define CSCONFIG_COL_BIT_11 0x00000003 1152e080313cSDave Liu 11534e8b750cSHeiko Schocher /* 11544e8b750cSHeiko Schocher * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 1155d87c57b2SScott Wood */ 1156d87c57b2SScott Wood #define TIMING_CFG0_RWT 0xC0000000 1157d87c57b2SScott Wood #define TIMING_CFG0_RWT_SHIFT 30 1158d87c57b2SScott Wood #define TIMING_CFG0_WRT 0x30000000 1159d87c57b2SScott Wood #define TIMING_CFG0_WRT_SHIFT 28 1160d87c57b2SScott Wood #define TIMING_CFG0_RRT 0x0C000000 1161d87c57b2SScott Wood #define TIMING_CFG0_RRT_SHIFT 26 1162d87c57b2SScott Wood #define TIMING_CFG0_WWT 0x03000000 1163d87c57b2SScott Wood #define TIMING_CFG0_WWT_SHIFT 24 1164d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 1165d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 1166d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 1167d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 1168d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 1169d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 1170d892b2dbSAnton Vorontsov #define TIMING_CFG0_MRS_CYC 0x0000000F 1171d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC_SHIFT 0 1172d87c57b2SScott Wood 11734e8b750cSHeiko Schocher /* 11744e8b750cSHeiko Schocher * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 1175e080313cSDave Liu */ 1176e080313cSDave Liu #define TIMING_CFG1_PRETOACT 0x70000000 1177e080313cSDave Liu #define TIMING_CFG1_PRETOACT_SHIFT 28 1178e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE 0x0F000000 1179e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE_SHIFT 24 1180e080313cSDave Liu #define TIMING_CFG1_ACTTORW 0x00700000 1181e080313cSDave Liu #define TIMING_CFG1_ACTTORW_SHIFT 20 1182e080313cSDave Liu #define TIMING_CFG1_CASLAT 0x00070000 1183e080313cSDave Liu #define TIMING_CFG1_CASLAT_SHIFT 16 1184e080313cSDave Liu #define TIMING_CFG1_REFREC 0x0000F000 1185e080313cSDave Liu #define TIMING_CFG1_REFREC_SHIFT 12 1186e080313cSDave Liu #define TIMING_CFG1_WRREC 0x00000700 1187e080313cSDave Liu #define TIMING_CFG1_WRREC_SHIFT 8 1188e080313cSDave Liu #define TIMING_CFG1_ACTTOACT 0x00000070 1189e080313cSDave Liu #define TIMING_CFG1_ACTTOACT_SHIFT 4 1190e080313cSDave Liu #define TIMING_CFG1_WRTORD 0x00000007 1191e080313cSDave Liu #define TIMING_CFG1_WRTORD_SHIFT 0 1192e080313cSDave Liu #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 1193e080313cSDave Liu #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 1194facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ 1195facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ 1196facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ 11972b68b233SHeiko Schocher #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ 11982b68b233SHeiko Schocher #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ 1199e080313cSDave Liu 12004e8b750cSHeiko Schocher /* 12014e8b750cSHeiko Schocher * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 1202e080313cSDave Liu */ 12038d172c0fSXie Xiaobo #define TIMING_CFG2_CPO 0x0F800000 12048d172c0fSXie Xiaobo #define TIMING_CFG2_CPO_SHIFT 23 1205e080313cSDave Liu #define TIMING_CFG2_ACSM 0x00080000 1206e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 1207e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 12084e8b750cSHeiko Schocher /* default (= CASLAT + 1) */ 12094e8b750cSHeiko Schocher #define TIMING_CFG2_CPO_DEF 0x00000000 1210e080313cSDave Liu 1211d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT 0x70000000 1212d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT_SHIFT 28 1213d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 1214d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 1215d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE 0x0000E000 1216d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 1217d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS 0x000001C0 1218d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS_SHIFT 6 1219d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT 0x0000003F 1220d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT_SHIFT 0 1221d87c57b2SScott Wood 12224e8b750cSHeiko Schocher /* 1223f1ccd106SHeiko Schocher * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 1224f1ccd106SHeiko Schocher */ 1225f1ccd106SHeiko Schocher #define TIMING_CFG3_EXT_REFREC 0x00070000 1226f1ccd106SHeiko Schocher #define TIMING_CFG3_EXT_REFREC_SHIFT 16 1227f1ccd106SHeiko Schocher 1228f1ccd106SHeiko Schocher /* 12294e8b750cSHeiko Schocher * DDR_SDRAM_CFG - DDR SDRAM Control Configuration 1230e080313cSDave Liu */ 1231e080313cSDave Liu #define SDRAM_CFG_MEM_EN 0x80000000 1232e080313cSDave Liu #define SDRAM_CFG_SREN 0x40000000 1233e080313cSDave Liu #define SDRAM_CFG_ECC_EN 0x20000000 1234e080313cSDave Liu #define SDRAM_CFG_RD_EN 0x10000000 1235bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 1236bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 1237bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 1238e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 1239e080313cSDave Liu #define SDRAM_CFG_DYN_PWR 0x00200000 12402fef4020SJoe Hershberger #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) 12412fef4020SJoe Hershberger #define SDRAM_CFG_DBW_MASK 0x00180000 12422fef4020SJoe Hershberger #define SDRAM_CFG_DBW_16 0x00100000 12432fef4020SJoe Hershberger #define SDRAM_CFG_DBW_32 0x00080000 12442fef4020SJoe Hershberger #else 1245e080313cSDave Liu #define SDRAM_CFG_32_BE 0x00080000 12462fef4020SJoe Hershberger #endif 12472fef4020SJoe Hershberger #if !defined(CONFIG_MPC8308) 1248e080313cSDave Liu #define SDRAM_CFG_8_BE 0x00040000 12492fef4020SJoe Hershberger #endif 1250e080313cSDave Liu #define SDRAM_CFG_NCAP 0x00020000 1251e080313cSDave Liu #define SDRAM_CFG_2T_EN 0x00008000 1252a7b8126eSAndre Schwarz #define SDRAM_CFG_HSE 0x00000008 1253d87c57b2SScott Wood #define SDRAM_CFG_BI 0x00000001 1254e080313cSDave Liu 12554e8b750cSHeiko Schocher /* 12564e8b750cSHeiko Schocher * DDR_SDRAM_MODE - DDR SDRAM Mode Register 1257e080313cSDave Liu */ 1258e080313cSDave Liu #define SDRAM_MODE_ESD 0xFFFF0000 1259e080313cSDave Liu #define SDRAM_MODE_ESD_SHIFT 16 1260e080313cSDave Liu #define SDRAM_MODE_SD 0x0000FFFF 1261e080313cSDave Liu #define SDRAM_MODE_SD_SHIFT 0 12624e8b750cSHeiko Schocher /* select extended mode reg */ 12634e8b750cSHeiko Schocher #define DDR_MODE_EXT_MODEREG 0x4000 12644e8b750cSHeiko Schocher /* operating mode, mask */ 12654e8b750cSHeiko Schocher #define DDR_MODE_EXT_OPMODE 0x3FF8 1266e080313cSDave Liu #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 12674e8b750cSHeiko Schocher /* QFC / compatibility, mask */ 12684e8b750cSHeiko Schocher #define DDR_MODE_QFC 0x0004 12694e8b750cSHeiko Schocher /* compatible to older SDRAMs */ 12704e8b750cSHeiko Schocher #define DDR_MODE_QFC_COMP 0x0000 12714e8b750cSHeiko Schocher /* weak drivers */ 12724e8b750cSHeiko Schocher #define DDR_MODE_WEAK 0x0002 12734e8b750cSHeiko Schocher /* disable DLL */ 12744e8b750cSHeiko Schocher #define DDR_MODE_DLL_DIS 0x0001 12754e8b750cSHeiko Schocher /* CAS latency, mask */ 12764e8b750cSHeiko Schocher #define DDR_MODE_CASLAT 0x0070 1277e080313cSDave Liu #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 1278e080313cSDave Liu #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 1279e080313cSDave Liu #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 1280e080313cSDave Liu #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 12814e8b750cSHeiko Schocher /* sequential burst */ 12824e8b750cSHeiko Schocher #define DDR_MODE_BTYPE_SEQ 0x0000 12834e8b750cSHeiko Schocher /* interleaved burst */ 12844e8b750cSHeiko Schocher #define DDR_MODE_BTYPE_ILVD 0x0008 1285e080313cSDave Liu #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 1286e080313cSDave Liu #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 12874e8b750cSHeiko Schocher /* exact value for 7.8125us */ 12884e8b750cSHeiko Schocher #define DDR_REFINT_166MHZ_7US 1302 12894e8b750cSHeiko Schocher /* use 256 cycles as a starting point */ 12904e8b750cSHeiko Schocher #define DDR_BSTOPRE 256 12914e8b750cSHeiko Schocher /* select mode register */ 12924e8b750cSHeiko Schocher #define DDR_MODE_MODEREG 0x0000 1293e080313cSDave Liu 12944e8b750cSHeiko Schocher /* 12954e8b750cSHeiko Schocher * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 1296e080313cSDave Liu */ 1297e080313cSDave Liu #define SDRAM_INTERVAL_REFINT 0x3FFF0000 1298e080313cSDave Liu #define SDRAM_INTERVAL_REFINT_SHIFT 16 1299e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 1300e080313cSDave Liu 13014e8b750cSHeiko Schocher /* 13024e8b750cSHeiko Schocher * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 1303e080313cSDave Liu */ 1304e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 1305e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 1306e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 1307e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 1308e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 1309e080313cSDave Liu 13104e8b750cSHeiko Schocher /* 13114e8b750cSHeiko Schocher * ECC_ERR_INJECT - Memory data path error injection mask ECC 1312e080313cSDave Liu */ 13134e8b750cSHeiko Schocher /* ECC Mirror Byte */ 13144e8b750cSHeiko Schocher #define ECC_ERR_INJECT_EMB (0x80000000 >> 22) 13154e8b750cSHeiko Schocher /* Error Injection Enable */ 13164e8b750cSHeiko Schocher #define ECC_ERR_INJECT_EIEN (0x80000000 >> 23) 13174e8b750cSHeiko Schocher /* ECC Erroe Injection Enable */ 13184e8b750cSHeiko Schocher #define ECC_ERR_INJECT_EEIM (0xff000000 >> 24) 1319e080313cSDave Liu #define ECC_ERR_INJECT_EEIM_SHIFT 0 1320e080313cSDave Liu 13214e8b750cSHeiko Schocher /* 13224e8b750cSHeiko Schocher * CAPTURE_ECC - Memory data path read capture ECC 1323e080313cSDave Liu */ 1324e080313cSDave Liu #define CAPTURE_ECC_ECE (0xff000000 >> 24) 1325e080313cSDave Liu #define CAPTURE_ECC_ECE_SHIFT 0 1326e080313cSDave Liu 13274e8b750cSHeiko Schocher /* 13284e8b750cSHeiko Schocher * ERR_DETECT - Memory error detect 1329e080313cSDave Liu */ 13304e8b750cSHeiko Schocher /* Multiple Memory Errors */ 13314e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_MME (0x80000000 >> 0) 13324e8b750cSHeiko Schocher /* Multiple-Bit Error */ 13334e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_MBE (0x80000000 >> 28) 13344e8b750cSHeiko Schocher /* Single-Bit ECC Error Pickup */ 13354e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_SBE (0x80000000 >> 29) 13364e8b750cSHeiko Schocher /* Memory Select Error */ 13374e8b750cSHeiko Schocher #define ECC_ERROR_DETECT_MSE (0x80000000 >> 31) 1338e080313cSDave Liu 13394e8b750cSHeiko Schocher /* 13404e8b750cSHeiko Schocher * ERR_DISABLE - Memory error disable 1341e080313cSDave Liu */ 13424e8b750cSHeiko Schocher /* Multiple-Bit ECC Error Disable */ 13434e8b750cSHeiko Schocher #define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28) 13444e8b750cSHeiko Schocher /* Sinle-Bit ECC Error disable */ 13454e8b750cSHeiko Schocher #define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29) 13464e8b750cSHeiko Schocher /* Memory Select Error Disable */ 13474e8b750cSHeiko Schocher #define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31) 13484e8b750cSHeiko Schocher #define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \ 13494e8b750cSHeiko Schocher ECC_ERROR_DISABLE_SBED | \ 13504e8b750cSHeiko Schocher ECC_ERROR_DISABLE_MBED)) 13514e8b750cSHeiko Schocher 13524e8b750cSHeiko Schocher /* 13534e8b750cSHeiko Schocher * ERR_INT_EN - Memory error interrupt enable 1354e080313cSDave Liu */ 13554e8b750cSHeiko Schocher /* Multiple-Bit ECC Error Interrupt Enable */ 13564e8b750cSHeiko Schocher #define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28) 13574e8b750cSHeiko Schocher /* Single-Bit ECC Error Interrupt Enable */ 13584e8b750cSHeiko Schocher #define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29) 13594e8b750cSHeiko Schocher /* Memory Select Error Interrupt Enable */ 13604e8b750cSHeiko Schocher #define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31) 13614e8b750cSHeiko Schocher #define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \ 13624e8b750cSHeiko Schocher ECC_ERR_INT_EN_SBEE | \ 13634e8b750cSHeiko Schocher ECC_ERR_INT_EN_MSEE)) 13644e8b750cSHeiko Schocher 13654e8b750cSHeiko Schocher /* 13664e8b750cSHeiko Schocher * CAPTURE_ATTRIBUTES - Memory error attributes capture 1367e080313cSDave Liu */ 13684e8b750cSHeiko Schocher /* Data Beat Num */ 13694e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1) 1370e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM_SHIFT 28 13714e8b750cSHeiko Schocher /* Transaction Size */ 13724e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6) 1373e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 1374e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 1375e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1376e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1377e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 13784e8b750cSHeiko Schocher /* Transaction Source */ 13794e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11) 1380e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1381e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1382e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1383e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1384e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1385e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1386e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1387e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1388e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1389e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1390e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1391e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_SHIFT 16 13924e8b750cSHeiko Schocher /* Transaction Type */ 13934e8b750cSHeiko Schocher #define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18) 1394e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1395e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_READ 0x2 1396e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1397e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1398e080313cSDave Liu #define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */ 1399e080313cSDave Liu 14004e8b750cSHeiko Schocher /* 14014e8b750cSHeiko Schocher * ERR_SBE - Single bit ECC memory error management 1402e080313cSDave Liu */ 14034e8b750cSHeiko Schocher /* Single-Bit Error Threshold 0..255 */ 14044e8b750cSHeiko Schocher #define ECC_ERROR_MAN_SBET (0xff000000 >> 8) 1405e080313cSDave Liu #define ECC_ERROR_MAN_SBET_SHIFT 16 14064e8b750cSHeiko Schocher /* Single Bit Error Counter 0..255 */ 14074e8b750cSHeiko Schocher #define ECC_ERROR_MAN_SBEC (0xff000000 >> 24) 1408e080313cSDave Liu #define ECC_ERROR_MAN_SBEC_SHIFT 0 1409e080313cSDave Liu 14104e8b750cSHeiko Schocher /* 14114e8b750cSHeiko Schocher * CONFIG_ADDRESS - PCI Config Address Register 1412e080313cSDave Liu */ 1413e080313cSDave Liu #define PCI_CONFIG_ADDRESS_EN 0x80000000 1414e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1415e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1416e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1417e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1418e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1419e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1420e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1421e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1422e080313cSDave Liu 14234e8b750cSHeiko Schocher /* 14244e8b750cSHeiko Schocher * POTAR - PCI Outbound Translation Address Register 1425e080313cSDave Liu */ 1426e080313cSDave Liu #define POTAR_TA_MASK 0x000fffff 1427e080313cSDave Liu 14284e8b750cSHeiko Schocher /* 14294e8b750cSHeiko Schocher * POBAR - PCI Outbound Base Address Register 1430e080313cSDave Liu */ 1431e080313cSDave Liu #define POBAR_BA_MASK 0x000fffff 1432e080313cSDave Liu 14334e8b750cSHeiko Schocher /* 14344e8b750cSHeiko Schocher * POCMR - PCI Outbound Comparision Mask Register 1435e080313cSDave Liu */ 1436e080313cSDave Liu #define POCMR_EN 0x80000000 14374e8b750cSHeiko Schocher /* 0-memory space 1-I/O space */ 14384e8b750cSHeiko Schocher #define POCMR_IO 0x40000000 1439e080313cSDave Liu #define POCMR_SE 0x20000000 /* streaming enable */ 1440e080313cSDave Liu #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1441e080313cSDave Liu #define POCMR_CM_MASK 0x000fffff 1442e080313cSDave Liu #define POCMR_CM_4G 0x00000000 1443e080313cSDave Liu #define POCMR_CM_2G 0x00080000 1444e080313cSDave Liu #define POCMR_CM_1G 0x000C0000 1445e080313cSDave Liu #define POCMR_CM_512M 0x000E0000 1446e080313cSDave Liu #define POCMR_CM_256M 0x000F0000 1447e080313cSDave Liu #define POCMR_CM_128M 0x000F8000 1448e080313cSDave Liu #define POCMR_CM_64M 0x000FC000 1449e080313cSDave Liu #define POCMR_CM_32M 0x000FE000 1450e080313cSDave Liu #define POCMR_CM_16M 0x000FF000 1451e080313cSDave Liu #define POCMR_CM_8M 0x000FF800 1452e080313cSDave Liu #define POCMR_CM_4M 0x000FFC00 1453e080313cSDave Liu #define POCMR_CM_2M 0x000FFE00 1454e080313cSDave Liu #define POCMR_CM_1M 0x000FFF00 1455e080313cSDave Liu #define POCMR_CM_512K 0x000FFF80 1456e080313cSDave Liu #define POCMR_CM_256K 0x000FFFC0 1457e080313cSDave Liu #define POCMR_CM_128K 0x000FFFE0 1458e080313cSDave Liu #define POCMR_CM_64K 0x000FFFF0 1459e080313cSDave Liu #define POCMR_CM_32K 0x000FFFF8 1460e080313cSDave Liu #define POCMR_CM_16K 0x000FFFFC 1461e080313cSDave Liu #define POCMR_CM_8K 0x000FFFFE 1462e080313cSDave Liu #define POCMR_CM_4K 0x000FFFFF 1463e080313cSDave Liu 14644e8b750cSHeiko Schocher /* 14654e8b750cSHeiko Schocher * PITAR - PCI Inbound Translation Address Register 1466e080313cSDave Liu */ 1467e080313cSDave Liu #define PITAR_TA_MASK 0x000fffff 1468e080313cSDave Liu 14694e8b750cSHeiko Schocher /* 14704e8b750cSHeiko Schocher * PIBAR - PCI Inbound Base/Extended Address Register 1471e080313cSDave Liu */ 1472e080313cSDave Liu #define PIBAR_MASK 0xffffffff 1473e080313cSDave Liu #define PIEBAR_EBA_MASK 0x000fffff 1474e080313cSDave Liu 14754e8b750cSHeiko Schocher /* 14764e8b750cSHeiko Schocher * PIWAR - PCI Inbound Windows Attributes Register 1477e080313cSDave Liu */ 1478e080313cSDave Liu #define PIWAR_EN 0x80000000 1479e080313cSDave Liu #define PIWAR_PF 0x20000000 1480e080313cSDave Liu #define PIWAR_RTT_MASK 0x000f0000 1481e080313cSDave Liu #define PIWAR_RTT_NO_SNOOP 0x00040000 1482e080313cSDave Liu #define PIWAR_RTT_SNOOP 0x00050000 1483e080313cSDave Liu #define PIWAR_WTT_MASK 0x0000f000 1484e080313cSDave Liu #define PIWAR_WTT_NO_SNOOP 0x00004000 1485e080313cSDave Liu #define PIWAR_WTT_SNOOP 0x00005000 1486e080313cSDave Liu #define PIWAR_IWS_MASK 0x0000003F 1487e080313cSDave Liu #define PIWAR_IWS_4K 0x0000000B 1488e080313cSDave Liu #define PIWAR_IWS_8K 0x0000000C 1489e080313cSDave Liu #define PIWAR_IWS_16K 0x0000000D 1490e080313cSDave Liu #define PIWAR_IWS_32K 0x0000000E 1491e080313cSDave Liu #define PIWAR_IWS_64K 0x0000000F 1492e080313cSDave Liu #define PIWAR_IWS_128K 0x00000010 1493e080313cSDave Liu #define PIWAR_IWS_256K 0x00000011 1494e080313cSDave Liu #define PIWAR_IWS_512K 0x00000012 1495e080313cSDave Liu #define PIWAR_IWS_1M 0x00000013 1496e080313cSDave Liu #define PIWAR_IWS_2M 0x00000014 1497e080313cSDave Liu #define PIWAR_IWS_4M 0x00000015 1498e080313cSDave Liu #define PIWAR_IWS_8M 0x00000016 1499e080313cSDave Liu #define PIWAR_IWS_16M 0x00000017 1500e080313cSDave Liu #define PIWAR_IWS_32M 0x00000018 1501e080313cSDave Liu #define PIWAR_IWS_64M 0x00000019 1502e080313cSDave Liu #define PIWAR_IWS_128M 0x0000001A 1503e080313cSDave Liu #define PIWAR_IWS_256M 0x0000001B 1504e080313cSDave Liu #define PIWAR_IWS_512M 0x0000001C 1505e080313cSDave Liu #define PIWAR_IWS_1G 0x0000001D 1506e080313cSDave Liu #define PIWAR_IWS_2G 0x0000001E 1507f6eda7f8SDave Liu 15084e8b750cSHeiko Schocher /* 15094e8b750cSHeiko Schocher * PMCCR1 - PCI Configuration Register 1 1510d87c57b2SScott Wood */ 1511d87c57b2SScott Wood #define PMCCR1_POWER_OFF 0x00000020 1512d87c57b2SScott Wood 15134e8b750cSHeiko Schocher /* 15144e8b750cSHeiko Schocher * DDRCDR - DDR Control Driver Register 1515d87c57b2SScott Wood */ 15169e896478SKim Phillips #define DDRCDR_DHC_EN 0x80000000 1517d87c57b2SScott Wood #define DDRCDR_EN 0x40000000 1518d87c57b2SScott Wood #define DDRCDR_PZ 0x3C000000 1519d87c57b2SScott Wood #define DDRCDR_PZ_MAXZ 0x00000000 1520d87c57b2SScott Wood #define DDRCDR_PZ_HIZ 0x20000000 1521d87c57b2SScott Wood #define DDRCDR_PZ_NOMZ 0x30000000 1522d87c57b2SScott Wood #define DDRCDR_PZ_LOZ 0x38000000 1523d87c57b2SScott Wood #define DDRCDR_PZ_MINZ 0x3C000000 1524d87c57b2SScott Wood #define DDRCDR_NZ 0x3C000000 1525d87c57b2SScott Wood #define DDRCDR_NZ_MAXZ 0x00000000 1526d87c57b2SScott Wood #define DDRCDR_NZ_HIZ 0x02000000 1527d87c57b2SScott Wood #define DDRCDR_NZ_NOMZ 0x03000000 1528d87c57b2SScott Wood #define DDRCDR_NZ_LOZ 0x03800000 1529d87c57b2SScott Wood #define DDRCDR_NZ_MINZ 0x03C00000 1530d87c57b2SScott Wood #define DDRCDR_ODT 0x00080000 1531d87c57b2SScott Wood #define DDRCDR_DDR_CFG 0x00040000 1532d87c57b2SScott Wood #define DDRCDR_M_ODR 0x00000002 1533d87c57b2SScott Wood #define DDRCDR_Q_DRN 0x00000001 1534d87c57b2SScott Wood 15354e8b750cSHeiko Schocher /* 15364e8b750cSHeiko Schocher * PCIE Bridge Register 1537fd6646c0SAnton Vorontsov */ 1538fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_OBPIOE 0x00000001 1539fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_IBPIOE 0x00000002 1540fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_WDMAE 0x00000004 1541fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_RDMAE 0x00000008 1542fd6646c0SAnton Vorontsov 1543fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_PIOE 0x00000001 1544fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_MEMWE 0x00000002 1545fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_IOWE 0x00000004 1546fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_CFGWE 0x00000008 1547fd6646c0SAnton Vorontsov 1548fd6646c0SAnton Vorontsov #define PEX_CSB_IBCTRL_PIOE 0x00000001 1549fd6646c0SAnton Vorontsov 1550fd6646c0SAnton Vorontsov #define PEX_OWAR_EN 0x00000001 1551fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_CFG 0x00000000 1552fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_IO 0x00000002 1553fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_MEM 0x00000004 1554fd6646c0SAnton Vorontsov #define PEX_OWAR_RLXO 0x00000008 1555fd6646c0SAnton Vorontsov #define PEX_OWAR_NANP 0x00000010 1556fd6646c0SAnton Vorontsov #define PEX_OWAR_SIZE 0xFFFFF000 1557fd6646c0SAnton Vorontsov 1558fd6646c0SAnton Vorontsov #define PEX_IWAR_EN 0x00000001 1559fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_INT 0x00000000 1560fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_PF 0x00000004 1561fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_NO_PF 0x00000006 1562fd6646c0SAnton Vorontsov #define PEX_IWAR_NSOV 0x00000008 1563fd6646c0SAnton Vorontsov #define PEX_IWAR_NSNP 0x00000010 1564fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE 0xFFFFF000 1565fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_1M 0x000FF000 1566fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_2M 0x001FF000 1567fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_4M 0x003FF000 1568fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_8M 0x007FF000 1569fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_16M 0x00FFF000 1570fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_32M 0x01FFF000 1571fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_64M 0x03FFF000 1572fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_128M 0x07FFF000 1573fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_256M 0x0FFFF000 1574fd6646c0SAnton Vorontsov 1575fd6646c0SAnton Vorontsov #define PEX_GCLK_RATIO 0x440 1576fd6646c0SAnton Vorontsov 157749ea3b6eSScott Wood #ifndef __ASSEMBLY__ 157849ea3b6eSScott Wood struct pci_region; 15796aa3d3bfSPeter Tyser void mpc83xx_pci_init(int num_buses, struct pci_region **reg); 158075f35209SIra Snyder void mpc83xx_pcislave_unlock(int bus); 15816aa3d3bfSPeter Tyser void mpc83xx_pcie_init(int num_buses, struct pci_region **reg); 158249ea3b6eSScott Wood #endif 158349ea3b6eSScott Wood 1584f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 1585