1f046ccd1SEran Liberty /* 2*7c619ddcSIlya Yanok * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty */ 12f046ccd1SEran Liberty 13f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 14f046ccd1SEran Liberty #define __MPC83XX_H__ 15f046ccd1SEran Liberty 16f6eda7f8SDave Liu #include <config.h> 17bf30bb1fSAnton Vorontsov #include <asm/fsl_lbc.h> 18f046ccd1SEran Liberty #if defined(CONFIG_E300) 19f046ccd1SEran Liberty #include <asm/e300.h> 20f046ccd1SEran Liberty #endif 21f046ccd1SEran Liberty 22e080313cSDave Liu /* MPC83xx cpu provide RCR register to do reset thing specially 23f046ccd1SEran Liberty */ 24f046ccd1SEran Liberty #define MPC83xx_RESET 25f046ccd1SEran Liberty 26e080313cSDave Liu /* System reset offset (PowerPC standard) 27f046ccd1SEran Liberty */ 28f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 2902032e8fSRafal Jaworowski #define _START_OFFSET EXC_OFF_SYS_RESET 30f046ccd1SEran Liberty 31e080313cSDave Liu /* IMMRBAR - Internal Memory Register Base Address 32f046ccd1SEran Liberty */ 33e4c09508SScott Wood #ifndef CONFIG_DEFAULT_IMMR 34e080313cSDave Liu #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 35e4c09508SScott Wood #endif 36e080313cSDave Liu #define IMMRBAR 0x0000 /* Register offset to immr */ 37e080313cSDave Liu #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 38f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 39f046ccd1SEran Liberty 40e080313cSDave Liu /* LAWBAR - Local Access Window Base Address Register 41f046ccd1SEran Liberty */ 42e080313cSDave Liu #define LBLAWBAR0 0x0020 /* Register offset to immr */ 43f046ccd1SEran Liberty #define LBLAWAR0 0x0024 44f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 45f046ccd1SEran Liberty #define LBLAWAR1 0x002C 46f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 47f046ccd1SEran Liberty #define LBLAWAR2 0x0034 48f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 49f046ccd1SEran Liberty #define LBLAWAR3 0x003C 50e080313cSDave Liu #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 51f046ccd1SEran Liberty 52e080313cSDave Liu /* SPRIDR - System Part and Revision ID Register 53f6eda7f8SDave Liu */ 54e5c4ade4SKim Phillips #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ 55e5c4ade4SKim Phillips #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ 56e080313cSDave Liu 572c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 58e5c4ade4SKim Phillips #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) 59e5c4ade4SKim Phillips #define REVID_MINOR(spridr) (spridr & 0x000000FF) 60e5c4ade4SKim Phillips #else 61e5c4ade4SKim Phillips #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) 62e5c4ade4SKim Phillips #define REVID_MINOR(spridr) (spridr & 0x0000000F) 63e5c4ade4SKim Phillips #endif 645f820439SDave Liu 65e5c4ade4SKim Phillips #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) 666b70ffb9SKim Phillips #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) 675f820439SDave Liu 68*7c619ddcSIlya Yanok #define SPR_8308 0x8100 696b70ffb9SKim Phillips #define SPR_831X_FAMILY 0x80B 70e5c4ade4SKim Phillips #define SPR_8311 0x80B2 71e5c4ade4SKim Phillips #define SPR_8313 0x80B0 72e5c4ade4SKim Phillips #define SPR_8314 0x80B6 73e5c4ade4SKim Phillips #define SPR_8315 0x80B4 746b70ffb9SKim Phillips #define SPR_832X_FAMILY 0x806 75e5c4ade4SKim Phillips #define SPR_8321 0x8066 76e5c4ade4SKim Phillips #define SPR_8323 0x8062 776b70ffb9SKim Phillips #define SPR_834X_FAMILY 0x803 78e5c4ade4SKim Phillips #define SPR_8343 0x8036 79e5c4ade4SKim Phillips #define SPR_8347_TBGA_ 0x8032 80e5c4ade4SKim Phillips #define SPR_8347_PBGA_ 0x8034 81e5c4ade4SKim Phillips #define SPR_8349 0x8030 826b70ffb9SKim Phillips #define SPR_836X_FAMILY 0x804 83e5c4ade4SKim Phillips #define SPR_8358_TBGA_ 0x804A 84e5c4ade4SKim Phillips #define SPR_8358_PBGA_ 0x804E 85e5c4ade4SKim Phillips #define SPR_8360 0x8048 866b70ffb9SKim Phillips #define SPR_837X_FAMILY 0x80C 87e5c4ade4SKim Phillips #define SPR_8377 0x80C6 88e5c4ade4SKim Phillips #define SPR_8378 0x80C4 89e5c4ade4SKim Phillips #define SPR_8379 0x80C2 90d87c57b2SScott Wood 91e080313cSDave Liu /* SPCR - System Priority Configuration Register 92f046ccd1SEran Liberty */ 93e080313cSDave Liu #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 94e080313cSDave Liu #define SPCR_PCIHPE_SHIFT (31-3) 95e080313cSDave Liu #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 96e080313cSDave Liu #define SPCR_PCIPR_SHIFT (31-7) 97e080313cSDave Liu #define SPCR_OPT 0x00800000 /* Optimize */ 985bbeea86SMichael Barkowski #define SPCR_OPT_SHIFT (31-8) 99e080313cSDave Liu #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 100e080313cSDave Liu #define SPCR_TBEN_SHIFT (31-9) 101e080313cSDave Liu #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 102e080313cSDave Liu #define SPCR_COREPR_SHIFT (31-11) 103e080313cSDave Liu 1042c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 105e080313cSDave Liu /* SPCR bits - MPC8349 specific */ 106e080313cSDave Liu #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 107e080313cSDave Liu #define SPCR_TSEC1DP_SHIFT (31-19) 108e080313cSDave Liu #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 109e080313cSDave Liu #define SPCR_TSEC1BDP_SHIFT (31-21) 110e080313cSDave Liu #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 111e080313cSDave Liu #define SPCR_TSEC1EP_SHIFT (31-23) 112e080313cSDave Liu #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 113e080313cSDave Liu #define SPCR_TSEC2DP_SHIFT (31-27) 114e080313cSDave Liu #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 115e080313cSDave Liu #define SPCR_TSEC2BDP_SHIFT (31-29) 116e080313cSDave Liu #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 117e080313cSDave Liu #define SPCR_TSEC2EP_SHIFT (31-31) 118d87c57b2SScott Wood 119*7c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 120*7c619ddcSIlya Yanok defined(CONFIG_MPC837x) 121*7c619ddcSIlya Yanok /* SPCR bits - MPC8308, MPC831x and MPC837x specific */ 122d87c57b2SScott Wood #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 123d87c57b2SScott Wood #define SPCR_TSECDP_SHIFT (31-19) 124ec2638eaSDave Liu #define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */ 125ec2638eaSDave Liu #define SPCR_TSECBDP_SHIFT (31-21) 126ec2638eaSDave Liu #define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */ 127ec2638eaSDave Liu #define SPCR_TSECEP_SHIFT (31-23) 128e080313cSDave Liu #endif 129e080313cSDave Liu 130e080313cSDave Liu /* SICRL/H - System I/O Configuration Register Low/High 131e080313cSDave Liu */ 1322c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 133e080313cSDave Liu /* SICRL bits - MPC8349 specific */ 134e080313cSDave Liu #define SICRL_LDP_A 0x80000000 135e080313cSDave Liu #define SICRL_USB1 0x40000000 136e080313cSDave Liu #define SICRL_USB0 0x20000000 137e080313cSDave Liu #define SICRL_UART 0x0C000000 138e080313cSDave Liu #define SICRL_GPIO1_A 0x02000000 139e080313cSDave Liu #define SICRL_GPIO1_B 0x01000000 140e080313cSDave Liu #define SICRL_GPIO1_C 0x00800000 141e080313cSDave Liu #define SICRL_GPIO1_D 0x00400000 142e080313cSDave Liu #define SICRL_GPIO1_E 0x00200000 143e080313cSDave Liu #define SICRL_GPIO1_F 0x00180000 144e080313cSDave Liu #define SICRL_GPIO1_G 0x00040000 145e080313cSDave Liu #define SICRL_GPIO1_H 0x00020000 146e080313cSDave Liu #define SICRL_GPIO1_I 0x00010000 147e080313cSDave Liu #define SICRL_GPIO1_J 0x00008000 148e080313cSDave Liu #define SICRL_GPIO1_K 0x00004000 149e080313cSDave Liu #define SICRL_GPIO1_L 0x00003000 150e080313cSDave Liu 151e080313cSDave Liu /* SICRH bits - MPC8349 specific */ 152e080313cSDave Liu #define SICRH_DDR 0x80000000 153e080313cSDave Liu #define SICRH_TSEC1_A 0x10000000 154e080313cSDave Liu #define SICRH_TSEC1_B 0x08000000 155e080313cSDave Liu #define SICRH_TSEC1_C 0x04000000 156e080313cSDave Liu #define SICRH_TSEC1_D 0x02000000 157e080313cSDave Liu #define SICRH_TSEC1_E 0x01000000 158e080313cSDave Liu #define SICRH_TSEC1_F 0x00800000 159e080313cSDave Liu #define SICRH_TSEC2_A 0x00400000 160e080313cSDave Liu #define SICRH_TSEC2_B 0x00200000 161e080313cSDave Liu #define SICRH_TSEC2_C 0x00100000 162e080313cSDave Liu #define SICRH_TSEC2_D 0x00080000 163e080313cSDave Liu #define SICRH_TSEC2_E 0x00040000 164e080313cSDave Liu #define SICRH_TSEC2_F 0x00020000 165e080313cSDave Liu #define SICRH_TSEC2_G 0x00010000 166e080313cSDave Liu #define SICRH_TSEC2_H 0x00008000 167e080313cSDave Liu #define SICRH_GPIO2_A 0x00004000 168e080313cSDave Liu #define SICRH_GPIO2_B 0x00002000 169e080313cSDave Liu #define SICRH_GPIO2_C 0x00001000 170e080313cSDave Liu #define SICRH_GPIO2_D 0x00000800 171e080313cSDave Liu #define SICRH_GPIO2_E 0x00000400 172e080313cSDave Liu #define SICRH_GPIO2_F 0x00000200 173e080313cSDave Liu #define SICRH_GPIO2_G 0x00000180 174e080313cSDave Liu #define SICRH_GPIO2_H 0x00000060 175e080313cSDave Liu #define SICRH_TSOBI1 0x00000002 176e080313cSDave Liu #define SICRH_TSOBI2 0x00000001 177e080313cSDave Liu 178e080313cSDave Liu #elif defined(CONFIG_MPC8360) 179e080313cSDave Liu /* SICRL bits - MPC8360 specific */ 180e080313cSDave Liu #define SICRL_LDP_A 0xC0000000 181e080313cSDave Liu #define SICRL_LCLK_1 0x10000000 182e080313cSDave Liu #define SICRL_LCLK_2 0x08000000 183e080313cSDave Liu #define SICRL_SRCID_A 0x03000000 184e080313cSDave Liu #define SICRL_IRQ_CKSTP_A 0x00C00000 185e080313cSDave Liu 186e080313cSDave Liu /* SICRH bits - MPC8360 specific */ 187e080313cSDave Liu #define SICRH_DDR 0x80000000 188e080313cSDave Liu #define SICRH_SECONDARY_DDR 0x40000000 189e080313cSDave Liu #define SICRH_SDDROE 0x20000000 190e080313cSDave Liu #define SICRH_IRQ3 0x10000000 191e080313cSDave Liu #define SICRH_UC1EOBI 0x00000004 192e080313cSDave Liu #define SICRH_UC2E1OBI 0x00000002 193e080313cSDave Liu #define SICRH_UC2E2OBI 0x00000001 19424c3aca3SDave Liu 1952c7920afSPeter Tyser #elif defined(CONFIG_MPC832x) 1962c7920afSPeter Tyser /* SICRL bits - MPC832x specific */ 19724c3aca3SDave Liu #define SICRL_LDP_LCS_A 0x80000000 19824c3aca3SDave Liu #define SICRL_IRQ_CKS 0x20000000 19924c3aca3SDave Liu #define SICRL_PCI_MSRC 0x10000000 20024c3aca3SDave Liu #define SICRL_URT_CTPR 0x06000000 20124c3aca3SDave Liu #define SICRL_IRQ_CTPR 0x00C00000 202d87c57b2SScott Wood 203555da617SDave Liu #elif defined(CONFIG_MPC8313) 204555da617SDave Liu /* SICRL bits - MPC8313 specific */ 205d87c57b2SScott Wood #define SICRL_LBC 0x30000000 206d87c57b2SScott Wood #define SICRL_UART 0x0C000000 207d87c57b2SScott Wood #define SICRL_SPI_A 0x03000000 208d87c57b2SScott Wood #define SICRL_SPI_B 0x00C00000 209d87c57b2SScott Wood #define SICRL_SPI_C 0x00300000 210d87c57b2SScott Wood #define SICRL_SPI_D 0x000C0000 211f986325dSRon Madrid #define SICRL_USBDR_11 0x00000C00 212f986325dSRon Madrid #define SICRL_USBDR_10 0x00000800 213f986325dSRon Madrid #define SICRL_USBDR_01 0x00000400 214f986325dSRon Madrid #define SICRL_USBDR_00 0x00000000 215d87c57b2SScott Wood #define SICRL_ETSEC1_A 0x0000000C 216d87c57b2SScott Wood #define SICRL_ETSEC2_A 0x00000003 217d87c57b2SScott Wood 218555da617SDave Liu /* SICRH bits - MPC8313 specific */ 219d87c57b2SScott Wood #define SICRH_INTR_A 0x02000000 220d87c57b2SScott Wood #define SICRH_INTR_B 0x00C00000 221d87c57b2SScott Wood #define SICRH_IIC 0x00300000 222d87c57b2SScott Wood #define SICRH_ETSEC2_B 0x000C0000 223d87c57b2SScott Wood #define SICRH_ETSEC2_C 0x00030000 224d87c57b2SScott Wood #define SICRH_ETSEC2_D 0x0000C000 225d87c57b2SScott Wood #define SICRH_ETSEC2_E 0x00003000 226d87c57b2SScott Wood #define SICRH_ETSEC2_F 0x00000C00 227d87c57b2SScott Wood #define SICRH_ETSEC2_G 0x00000300 228d87c57b2SScott Wood #define SICRH_ETSEC1_B 0x00000080 229d87c57b2SScott Wood #define SICRH_ETSEC1_C 0x00000060 230d87c57b2SScott Wood #define SICRH_GTX1_DLY 0x00000008 231d87c57b2SScott Wood #define SICRH_GTX2_DLY 0x00000004 232d87c57b2SScott Wood #define SICRH_TSOBI1 0x00000002 233d87c57b2SScott Wood #define SICRH_TSOBI2 0x00000001 234d87c57b2SScott Wood 235555da617SDave Liu #elif defined(CONFIG_MPC8315) 236555da617SDave Liu /* SICRL bits - MPC8315 specific */ 237555da617SDave Liu #define SICRL_DMA_CH0 0xc0000000 238555da617SDave Liu #define SICRL_DMA_SPI 0x30000000 239555da617SDave Liu #define SICRL_UART 0x0c000000 240555da617SDave Liu #define SICRL_IRQ4 0x02000000 241555da617SDave Liu #define SICRL_IRQ5 0x01800000 242555da617SDave Liu #define SICRL_IRQ6_7 0x00400000 243555da617SDave Liu #define SICRL_IIC1 0x00300000 244555da617SDave Liu #define SICRL_TDM 0x000c0000 245555da617SDave Liu #define SICRL_TDM_SHARED 0x00030000 246555da617SDave Liu #define SICRL_PCI_A 0x0000c000 247555da617SDave Liu #define SICRL_ELBC_A 0x00003000 248555da617SDave Liu #define SICRL_ETSEC1_A 0x000000c0 249555da617SDave Liu #define SICRL_ETSEC1_B 0x00000030 250555da617SDave Liu #define SICRL_ETSEC1_C 0x0000000c 251555da617SDave Liu #define SICRL_TSEXPOBI 0x00000001 252555da617SDave Liu 253555da617SDave Liu /* SICRH bits - MPC8315 specific */ 254555da617SDave Liu #define SICRH_GPIO_0 0xc0000000 255555da617SDave Liu #define SICRH_GPIO_1 0x30000000 256555da617SDave Liu #define SICRH_GPIO_2 0x0c000000 257555da617SDave Liu #define SICRH_GPIO_3 0x03000000 258555da617SDave Liu #define SICRH_GPIO_4 0x00c00000 259555da617SDave Liu #define SICRH_GPIO_5 0x00300000 260555da617SDave Liu #define SICRH_GPIO_6 0x000c0000 261555da617SDave Liu #define SICRH_GPIO_7 0x00030000 262555da617SDave Liu #define SICRH_GPIO_8 0x0000c000 263555da617SDave Liu #define SICRH_GPIO_9 0x00003000 264555da617SDave Liu #define SICRH_GPIO_10 0x00000c00 265555da617SDave Liu #define SICRH_GPIO_11 0x00000300 266555da617SDave Liu #define SICRH_ETSEC2_A 0x000000c0 267555da617SDave Liu #define SICRH_TSOBI1 0x00000002 268555da617SDave Liu #define SICRH_TSOBI2 0x00000001 269555da617SDave Liu 2702c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 27103051c3dSDave Liu /* SICRL bits - MPC837x specific */ 27203051c3dSDave Liu #define SICRL_USB_A 0xC0000000 27303051c3dSDave Liu #define SICRL_USB_B 0x30000000 274e1ac387fSAndy Fleming #define SICRL_USB_B_SD 0x20000000 27503051c3dSDave Liu #define SICRL_UART 0x0C000000 27603051c3dSDave Liu #define SICRL_GPIO_A 0x02000000 27703051c3dSDave Liu #define SICRL_GPIO_B 0x01000000 27803051c3dSDave Liu #define SICRL_GPIO_C 0x00800000 27903051c3dSDave Liu #define SICRL_GPIO_D 0x00400000 28003051c3dSDave Liu #define SICRL_GPIO_E 0x00200000 28103051c3dSDave Liu #define SICRL_GPIO_F 0x00180000 28203051c3dSDave Liu #define SICRL_GPIO_G 0x00040000 28303051c3dSDave Liu #define SICRL_GPIO_H 0x00020000 28403051c3dSDave Liu #define SICRL_GPIO_I 0x00010000 28503051c3dSDave Liu #define SICRL_GPIO_J 0x00008000 28603051c3dSDave Liu #define SICRL_GPIO_K 0x00004000 28703051c3dSDave Liu #define SICRL_GPIO_L 0x00003000 28803051c3dSDave Liu #define SICRL_DMA_A 0x00000800 28903051c3dSDave Liu #define SICRL_DMA_B 0x00000400 29003051c3dSDave Liu #define SICRL_DMA_C 0x00000200 29103051c3dSDave Liu #define SICRL_DMA_D 0x00000100 29203051c3dSDave Liu #define SICRL_DMA_E 0x00000080 29303051c3dSDave Liu #define SICRL_DMA_F 0x00000040 29403051c3dSDave Liu #define SICRL_DMA_G 0x00000020 29503051c3dSDave Liu #define SICRL_DMA_H 0x00000010 29603051c3dSDave Liu #define SICRL_DMA_I 0x00000008 29703051c3dSDave Liu #define SICRL_DMA_J 0x00000004 29803051c3dSDave Liu #define SICRL_LDP_A 0x00000002 29903051c3dSDave Liu #define SICRL_LDP_B 0x00000001 30003051c3dSDave Liu 30103051c3dSDave Liu /* SICRH bits - MPC837x specific */ 30203051c3dSDave Liu #define SICRH_DDR 0x80000000 30303051c3dSDave Liu #define SICRH_TSEC1_A 0x10000000 30403051c3dSDave Liu #define SICRH_TSEC1_B 0x08000000 30503051c3dSDave Liu #define SICRH_TSEC2_A 0x00400000 30603051c3dSDave Liu #define SICRH_TSEC2_B 0x00200000 30703051c3dSDave Liu #define SICRH_TSEC2_C 0x00100000 30803051c3dSDave Liu #define SICRH_TSEC2_D 0x00080000 30903051c3dSDave Liu #define SICRH_TSEC2_E 0x00040000 31003051c3dSDave Liu #define SICRH_TMR 0x00010000 31103051c3dSDave Liu #define SICRH_GPIO2_A 0x00008000 31203051c3dSDave Liu #define SICRH_GPIO2_B 0x00004000 31303051c3dSDave Liu #define SICRH_GPIO2_C 0x00002000 31403051c3dSDave Liu #define SICRH_GPIO2_D 0x00001000 31503051c3dSDave Liu #define SICRH_GPIO2_E 0x00000C00 316e1ac387fSAndy Fleming #define SICRH_GPIO2_E_SD 0x00000800 31703051c3dSDave Liu #define SICRH_GPIO2_F 0x00000300 31803051c3dSDave Liu #define SICRH_GPIO2_G 0x000000C0 31903051c3dSDave Liu #define SICRH_GPIO2_H 0x00000030 32003051c3dSDave Liu #define SICRH_SPI 0x00000003 321e1ac387fSAndy Fleming #define SICRH_SPI_SD 0x00000001 322e080313cSDave Liu #endif 323e080313cSDave Liu 324e080313cSDave Liu /* SWCRR - System Watchdog Control Register 325e080313cSDave Liu */ 326e080313cSDave Liu #define SWCRR 0x0204 /* Register offset to immr */ 327e080313cSDave Liu #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 328e080313cSDave Liu #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 329e080313cSDave Liu #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 330e080313cSDave Liu #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 331e080313cSDave Liu #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 332e080313cSDave Liu 333e080313cSDave Liu /* SWCNR - System Watchdog Counter Register 334e080313cSDave Liu */ 335e080313cSDave Liu #define SWCNR 0x0208 /* Register offset to immr */ 336e080313cSDave Liu #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 337e080313cSDave Liu #define SWCNR_RES ~(SWCNR_SWCN) 338e080313cSDave Liu 339e080313cSDave Liu /* SWSRR - System Watchdog Service Register 340e080313cSDave Liu */ 341e080313cSDave Liu #define SWSRR 0x020E /* Register offset to immr */ 342e080313cSDave Liu 343e080313cSDave Liu /* ACR - Arbiter Configuration Register 344e080313cSDave Liu */ 345e080313cSDave Liu #define ACR_COREDIS 0x10000000 /* Core disable */ 346e080313cSDave Liu #define ACR_COREDIS_SHIFT (31-7) 347e080313cSDave Liu #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 348e080313cSDave Liu #define ACR_PIPE_DEP_SHIFT (31-15) 349e080313cSDave Liu #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 350e080313cSDave Liu #define ACR_PCI_RPTCNT_SHIFT (31-19) 351e080313cSDave Liu #define ACR_RPTCNT 0x00000700 /* Repeat count */ 352e080313cSDave Liu #define ACR_RPTCNT_SHIFT (31-23) 353e080313cSDave Liu #define ACR_APARK 0x00000030 /* Address parking */ 354e080313cSDave Liu #define ACR_APARK_SHIFT (31-27) 355e080313cSDave Liu #define ACR_PARKM 0x0000000F /* Parking master */ 356e080313cSDave Liu #define ACR_PARKM_SHIFT (31-31) 357e080313cSDave Liu 358e080313cSDave Liu /* ATR - Arbiter Timers Register 359e080313cSDave Liu */ 360e080313cSDave Liu #define ATR_DTO 0x00FF0000 /* Data time out */ 361002d27caSNick Spence #define ATR_DTO_SHIFT 16 362e080313cSDave Liu #define ATR_ATO 0x000000FF /* Address time out */ 363002d27caSNick Spence #define ATR_ATO_SHIFT 0 364e080313cSDave Liu 365e080313cSDave Liu /* AER - Arbiter Event Register 366e080313cSDave Liu */ 367e080313cSDave Liu #define AER_ETEA 0x00000020 /* Transfer error */ 368e080313cSDave Liu #define AER_RES 0x00000010 /* Reserved transfer type */ 369e080313cSDave Liu #define AER_ECW 0x00000008 /* External control word transfer type */ 370e080313cSDave Liu #define AER_AO 0x00000004 /* Address Only transfer type */ 371e080313cSDave Liu #define AER_DTO 0x00000002 /* Data time out */ 372e080313cSDave Liu #define AER_ATO 0x00000001 /* Address time out */ 373e080313cSDave Liu 374e080313cSDave Liu /* AEATR - Arbiter Event Address Register 375e080313cSDave Liu */ 376e080313cSDave Liu #define AEATR_EVENT 0x07000000 /* Event type */ 377002d27caSNick Spence #define AEATR_EVENT_SHIFT 24 378e080313cSDave Liu #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 379002d27caSNick Spence #define AEATR_MSTR_ID_SHIFT 16 380e080313cSDave Liu #define AEATR_TBST 0x00000800 /* Transfer burst */ 381002d27caSNick Spence #define AEATR_TBST_SHIFT 11 382e080313cSDave Liu #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 383002d27caSNick Spence #define AEATR_TSIZE_SHIFT 8 384e080313cSDave Liu #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 385002d27caSNick Spence #define AEATR_TTYPE_SHIFT 0 386e080313cSDave Liu 387e080313cSDave Liu /* HRCWL - Hard Reset Configuration Word Low 388e080313cSDave Liu */ 389e080313cSDave Liu #define HRCWL_LBIUCM 0x80000000 390e080313cSDave Liu #define HRCWL_LBIUCM_SHIFT 31 391e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 392e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 393e080313cSDave Liu 394e080313cSDave Liu #define HRCWL_DDRCM 0x40000000 395e080313cSDave Liu #define HRCWL_DDRCM_SHIFT 30 396e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 397e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 398e080313cSDave Liu 399e080313cSDave Liu #define HRCWL_SPMF 0x0f000000 400e080313cSDave Liu #define HRCWL_SPMF_SHIFT 24 401e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 402e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 403e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 404e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 405e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 406e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 407e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 408e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 409e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 410e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 411e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 412e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 413e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 414e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 415e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 416e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 417e080313cSDave Liu 418e080313cSDave Liu #define HRCWL_VCO_BYPASS 0x00000000 419e080313cSDave Liu #define HRCWL_VCO_1X2 0x00000000 420e080313cSDave Liu #define HRCWL_VCO_1X4 0x00200000 421e080313cSDave Liu #define HRCWL_VCO_1X8 0x00400000 422e080313cSDave Liu 423e080313cSDave Liu #define HRCWL_COREPLL 0x007F0000 424e080313cSDave Liu #define HRCWL_COREPLL_SHIFT 16 425e080313cSDave Liu #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 426e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1X1 0x00020000 427e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 428e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2X1 0x00040000 429e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 430e080313cSDave Liu #define HRCWL_CORE_TO_CSB_3X1 0x00060000 431e080313cSDave Liu 4322c7920afSPeter Tyser #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x) 433e080313cSDave Liu #define HRCWL_CEVCOD 0x000000C0 434e080313cSDave Liu #define HRCWL_CEVCOD_SHIFT 6 435e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 436e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 437e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 438e080313cSDave Liu 439e080313cSDave Liu #define HRCWL_CEPDF 0x00000020 440e080313cSDave Liu #define HRCWL_CEPDF_SHIFT 5 441e080313cSDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 442e080313cSDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 443e080313cSDave Liu 444e080313cSDave Liu #define HRCWL_CEPMF 0x0000001F 445e080313cSDave Liu #define HRCWL_CEPMF_SHIFT 0 446e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 447e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 448e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 449e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 450e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 451e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 452e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 453e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 454e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 455e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 456e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 457e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 458e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 459e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 460e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 461e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 462e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 463e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 464e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 465e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 466e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 467e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 468e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 469e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 470e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 471e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 472e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 473e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 474e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 475e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 476e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 47703051c3dSDave Liu 478*7c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 4796f3931a2SDave Liu #define HRCWL_SVCOD 0x30000000 4806f3931a2SDave Liu #define HRCWL_SVCOD_SHIFT 28 4816f3931a2SDave Liu #define HRCWL_SVCOD_DIV_2 0x00000000 4826f3931a2SDave Liu #define HRCWL_SVCOD_DIV_4 0x10000000 4836f3931a2SDave Liu #define HRCWL_SVCOD_DIV_8 0x20000000 4846f3931a2SDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 4856f3931a2SDave Liu 4862c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 48703051c3dSDave Liu #define HRCWL_SVCOD 0x30000000 48803051c3dSDave Liu #define HRCWL_SVCOD_SHIFT 28 48903051c3dSDave Liu #define HRCWL_SVCOD_DIV_4 0x00000000 49003051c3dSDave Liu #define HRCWL_SVCOD_DIV_8 0x10000000 49103051c3dSDave Liu #define HRCWL_SVCOD_DIV_2 0x20000000 49203051c3dSDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 493e080313cSDave Liu #endif 494e080313cSDave Liu 495e080313cSDave Liu /* HRCWH - Hardware Reset Configuration Word High 496e080313cSDave Liu */ 497e080313cSDave Liu #define HRCWH_PCI_HOST 0x80000000 498e080313cSDave Liu #define HRCWH_PCI_HOST_SHIFT 31 499e080313cSDave Liu #define HRCWH_PCI_AGENT 0x00000000 500e080313cSDave Liu 5012c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 502e080313cSDave Liu #define HRCWH_32_BIT_PCI 0x00000000 503e080313cSDave Liu #define HRCWH_64_BIT_PCI 0x40000000 504e080313cSDave Liu #endif 505e080313cSDave Liu 506e080313cSDave Liu #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 507e080313cSDave Liu #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 508e080313cSDave Liu 509e080313cSDave Liu #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 510e080313cSDave Liu #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 511e080313cSDave Liu 5122c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 513e080313cSDave Liu #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 514e080313cSDave Liu #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 515e080313cSDave Liu 516e080313cSDave Liu #elif defined(CONFIG_MPC8360) 517e080313cSDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 518e080313cSDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 519e080313cSDave Liu #endif 520e080313cSDave Liu 521e080313cSDave Liu #define HRCWH_CORE_DISABLE 0x08000000 522e080313cSDave Liu #define HRCWH_CORE_ENABLE 0x00000000 523e080313cSDave Liu 524e080313cSDave Liu #define HRCWH_FROM_0X00000100 0x00000000 525e080313cSDave Liu #define HRCWH_FROM_0XFFF00100 0x04000000 526e080313cSDave Liu 527e080313cSDave Liu #define HRCWH_BOOTSEQ_DISABLE 0x00000000 528e080313cSDave Liu #define HRCWH_BOOTSEQ_NORMAL 0x01000000 529e080313cSDave Liu #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 530e080313cSDave Liu 531e080313cSDave Liu #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 532e080313cSDave Liu #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 533e080313cSDave Liu 534e080313cSDave Liu #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 535e080313cSDave Liu #define HRCWH_ROM_LOC_PCI1 0x00100000 5362c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 537e080313cSDave Liu #define HRCWH_ROM_LOC_PCI2 0x00200000 538e080313cSDave Liu #endif 5392c7920afSPeter Tyser #if defined(CONFIG_MPC837x) 54003051c3dSDave Liu #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 54103051c3dSDave Liu #endif 542e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 543e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 544e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 545e080313cSDave Liu 546*7c619ddcSIlya Yanok #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 547*7c619ddcSIlya Yanok defined(CONFIG_MPC837x) 548d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 549d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 550d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 551d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 552d87c57b2SScott Wood 553d87c57b2SScott Wood #define HRCWH_RL_EXT_LEGACY 0x00000000 554d87c57b2SScott Wood #define HRCWH_RL_EXT_NAND 0x00040000 555d87c57b2SScott Wood 556e6d9c891SAnton Vorontsov #define HRCWH_TSEC1M_MASK 0x0000E000 557d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_MII 0x00000000 558d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RMII 0x00002000 559d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RGMII 0x00006000 560d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 561d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 562d87c57b2SScott Wood 563e6d9c891SAnton Vorontsov #define HRCWH_TSEC2M_MASK 0x00001C00 564d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_MII 0x00000000 565d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RMII 0x00000400 566d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 567d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RTBI 0x00001400 568d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_SGMII 0x00001800 569d87c57b2SScott Wood #endif 570d87c57b2SScott Wood 5712c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 572e080313cSDave Liu #define HRCWH_TSEC1M_IN_RGMII 0x00000000 573e080313cSDave Liu #define HRCWH_TSEC1M_IN_RTBI 0x00004000 574e080313cSDave Liu #define HRCWH_TSEC1M_IN_GMII 0x00008000 575e080313cSDave Liu #define HRCWH_TSEC1M_IN_TBI 0x0000C000 576e080313cSDave Liu #define HRCWH_TSEC2M_IN_RGMII 0x00000000 577e080313cSDave Liu #define HRCWH_TSEC2M_IN_RTBI 0x00001000 578e080313cSDave Liu #define HRCWH_TSEC2M_IN_GMII 0x00002000 579e080313cSDave Liu #define HRCWH_TSEC2M_IN_TBI 0x00003000 580e080313cSDave Liu #endif 581e080313cSDave Liu 582e080313cSDave Liu #if defined(CONFIG_MPC8360) 583e080313cSDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 584e080313cSDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 585e080313cSDave Liu #endif 586e080313cSDave Liu 587e080313cSDave Liu #define HRCWH_BIG_ENDIAN 0x00000000 588e080313cSDave Liu #define HRCWH_LITTLE_ENDIAN 0x00000008 589e080313cSDave Liu 590e080313cSDave Liu #define HRCWH_LALE_NORMAL 0x00000000 591e080313cSDave Liu #define HRCWH_LALE_EARLY 0x00000004 592e080313cSDave Liu 593e080313cSDave Liu #define HRCWH_LDP_SET 0x00000000 594e080313cSDave Liu #define HRCWH_LDP_CLEAR 0x00000002 595e080313cSDave Liu 596e080313cSDave Liu /* RSR - Reset Status Register 597e080313cSDave Liu */ 598*7c619ddcSIlya Yanok #if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ 599*7c619ddcSIlya Yanok defined(CONFIG_MPC837x) 60003051c3dSDave Liu #define RSR_RSTSRC 0xF0000000 /* Reset source */ 60103051c3dSDave Liu #define RSR_RSTSRC_SHIFT 28 60203051c3dSDave Liu #else 603e080313cSDave Liu #define RSR_RSTSRC 0xE0000000 /* Reset source */ 604e080313cSDave Liu #define RSR_RSTSRC_SHIFT 29 60503051c3dSDave Liu #endif 606e080313cSDave Liu #define RSR_BSF 0x00010000 /* Boot seq. fail */ 607e080313cSDave Liu #define RSR_BSF_SHIFT 16 608e080313cSDave Liu #define RSR_SWSR 0x00002000 /* software soft reset */ 609e080313cSDave Liu #define RSR_SWSR_SHIFT 13 610e080313cSDave Liu #define RSR_SWHR 0x00001000 /* software hard reset */ 611e080313cSDave Liu #define RSR_SWHR_SHIFT 12 612e080313cSDave Liu #define RSR_JHRS 0x00000200 /* jtag hreset */ 613e080313cSDave Liu #define RSR_JHRS_SHIFT 9 614e080313cSDave Liu #define RSR_JSRS 0x00000100 /* jtag sreset status */ 615e080313cSDave Liu #define RSR_JSRS_SHIFT 8 616e080313cSDave Liu #define RSR_CSHR 0x00000010 /* checkstop reset status */ 617e080313cSDave Liu #define RSR_CSHR_SHIFT 4 618e080313cSDave Liu #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 619e080313cSDave Liu #define RSR_SWRS_SHIFT 3 620e080313cSDave Liu #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 621e080313cSDave Liu #define RSR_BMRS_SHIFT 2 622e080313cSDave Liu #define RSR_SRS 0x00000002 /* soft reset status */ 623e080313cSDave Liu #define RSR_SRS_SHIFT 1 624e080313cSDave Liu #define RSR_HRS 0x00000001 /* hard reset status */ 625e080313cSDave Liu #define RSR_HRS_SHIFT 0 626e080313cSDave Liu #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 627e080313cSDave Liu RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 628e080313cSDave Liu RSR_BMRS | RSR_SRS | RSR_HRS) 629e080313cSDave Liu /* RMR - Reset Mode Register 630e080313cSDave Liu */ 631e080313cSDave Liu #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 632e080313cSDave Liu #define RMR_CSRE_SHIFT 0 633e080313cSDave Liu #define RMR_RES ~(RMR_CSRE) 634e080313cSDave Liu 635e080313cSDave Liu /* RCR - Reset Control Register 636e080313cSDave Liu */ 637e080313cSDave Liu #define RCR_SWHR 0x00000002 /* software hard reset */ 638e080313cSDave Liu #define RCR_SWSR 0x00000001 /* software soft reset */ 639e080313cSDave Liu #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 640e080313cSDave Liu 641e080313cSDave Liu /* RCER - Reset Control Enable Register 642e080313cSDave Liu */ 643e080313cSDave Liu #define RCER_CRE 0x00000001 /* software hard reset */ 644e080313cSDave Liu #define RCER_RES ~(RCER_CRE) 645e080313cSDave Liu 646e080313cSDave Liu /* SPMR - System PLL Mode Register 647e080313cSDave Liu */ 648e080313cSDave Liu #define SPMR_LBIUCM 0x80000000 649e080313cSDave Liu #define SPMR_DDRCM 0x40000000 650e080313cSDave Liu #define SPMR_SPMF 0x0F000000 651e080313cSDave Liu #define SPMR_CKID 0x00800000 652e080313cSDave Liu #define SPMR_CKID_SHIFT 23 653e080313cSDave Liu #define SPMR_COREPLL 0x007F0000 654e080313cSDave Liu #define SPMR_CEVCOD 0x000000C0 655e080313cSDave Liu #define SPMR_CEPDF 0x00000020 656e080313cSDave Liu #define SPMR_CEPMF 0x0000001F 657e080313cSDave Liu 658e080313cSDave Liu /* OCCR - Output Clock Control Register 659e080313cSDave Liu */ 660e080313cSDave Liu #define OCCR_PCICOE0 0x80000000 661e080313cSDave Liu #define OCCR_PCICOE1 0x40000000 662e080313cSDave Liu #define OCCR_PCICOE2 0x20000000 663e080313cSDave Liu #define OCCR_PCICOE3 0x10000000 664e080313cSDave Liu #define OCCR_PCICOE4 0x08000000 665e080313cSDave Liu #define OCCR_PCICOE5 0x04000000 666e080313cSDave Liu #define OCCR_PCICOE6 0x02000000 667e080313cSDave Liu #define OCCR_PCICOE7 0x01000000 668e080313cSDave Liu #define OCCR_PCICD0 0x00800000 669e080313cSDave Liu #define OCCR_PCICD1 0x00400000 670e080313cSDave Liu #define OCCR_PCICD2 0x00200000 671e080313cSDave Liu #define OCCR_PCICD3 0x00100000 672e080313cSDave Liu #define OCCR_PCICD4 0x00080000 673e080313cSDave Liu #define OCCR_PCICD5 0x00040000 674e080313cSDave Liu #define OCCR_PCICD6 0x00020000 675e080313cSDave Liu #define OCCR_PCICD7 0x00010000 676e080313cSDave Liu #define OCCR_PCI1CR 0x00000002 677e080313cSDave Liu #define OCCR_PCI2CR 0x00000001 678e080313cSDave Liu #define OCCR_PCICR OCCR_PCI1CR 679e080313cSDave Liu 680e080313cSDave Liu /* SCCR - System Clock Control Register 681e080313cSDave Liu */ 682e080313cSDave Liu #define SCCR_ENCCM 0x03000000 683e080313cSDave Liu #define SCCR_ENCCM_SHIFT 24 684e080313cSDave Liu #define SCCR_ENCCM_0 0x00000000 685e080313cSDave Liu #define SCCR_ENCCM_1 0x01000000 686e080313cSDave Liu #define SCCR_ENCCM_2 0x02000000 687e080313cSDave Liu #define SCCR_ENCCM_3 0x03000000 688e080313cSDave Liu 689e080313cSDave Liu #define SCCR_PCICM 0x00010000 690e080313cSDave Liu #define SCCR_PCICM_SHIFT 16 691e080313cSDave Liu 6922c7920afSPeter Tyser #if defined(CONFIG_MPC834x) 69303051c3dSDave Liu /* SCCR bits - MPC834x specific */ 694e080313cSDave Liu #define SCCR_TSEC1CM 0xc0000000 695e080313cSDave Liu #define SCCR_TSEC1CM_SHIFT 30 696e080313cSDave Liu #define SCCR_TSEC1CM_0 0x00000000 697e080313cSDave Liu #define SCCR_TSEC1CM_1 0x40000000 698e080313cSDave Liu #define SCCR_TSEC1CM_2 0x80000000 699e080313cSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 700e080313cSDave Liu 701e080313cSDave Liu #define SCCR_TSEC2CM 0x30000000 702e080313cSDave Liu #define SCCR_TSEC2CM_SHIFT 28 703e080313cSDave Liu #define SCCR_TSEC2CM_0 0x00000000 704e080313cSDave Liu #define SCCR_TSEC2CM_1 0x10000000 705e080313cSDave Liu #define SCCR_TSEC2CM_2 0x20000000 706e080313cSDave Liu #define SCCR_TSEC2CM_3 0x30000000 707d87c57b2SScott Wood 70803051c3dSDave Liu /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 70903051c3dSDave Liu #define SCCR_USBMPHCM 0x00c00000 71003051c3dSDave Liu #define SCCR_USBMPHCM_SHIFT 22 71103051c3dSDave Liu #define SCCR_USBDRCM 0x00300000 71203051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 20 71303051c3dSDave Liu #define SCCR_USBCM 0x00f00000 71403051c3dSDave Liu #define SCCR_USBCM_SHIFT 20 71503051c3dSDave Liu #define SCCR_USBCM_0 0x00000000 71603051c3dSDave Liu #define SCCR_USBCM_1 0x00500000 71703051c3dSDave Liu #define SCCR_USBCM_2 0x00A00000 71803051c3dSDave Liu #define SCCR_USBCM_3 0x00F00000 71903051c3dSDave Liu 720555da617SDave Liu #elif defined(CONFIG_MPC8313) 721a8cb43a8SDave Liu /* TSEC1 bits are for TSEC2 as well */ 722d87c57b2SScott Wood #define SCCR_TSEC1CM 0xc0000000 723d87c57b2SScott Wood #define SCCR_TSEC1CM_SHIFT 30 7249e896478SKim Phillips #define SCCR_TSEC1CM_0 0x00000000 725d87c57b2SScott Wood #define SCCR_TSEC1CM_1 0x40000000 726d87c57b2SScott Wood #define SCCR_TSEC1CM_2 0x80000000 727d87c57b2SScott Wood #define SCCR_TSEC1CM_3 0xC0000000 728d87c57b2SScott Wood 729d87c57b2SScott Wood #define SCCR_TSEC1ON 0x20000000 730df33f6b4STimur Tabi #define SCCR_TSEC1ON_SHIFT 29 731d87c57b2SScott Wood #define SCCR_TSEC2ON 0x10000000 732df33f6b4STimur Tabi #define SCCR_TSEC2ON_SHIFT 28 733d87c57b2SScott Wood 734e080313cSDave Liu #define SCCR_USBDRCM 0x00300000 735e080313cSDave Liu #define SCCR_USBDRCM_SHIFT 20 73603051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 73703051c3dSDave Liu #define SCCR_USBDRCM_1 0x00100000 73803051c3dSDave Liu #define SCCR_USBDRCM_2 0x00200000 73903051c3dSDave Liu #define SCCR_USBDRCM_3 0x00300000 740e080313cSDave Liu 741*7c619ddcSIlya Yanok #elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) 742*7c619ddcSIlya Yanok /* SCCR bits - MPC8315/MPC8308 specific */ 743555da617SDave Liu #define SCCR_TSEC1CM 0xc0000000 744555da617SDave Liu #define SCCR_TSEC1CM_SHIFT 30 745555da617SDave Liu #define SCCR_TSEC1CM_0 0x00000000 746555da617SDave Liu #define SCCR_TSEC1CM_1 0x40000000 747555da617SDave Liu #define SCCR_TSEC1CM_2 0x80000000 748555da617SDave Liu #define SCCR_TSEC1CM_3 0xC0000000 749555da617SDave Liu 750555da617SDave Liu #define SCCR_TSEC2CM 0x30000000 751555da617SDave Liu #define SCCR_TSEC2CM_SHIFT 28 752555da617SDave Liu #define SCCR_TSEC2CM_0 0x00000000 753555da617SDave Liu #define SCCR_TSEC2CM_1 0x10000000 754555da617SDave Liu #define SCCR_TSEC2CM_2 0x20000000 755555da617SDave Liu #define SCCR_TSEC2CM_3 0x30000000 756555da617SDave Liu 757*7c619ddcSIlya Yanok #define SCCR_SDHCCM 0x0c000000 758*7c619ddcSIlya Yanok #define SCCR_SDHCCM_SHIFT 26 759*7c619ddcSIlya Yanok #define SCCR_SDHCCM_0 0x00000000 760*7c619ddcSIlya Yanok #define SCCR_SDHCCM_1 0x04000000 761*7c619ddcSIlya Yanok #define SCCR_SDHCCM_2 0x08000000 762*7c619ddcSIlya Yanok #define SCCR_SDHCCM_3 0x0c000000 763*7c619ddcSIlya Yanok 7646f3931a2SDave Liu #define SCCR_USBDRCM 0x00c00000 7656f3931a2SDave Liu #define SCCR_USBDRCM_SHIFT 22 766555da617SDave Liu #define SCCR_USBDRCM_0 0x00000000 7676f3931a2SDave Liu #define SCCR_USBDRCM_1 0x00400000 7686f3931a2SDave Liu #define SCCR_USBDRCM_2 0x00800000 7696f3931a2SDave Liu #define SCCR_USBDRCM_3 0x00c00000 770555da617SDave Liu 7716f3931a2SDave Liu #define SCCR_SATA1CM 0x00003000 7726f3931a2SDave Liu #define SCCR_SATA1CM_SHIFT 12 7736f3931a2SDave Liu #define SCCR_SATACM 0x00003c00 7746f3931a2SDave Liu #define SCCR_SATACM_SHIFT 10 775555da617SDave Liu #define SCCR_SATACM_0 0x00000000 7766f3931a2SDave Liu #define SCCR_SATACM_1 0x00001400 7776f3931a2SDave Liu #define SCCR_SATACM_2 0x00002800 7786f3931a2SDave Liu #define SCCR_SATACM_3 0x00003c00 779555da617SDave Liu 7806f3931a2SDave Liu #define SCCR_TDMCM 0x00000030 7816f3931a2SDave Liu #define SCCR_TDMCM_SHIFT 4 782555da617SDave Liu #define SCCR_TDMCM_0 0x00000000 7836f3931a2SDave Liu #define SCCR_TDMCM_1 0x00000010 7846f3931a2SDave Liu #define SCCR_TDMCM_2 0x00000020 7856f3931a2SDave Liu #define SCCR_TDMCM_3 0x00000030 786555da617SDave Liu 7872c7920afSPeter Tyser #elif defined(CONFIG_MPC837x) 78803051c3dSDave Liu /* SCCR bits - MPC837x specific */ 78903051c3dSDave Liu #define SCCR_TSEC1CM 0xc0000000 79003051c3dSDave Liu #define SCCR_TSEC1CM_SHIFT 30 79103051c3dSDave Liu #define SCCR_TSEC1CM_0 0x00000000 79203051c3dSDave Liu #define SCCR_TSEC1CM_1 0x40000000 79303051c3dSDave Liu #define SCCR_TSEC1CM_2 0x80000000 79403051c3dSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 79503051c3dSDave Liu 79603051c3dSDave Liu #define SCCR_TSEC2CM 0x30000000 79703051c3dSDave Liu #define SCCR_TSEC2CM_SHIFT 28 79803051c3dSDave Liu #define SCCR_TSEC2CM_0 0x00000000 79903051c3dSDave Liu #define SCCR_TSEC2CM_1 0x10000000 80003051c3dSDave Liu #define SCCR_TSEC2CM_2 0x20000000 80103051c3dSDave Liu #define SCCR_TSEC2CM_3 0x30000000 80203051c3dSDave Liu 80303051c3dSDave Liu #define SCCR_SDHCCM 0x0c000000 80403051c3dSDave Liu #define SCCR_SDHCCM_SHIFT 26 80503051c3dSDave Liu #define SCCR_SDHCCM_0 0x00000000 80603051c3dSDave Liu #define SCCR_SDHCCM_1 0x04000000 80703051c3dSDave Liu #define SCCR_SDHCCM_2 0x08000000 80803051c3dSDave Liu #define SCCR_SDHCCM_3 0x0c000000 80903051c3dSDave Liu 81003051c3dSDave Liu #define SCCR_USBDRCM 0x00c00000 81103051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 22 81203051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 81303051c3dSDave Liu #define SCCR_USBDRCM_1 0x00400000 81403051c3dSDave Liu #define SCCR_USBDRCM_2 0x00800000 81503051c3dSDave Liu #define SCCR_USBDRCM_3 0x00c00000 81603051c3dSDave Liu 817fd6646c0SAnton Vorontsov /* All of the four SATA controllers must have the same clock ratio */ 818fd6646c0SAnton Vorontsov #define SCCR_SATA1CM 0x000000c0 819fd6646c0SAnton Vorontsov #define SCCR_SATA1CM_SHIFT 6 820fd6646c0SAnton Vorontsov #define SCCR_SATACM 0x000000ff 821fd6646c0SAnton Vorontsov #define SCCR_SATACM_SHIFT 0 822fd6646c0SAnton Vorontsov #define SCCR_SATACM_0 0x00000000 823fd6646c0SAnton Vorontsov #define SCCR_SATACM_1 0x00000055 824fd6646c0SAnton Vorontsov #define SCCR_SATACM_2 0x000000aa 825fd6646c0SAnton Vorontsov #define SCCR_SATACM_3 0x000000ff 826fd6646c0SAnton Vorontsov #endif 827fd6646c0SAnton Vorontsov 82803051c3dSDave Liu #define SCCR_PCIEXP1CM 0x00300000 82903051c3dSDave Liu #define SCCR_PCIEXP1CM_SHIFT 20 83003051c3dSDave Liu #define SCCR_PCIEXP1CM_0 0x00000000 83103051c3dSDave Liu #define SCCR_PCIEXP1CM_1 0x00100000 83203051c3dSDave Liu #define SCCR_PCIEXP1CM_2 0x00200000 83303051c3dSDave Liu #define SCCR_PCIEXP1CM_3 0x00300000 83403051c3dSDave Liu 83503051c3dSDave Liu #define SCCR_PCIEXP2CM 0x000c0000 83603051c3dSDave Liu #define SCCR_PCIEXP2CM_SHIFT 18 83703051c3dSDave Liu #define SCCR_PCIEXP2CM_0 0x00000000 83803051c3dSDave Liu #define SCCR_PCIEXP2CM_1 0x00040000 83903051c3dSDave Liu #define SCCR_PCIEXP2CM_2 0x00080000 84003051c3dSDave Liu #define SCCR_PCIEXP2CM_3 0x000c0000 84103051c3dSDave Liu 842e080313cSDave Liu /* CSn_BDNS - Chip Select memory Bounds Register 843e080313cSDave Liu */ 844e080313cSDave Liu #define CSBNDS_SA 0x00FF0000 845e080313cSDave Liu #define CSBNDS_SA_SHIFT 8 846e080313cSDave Liu #define CSBNDS_EA 0x000000FF 847e080313cSDave Liu #define CSBNDS_EA_SHIFT 24 848e080313cSDave Liu 849e080313cSDave Liu /* CSn_CONFIG - Chip Select Configuration Register 850e080313cSDave Liu */ 851e080313cSDave Liu #define CSCONFIG_EN 0x80000000 852e080313cSDave Liu #define CSCONFIG_AP 0x00800000 8539e896478SKim Phillips #define CSCONFIG_ODT_WR_ACS 0x00010000 8546d2c26acSHeiko Schocher #if defined(CONFIG_MPC832x) 8556d2c26acSHeiko Schocher #define CSCONFIG_ODT_WR_CFG 0x00040000 8566d2c26acSHeiko Schocher #endif 857d82b4fc0STor Krill #define CSCONFIG_BANK_BIT_3 0x00004000 858e080313cSDave Liu #define CSCONFIG_ROW_BIT 0x00000700 859e080313cSDave Liu #define CSCONFIG_ROW_BIT_12 0x00000000 860e080313cSDave Liu #define CSCONFIG_ROW_BIT_13 0x00000100 861e080313cSDave Liu #define CSCONFIG_ROW_BIT_14 0x00000200 862e080313cSDave Liu #define CSCONFIG_COL_BIT 0x00000007 863e080313cSDave Liu #define CSCONFIG_COL_BIT_8 0x00000000 864e080313cSDave Liu #define CSCONFIG_COL_BIT_9 0x00000001 865e080313cSDave Liu #define CSCONFIG_COL_BIT_10 0x00000002 866e080313cSDave Liu #define CSCONFIG_COL_BIT_11 0x00000003 867e080313cSDave Liu 868d87c57b2SScott Wood /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 869d87c57b2SScott Wood */ 870d87c57b2SScott Wood #define TIMING_CFG0_RWT 0xC0000000 871d87c57b2SScott Wood #define TIMING_CFG0_RWT_SHIFT 30 872d87c57b2SScott Wood #define TIMING_CFG0_WRT 0x30000000 873d87c57b2SScott Wood #define TIMING_CFG0_WRT_SHIFT 28 874d87c57b2SScott Wood #define TIMING_CFG0_RRT 0x0C000000 875d87c57b2SScott Wood #define TIMING_CFG0_RRT_SHIFT 26 876d87c57b2SScott Wood #define TIMING_CFG0_WWT 0x03000000 877d87c57b2SScott Wood #define TIMING_CFG0_WWT_SHIFT 24 878d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 879d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 880d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 881d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 882d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 883d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 884d892b2dbSAnton Vorontsov #define TIMING_CFG0_MRS_CYC 0x0000000F 885d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC_SHIFT 0 886d87c57b2SScott Wood 887e080313cSDave Liu /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 888e080313cSDave Liu */ 889e080313cSDave Liu #define TIMING_CFG1_PRETOACT 0x70000000 890e080313cSDave Liu #define TIMING_CFG1_PRETOACT_SHIFT 28 891e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE 0x0F000000 892e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE_SHIFT 24 893e080313cSDave Liu #define TIMING_CFG1_ACTTORW 0x00700000 894e080313cSDave Liu #define TIMING_CFG1_ACTTORW_SHIFT 20 895e080313cSDave Liu #define TIMING_CFG1_CASLAT 0x00070000 896e080313cSDave Liu #define TIMING_CFG1_CASLAT_SHIFT 16 897e080313cSDave Liu #define TIMING_CFG1_REFREC 0x0000F000 898e080313cSDave Liu #define TIMING_CFG1_REFREC_SHIFT 12 899e080313cSDave Liu #define TIMING_CFG1_WRREC 0x00000700 900e080313cSDave Liu #define TIMING_CFG1_WRREC_SHIFT 8 901e080313cSDave Liu #define TIMING_CFG1_ACTTOACT 0x00000070 902e080313cSDave Liu #define TIMING_CFG1_ACTTOACT_SHIFT 4 903e080313cSDave Liu #define TIMING_CFG1_WRTORD 0x00000007 904e080313cSDave Liu #define TIMING_CFG1_WRTORD_SHIFT 0 905e080313cSDave Liu #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 906e080313cSDave Liu #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 907facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */ 908facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */ 909facdad5fSHeiko Schocher #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ 9102b68b233SHeiko Schocher #define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */ 9112b68b233SHeiko Schocher #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ 912e080313cSDave Liu 913e080313cSDave Liu /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 914e080313cSDave Liu */ 9158d172c0fSXie Xiaobo #define TIMING_CFG2_CPO 0x0F800000 9168d172c0fSXie Xiaobo #define TIMING_CFG2_CPO_SHIFT 23 917e080313cSDave Liu #define TIMING_CFG2_ACSM 0x00080000 918e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 919e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 920e080313cSDave Liu #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 921e080313cSDave Liu 922d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT 0x70000000 923d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT_SHIFT 28 924d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 925d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 926d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE 0x0000E000 927d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 928d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS 0x000001C0 929d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS_SHIFT 6 930d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT 0x0000003F 931d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT_SHIFT 0 932d87c57b2SScott Wood 933e080313cSDave Liu /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 934e080313cSDave Liu */ 935e080313cSDave Liu #define SDRAM_CFG_MEM_EN 0x80000000 936e080313cSDave Liu #define SDRAM_CFG_SREN 0x40000000 937e080313cSDave Liu #define SDRAM_CFG_ECC_EN 0x20000000 938e080313cSDave Liu #define SDRAM_CFG_RD_EN 0x10000000 939bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 940bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 941bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 942e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 943e080313cSDave Liu #define SDRAM_CFG_DYN_PWR 0x00200000 944e080313cSDave Liu #define SDRAM_CFG_32_BE 0x00080000 945e080313cSDave Liu #define SDRAM_CFG_8_BE 0x00040000 946e080313cSDave Liu #define SDRAM_CFG_NCAP 0x00020000 947e080313cSDave Liu #define SDRAM_CFG_2T_EN 0x00008000 948d87c57b2SScott Wood #define SDRAM_CFG_BI 0x00000001 949e080313cSDave Liu 950e080313cSDave Liu /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 951e080313cSDave Liu */ 952e080313cSDave Liu #define SDRAM_MODE_ESD 0xFFFF0000 953e080313cSDave Liu #define SDRAM_MODE_ESD_SHIFT 16 954e080313cSDave Liu #define SDRAM_MODE_SD 0x0000FFFF 955e080313cSDave Liu #define SDRAM_MODE_SD_SHIFT 0 956e080313cSDave Liu #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 957e080313cSDave Liu #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 958e080313cSDave Liu #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 959e080313cSDave Liu #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 960e080313cSDave Liu #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 961e080313cSDave Liu #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 962e080313cSDave Liu #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 963e080313cSDave Liu #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 964e080313cSDave Liu #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 965e080313cSDave Liu #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 966e080313cSDave Liu #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 967e080313cSDave Liu #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 968e080313cSDave Liu #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 969e080313cSDave Liu #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 970e080313cSDave Liu #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 971e080313cSDave Liu #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 972e080313cSDave Liu #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 973e080313cSDave Liu #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 974e080313cSDave Liu #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 975e080313cSDave Liu 976e080313cSDave Liu /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 977e080313cSDave Liu */ 978e080313cSDave Liu #define SDRAM_INTERVAL_REFINT 0x3FFF0000 979e080313cSDave Liu #define SDRAM_INTERVAL_REFINT_SHIFT 16 980e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 981e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 982e080313cSDave Liu 983e080313cSDave Liu /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 984e080313cSDave Liu */ 985e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 986e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 987e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 988e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 989e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 990e080313cSDave Liu 991e080313cSDave Liu /* ECC_ERR_INJECT - Memory data path error injection mask ECC 992e080313cSDave Liu */ 993e080313cSDave Liu #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 994e080313cSDave Liu #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 995e080313cSDave Liu #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 996e080313cSDave Liu #define ECC_ERR_INJECT_EEIM_SHIFT 0 997e080313cSDave Liu 998e080313cSDave Liu /* CAPTURE_ECC - Memory data path read capture ECC 999e080313cSDave Liu */ 1000e080313cSDave Liu #define CAPTURE_ECC_ECE (0xff000000>>24) 1001e080313cSDave Liu #define CAPTURE_ECC_ECE_SHIFT 0 1002e080313cSDave Liu 1003e080313cSDave Liu /* ERR_DETECT - Memory error detect 1004e080313cSDave Liu */ 1005e080313cSDave Liu #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 1006e080313cSDave Liu #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 1007e080313cSDave Liu #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 1008e080313cSDave Liu #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 1009e080313cSDave Liu 1010e080313cSDave Liu /* ERR_DISABLE - Memory error disable 1011e080313cSDave Liu */ 1012e080313cSDave Liu #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 1013e080313cSDave Liu #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 1014e080313cSDave Liu #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 1015e080313cSDave Liu #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 1016e080313cSDave Liu ECC_ERROR_DISABLE_MBED) 1017e080313cSDave Liu /* ERR_INT_EN - Memory error interrupt enable 1018e080313cSDave Liu */ 1019e080313cSDave Liu #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 1020e080313cSDave Liu #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 1021e080313cSDave Liu #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 1022e080313cSDave Liu #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 1023e080313cSDave Liu ECC_ERR_INT_EN_MSEE) 1024e080313cSDave Liu /* CAPTURE_ATTRIBUTES - Memory error attributes capture 1025e080313cSDave Liu */ 1026e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 1027e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM_SHIFT 28 1028e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 1029e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 1030e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 1031e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1032e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1033e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 1034e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 1035e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1036e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1037e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1038e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1039e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1040e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1041e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1042e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1043e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1044e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1045e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1046e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_SHIFT 16 1047e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 1048e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1049e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_READ 0x2 1050e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1051e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1052e080313cSDave Liu #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 1053e080313cSDave Liu 1054e080313cSDave Liu /* ERR_SBE - Single bit ECC memory error management 1055e080313cSDave Liu */ 1056e080313cSDave Liu #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 1057e080313cSDave Liu #define ECC_ERROR_MAN_SBET_SHIFT 16 1058e080313cSDave Liu #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 1059e080313cSDave Liu #define ECC_ERROR_MAN_SBEC_SHIFT 0 1060e080313cSDave Liu 1061e080313cSDave Liu /* CONFIG_ADDRESS - PCI Config Address Register 1062e080313cSDave Liu */ 1063e080313cSDave Liu #define PCI_CONFIG_ADDRESS_EN 0x80000000 1064e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1065e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1066e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1067e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1068e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1069e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1070e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1071e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1072e080313cSDave Liu 1073e080313cSDave Liu /* POTAR - PCI Outbound Translation Address Register 1074e080313cSDave Liu */ 1075e080313cSDave Liu #define POTAR_TA_MASK 0x000fffff 1076e080313cSDave Liu 1077e080313cSDave Liu /* POBAR - PCI Outbound Base Address Register 1078e080313cSDave Liu */ 1079e080313cSDave Liu #define POBAR_BA_MASK 0x000fffff 1080e080313cSDave Liu 1081e080313cSDave Liu /* POCMR - PCI Outbound Comparision Mask Register 1082e080313cSDave Liu */ 1083e080313cSDave Liu #define POCMR_EN 0x80000000 1084e080313cSDave Liu #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1085e080313cSDave Liu #define POCMR_SE 0x20000000 /* streaming enable */ 1086e080313cSDave Liu #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1087e080313cSDave Liu #define POCMR_CM_MASK 0x000fffff 1088e080313cSDave Liu #define POCMR_CM_4G 0x00000000 1089e080313cSDave Liu #define POCMR_CM_2G 0x00080000 1090e080313cSDave Liu #define POCMR_CM_1G 0x000C0000 1091e080313cSDave Liu #define POCMR_CM_512M 0x000E0000 1092e080313cSDave Liu #define POCMR_CM_256M 0x000F0000 1093e080313cSDave Liu #define POCMR_CM_128M 0x000F8000 1094e080313cSDave Liu #define POCMR_CM_64M 0x000FC000 1095e080313cSDave Liu #define POCMR_CM_32M 0x000FE000 1096e080313cSDave Liu #define POCMR_CM_16M 0x000FF000 1097e080313cSDave Liu #define POCMR_CM_8M 0x000FF800 1098e080313cSDave Liu #define POCMR_CM_4M 0x000FFC00 1099e080313cSDave Liu #define POCMR_CM_2M 0x000FFE00 1100e080313cSDave Liu #define POCMR_CM_1M 0x000FFF00 1101e080313cSDave Liu #define POCMR_CM_512K 0x000FFF80 1102e080313cSDave Liu #define POCMR_CM_256K 0x000FFFC0 1103e080313cSDave Liu #define POCMR_CM_128K 0x000FFFE0 1104e080313cSDave Liu #define POCMR_CM_64K 0x000FFFF0 1105e080313cSDave Liu #define POCMR_CM_32K 0x000FFFF8 1106e080313cSDave Liu #define POCMR_CM_16K 0x000FFFFC 1107e080313cSDave Liu #define POCMR_CM_8K 0x000FFFFE 1108e080313cSDave Liu #define POCMR_CM_4K 0x000FFFFF 1109e080313cSDave Liu 1110e080313cSDave Liu /* PITAR - PCI Inbound Translation Address Register 1111e080313cSDave Liu */ 1112e080313cSDave Liu #define PITAR_TA_MASK 0x000fffff 1113e080313cSDave Liu 1114e080313cSDave Liu /* PIBAR - PCI Inbound Base/Extended Address Register 1115e080313cSDave Liu */ 1116e080313cSDave Liu #define PIBAR_MASK 0xffffffff 1117e080313cSDave Liu #define PIEBAR_EBA_MASK 0x000fffff 1118e080313cSDave Liu 1119e080313cSDave Liu /* PIWAR - PCI Inbound Windows Attributes Register 1120e080313cSDave Liu */ 1121e080313cSDave Liu #define PIWAR_EN 0x80000000 1122e080313cSDave Liu #define PIWAR_PF 0x20000000 1123e080313cSDave Liu #define PIWAR_RTT_MASK 0x000f0000 1124e080313cSDave Liu #define PIWAR_RTT_NO_SNOOP 0x00040000 1125e080313cSDave Liu #define PIWAR_RTT_SNOOP 0x00050000 1126e080313cSDave Liu #define PIWAR_WTT_MASK 0x0000f000 1127e080313cSDave Liu #define PIWAR_WTT_NO_SNOOP 0x00004000 1128e080313cSDave Liu #define PIWAR_WTT_SNOOP 0x00005000 1129e080313cSDave Liu #define PIWAR_IWS_MASK 0x0000003F 1130e080313cSDave Liu #define PIWAR_IWS_4K 0x0000000B 1131e080313cSDave Liu #define PIWAR_IWS_8K 0x0000000C 1132e080313cSDave Liu #define PIWAR_IWS_16K 0x0000000D 1133e080313cSDave Liu #define PIWAR_IWS_32K 0x0000000E 1134e080313cSDave Liu #define PIWAR_IWS_64K 0x0000000F 1135e080313cSDave Liu #define PIWAR_IWS_128K 0x00000010 1136e080313cSDave Liu #define PIWAR_IWS_256K 0x00000011 1137e080313cSDave Liu #define PIWAR_IWS_512K 0x00000012 1138e080313cSDave Liu #define PIWAR_IWS_1M 0x00000013 1139e080313cSDave Liu #define PIWAR_IWS_2M 0x00000014 1140e080313cSDave Liu #define PIWAR_IWS_4M 0x00000015 1141e080313cSDave Liu #define PIWAR_IWS_8M 0x00000016 1142e080313cSDave Liu #define PIWAR_IWS_16M 0x00000017 1143e080313cSDave Liu #define PIWAR_IWS_32M 0x00000018 1144e080313cSDave Liu #define PIWAR_IWS_64M 0x00000019 1145e080313cSDave Liu #define PIWAR_IWS_128M 0x0000001A 1146e080313cSDave Liu #define PIWAR_IWS_256M 0x0000001B 1147e080313cSDave Liu #define PIWAR_IWS_512M 0x0000001C 1148e080313cSDave Liu #define PIWAR_IWS_1G 0x0000001D 1149e080313cSDave Liu #define PIWAR_IWS_2G 0x0000001E 1150f6eda7f8SDave Liu 1151d87c57b2SScott Wood /* PMCCR1 - PCI Configuration Register 1 1152d87c57b2SScott Wood */ 1153d87c57b2SScott Wood #define PMCCR1_POWER_OFF 0x00000020 1154d87c57b2SScott Wood 115503051c3dSDave Liu /* DDRCDR - DDR Control Driver Register 1156d87c57b2SScott Wood */ 11579e896478SKim Phillips #define DDRCDR_DHC_EN 0x80000000 1158d87c57b2SScott Wood #define DDRCDR_EN 0x40000000 1159d87c57b2SScott Wood #define DDRCDR_PZ 0x3C000000 1160d87c57b2SScott Wood #define DDRCDR_PZ_MAXZ 0x00000000 1161d87c57b2SScott Wood #define DDRCDR_PZ_HIZ 0x20000000 1162d87c57b2SScott Wood #define DDRCDR_PZ_NOMZ 0x30000000 1163d87c57b2SScott Wood #define DDRCDR_PZ_LOZ 0x38000000 1164d87c57b2SScott Wood #define DDRCDR_PZ_MINZ 0x3C000000 1165d87c57b2SScott Wood #define DDRCDR_NZ 0x3C000000 1166d87c57b2SScott Wood #define DDRCDR_NZ_MAXZ 0x00000000 1167d87c57b2SScott Wood #define DDRCDR_NZ_HIZ 0x02000000 1168d87c57b2SScott Wood #define DDRCDR_NZ_NOMZ 0x03000000 1169d87c57b2SScott Wood #define DDRCDR_NZ_LOZ 0x03800000 1170d87c57b2SScott Wood #define DDRCDR_NZ_MINZ 0x03C00000 1171d87c57b2SScott Wood #define DDRCDR_ODT 0x00080000 1172d87c57b2SScott Wood #define DDRCDR_DDR_CFG 0x00040000 1173d87c57b2SScott Wood #define DDRCDR_M_ODR 0x00000002 1174d87c57b2SScott Wood #define DDRCDR_Q_DRN 0x00000001 1175d87c57b2SScott Wood 1176fd6646c0SAnton Vorontsov /* PCIE Bridge Register 1177fd6646c0SAnton Vorontsov */ 1178fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_OBPIOE 0x00000001 1179fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_IBPIOE 0x00000002 1180fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_WDMAE 0x00000004 1181fd6646c0SAnton Vorontsov #define PEX_CSB_CTRL_RDMAE 0x00000008 1182fd6646c0SAnton Vorontsov 1183fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_PIOE 0x00000001 1184fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_MEMWE 0x00000002 1185fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_IOWE 0x00000004 1186fd6646c0SAnton Vorontsov #define PEX_CSB_OBCTRL_CFGWE 0x00000008 1187fd6646c0SAnton Vorontsov 1188fd6646c0SAnton Vorontsov #define PEX_CSB_IBCTRL_PIOE 0x00000001 1189fd6646c0SAnton Vorontsov 1190fd6646c0SAnton Vorontsov #define PEX_OWAR_EN 0x00000001 1191fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_CFG 0x00000000 1192fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_IO 0x00000002 1193fd6646c0SAnton Vorontsov #define PEX_OWAR_TYPE_MEM 0x00000004 1194fd6646c0SAnton Vorontsov #define PEX_OWAR_RLXO 0x00000008 1195fd6646c0SAnton Vorontsov #define PEX_OWAR_NANP 0x00000010 1196fd6646c0SAnton Vorontsov #define PEX_OWAR_SIZE 0xFFFFF000 1197fd6646c0SAnton Vorontsov 1198fd6646c0SAnton Vorontsov #define PEX_IWAR_EN 0x00000001 1199fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_INT 0x00000000 1200fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_PF 0x00000004 1201fd6646c0SAnton Vorontsov #define PEX_IWAR_TYPE_NO_PF 0x00000006 1202fd6646c0SAnton Vorontsov #define PEX_IWAR_NSOV 0x00000008 1203fd6646c0SAnton Vorontsov #define PEX_IWAR_NSNP 0x00000010 1204fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE 0xFFFFF000 1205fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_1M 0x000FF000 1206fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_2M 0x001FF000 1207fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_4M 0x003FF000 1208fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_8M 0x007FF000 1209fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_16M 0x00FFF000 1210fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_32M 0x01FFF000 1211fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_64M 0x03FFF000 1212fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_128M 0x07FFF000 1213fd6646c0SAnton Vorontsov #define PEX_IWAR_SIZE_256M 0x0FFFF000 1214fd6646c0SAnton Vorontsov 1215fd6646c0SAnton Vorontsov #define PEX_GCLK_RATIO 0x440 1216fd6646c0SAnton Vorontsov 121749ea3b6eSScott Wood #ifndef __ASSEMBLY__ 121849ea3b6eSScott Wood struct pci_region; 121949ea3b6eSScott Wood void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 122075f35209SIra Snyder void mpc83xx_pcislave_unlock(int bus); 1221fd6646c0SAnton Vorontsov void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot); 122249ea3b6eSScott Wood #endif 122349ea3b6eSScott Wood 1224f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 1225