1f046ccd1SEran Liberty /* 2f6eda7f8SDave Liu * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty */ 12f046ccd1SEran Liberty 13f046ccd1SEran Liberty /* 14f046ccd1SEran Liberty * mpc83xx.h 15f046ccd1SEran Liberty * 16f046ccd1SEran Liberty * MPC83xx specific definitions 17f046ccd1SEran Liberty */ 18f046ccd1SEran Liberty 19f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 20f046ccd1SEran Liberty #define __MPC83XX_H__ 21f046ccd1SEran Liberty 22f6eda7f8SDave Liu #include <config.h> 23f046ccd1SEran Liberty #if defined(CONFIG_E300) 24f046ccd1SEran Liberty #include <asm/e300.h> 25f046ccd1SEran Liberty #endif 26f046ccd1SEran Liberty 27f046ccd1SEran Liberty /* 28f046ccd1SEran Liberty * MPC83xx cpu provide RCR register to do reset thing specially. easier 29f046ccd1SEran Liberty * to implement 30f046ccd1SEran Liberty */ 31f046ccd1SEran Liberty 32f046ccd1SEran Liberty #define MPC83xx_RESET 33f046ccd1SEran Liberty 34f046ccd1SEran Liberty /* 35f046ccd1SEran Liberty * System reset offset (PowerPC standard) 36f046ccd1SEran Liberty */ 37f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 38f046ccd1SEran Liberty 39f046ccd1SEran Liberty /* 40f046ccd1SEran Liberty * Default Internal Memory Register Space (Freescale recomandation) 41f046ccd1SEran Liberty */ 42f046ccd1SEran Liberty #define CONFIG_DEFAULT_IMMR 0xFF400000 43f046ccd1SEran Liberty 44f046ccd1SEran Liberty /* 45f046ccd1SEran Liberty * Watchdog 46f046ccd1SEran Liberty */ 47f046ccd1SEran Liberty #define SWCRR 0x0204 48f046ccd1SEran Liberty #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ 49f046ccd1SEran Liberty #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ 50f046ccd1SEran Liberty #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ 51f046ccd1SEran Liberty #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ 52f046ccd1SEran Liberty #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 53f046ccd1SEran Liberty 54f046ccd1SEran Liberty #define SWCNR 0x0208 55f046ccd1SEran Liberty #define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. 56f046ccd1SEran Liberty #define SWCNR_RES ~(SWCNR_SWCN) 57f046ccd1SEran Liberty 58f046ccd1SEran Liberty #define SWSRR 0x020E 59f046ccd1SEran Liberty 60f046ccd1SEran Liberty /* 61f046ccd1SEran Liberty * Default Internal Memory Register Space (Freescale recomandation) 62f046ccd1SEran Liberty */ 63f046ccd1SEran Liberty #define IMMRBAR 0x0000 64f046ccd1SEran Liberty #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */ 65f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 66f046ccd1SEran Liberty 67f046ccd1SEran Liberty /* 68f046ccd1SEran Liberty * Default Internal Memory Register Space (Freescale recomandation) 69f046ccd1SEran Liberty */ 70f046ccd1SEran Liberty #define LBLAWBAR0 0x0020 71f046ccd1SEran Liberty #define LBLAWAR0 0x0024 72f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 73f046ccd1SEran Liberty #define LBLAWAR1 0x002C 74f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 75f046ccd1SEran Liberty #define LBLAWAR2 0x0034 76f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 77f046ccd1SEran Liberty #define LBLAWAR3 0x003C 78f046ccd1SEran Liberty 79f6eda7f8SDave Liu /* 80f6eda7f8SDave Liu * The device ID and revision numbers 81f6eda7f8SDave Liu */ 82f6eda7f8SDave Liu #define SPR_8349E_REV10 0x80300100 83*5f820439SDave Liu #define SPR_8349_REV10 0x80310100 84*5f820439SDave Liu #define SPR_8347E_REV10_TBGA 0x80320100 85*5f820439SDave Liu #define SPR_8347_REV10_TBGA 0x80330100 86*5f820439SDave Liu #define SPR_8347E_REV10_PBGA 0x80340100 87*5f820439SDave Liu #define SPR_8347_REV10_PBGA 0x80350100 88*5f820439SDave Liu #define SPR_8343E_REV10 0x80360100 89*5f820439SDave Liu #define SPR_8343_REV10 0x80370100 90*5f820439SDave Liu 91f6eda7f8SDave Liu #define SPR_8349E_REV11 0x80300101 92*5f820439SDave Liu #define SPR_8349_REV11 0x80310101 93*5f820439SDave Liu #define SPR_8347E_REV11_TBGA 0x80320101 94*5f820439SDave Liu #define SPR_8347_REV11_TBGA 0x80330101 95*5f820439SDave Liu #define SPR_8347E_REV11_PBGA 0x80340101 96*5f820439SDave Liu #define SPR_8347_REV11_PBGA 0x80350101 97*5f820439SDave Liu #define SPR_8343E_REV11 0x80360101 98*5f820439SDave Liu #define SPR_8343_REV11 0x80370101 99*5f820439SDave Liu 100*5f820439SDave Liu #define SPR_8360E_REV10 0x80480010 101*5f820439SDave Liu #define SPR_8360_REV10 0x80490010 102*5f820439SDave Liu #define SPR_8360E_REV11 0x80480011 103*5f820439SDave Liu #define SPR_8360_REV11 0x80490011 104*5f820439SDave Liu #define SPR_8360E_REV12 0x80480012 105*5f820439SDave Liu #define SPR_8360_REV12 0x80490012 106f046ccd1SEran Liberty 107f046ccd1SEran Liberty /* 108f046ccd1SEran Liberty * Base Registers & Option Registers 109f046ccd1SEran Liberty */ 110f046ccd1SEran Liberty #define BR0 0x5000 111f046ccd1SEran Liberty #define BR1 0x5008 112f046ccd1SEran Liberty #define BR2 0x5010 113f046ccd1SEran Liberty #define BR3 0x5018 114f046ccd1SEran Liberty #define BR4 0x5020 115f046ccd1SEran Liberty #define BR5 0x5028 116f046ccd1SEran Liberty #define BR6 0x5030 117f046ccd1SEran Liberty #define BR7 0x5038 118f046ccd1SEran Liberty 119f046ccd1SEran Liberty #define BR_BA 0xFFFF8000 120f046ccd1SEran Liberty #define BR_BA_SHIFT 15 121f046ccd1SEran Liberty #define BR_PS 0x00001800 122f046ccd1SEran Liberty #define BR_PS_SHIFT 11 123e6f2e902SMarian Balakowicz #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 124e6f2e902SMarian Balakowicz #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 125e6f2e902SMarian Balakowicz #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 126f046ccd1SEran Liberty #define BR_DECC 0x00000600 127f046ccd1SEran Liberty #define BR_DECC_SHIFT 9 128f046ccd1SEran Liberty #define BR_WP 0x00000100 129f046ccd1SEran Liberty #define BR_WP_SHIFT 8 130f046ccd1SEran Liberty #define BR_MSEL 0x000000E0 131f046ccd1SEran Liberty #define BR_MSEL_SHIFT 5 132e6f2e902SMarian Balakowicz #define BR_MS_GPCM 0x00000000 /* GPCM */ 133e6f2e902SMarian Balakowicz #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 134e6f2e902SMarian Balakowicz #define BR_MS_UPMA 0x00000080 /* UPMA */ 135e6f2e902SMarian Balakowicz #define BR_MS_UPMB 0x000000A0 /* UPMB */ 136e6f2e902SMarian Balakowicz #define BR_MS_UPMC 0x000000C0 /* UPMC */ 137*5f820439SDave Liu #if defined (CONFIG_MPC8360) 138*5f820439SDave Liu #define BR_ATOM 0x0000000C 139*5f820439SDave Liu #define BR_ATOM_SHIFT 2 140*5f820439SDave Liu #endif 141f046ccd1SEran Liberty #define BR_V 0x00000001 142f046ccd1SEran Liberty #define BR_V_SHIFT 0 143*5f820439SDave Liu #if defined (CONFIG_MPC8349) 144f046ccd1SEran Liberty #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) 145*5f820439SDave Liu #elif defined (CONFIG_MPC8360) 146*5f820439SDave Liu #define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V) 147*5f820439SDave Liu #endif 148f046ccd1SEran Liberty 149f046ccd1SEran Liberty #define OR0 0x5004 150f046ccd1SEran Liberty #define OR1 0x500C 151f046ccd1SEran Liberty #define OR2 0x5014 152f046ccd1SEran Liberty #define OR3 0x501C 153f046ccd1SEran Liberty #define OR4 0x5024 154f046ccd1SEran Liberty #define OR5 0x502C 155f046ccd1SEran Liberty #define OR6 0x5034 156f046ccd1SEran Liberty #define OR7 0x503C 157f046ccd1SEran Liberty 158f046ccd1SEran Liberty #define OR_GPCM_AM 0xFFFF8000 159f046ccd1SEran Liberty #define OR_GPCM_AM_SHIFT 15 160f046ccd1SEran Liberty #define OR_GPCM_BCTLD 0x00001000 161f046ccd1SEran Liberty #define OR_GPCM_BCTLD_SHIFT 12 162f046ccd1SEran Liberty #define OR_GPCM_CSNT 0x00000800 163f046ccd1SEran Liberty #define OR_GPCM_CSNT_SHIFT 11 164f046ccd1SEran Liberty #define OR_GPCM_ACS 0x00000600 165f046ccd1SEran Liberty #define OR_GPCM_ACS_SHIFT 9 166e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b10 0x00000400 167e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b11 0x00000600 168f046ccd1SEran Liberty #define OR_GPCM_XACS 0x00000100 169f046ccd1SEran Liberty #define OR_GPCM_XACS_SHIFT 8 170f046ccd1SEran Liberty #define OR_GPCM_SCY 0x000000F0 171f046ccd1SEran Liberty #define OR_GPCM_SCY_SHIFT 4 172e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_1 0x00000010 173e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_2 0x00000020 174e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_3 0x00000030 175e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_4 0x00000040 176e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_5 0x00000050 177e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_6 0x00000060 178e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_7 0x00000070 179e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_8 0x00000080 180e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_9 0x00000090 181e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_10 0x000000a0 182e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_11 0x000000b0 183e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_12 0x000000c0 184e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_13 0x000000d0 185e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_14 0x000000e0 186e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_15 0x000000f0 187f046ccd1SEran Liberty #define OR_GPCM_SETA 0x00000008 188f046ccd1SEran Liberty #define OR_GPCM_SETA_SHIFT 3 189f046ccd1SEran Liberty #define OR_GPCM_TRLX 0x00000004 190f046ccd1SEran Liberty #define OR_GPCM_TRLX_SHIFT 2 191f046ccd1SEran Liberty #define OR_GPCM_EHTR 0x00000002 192f046ccd1SEran Liberty #define OR_GPCM_EHTR_SHIFT 1 193f046ccd1SEran Liberty #define OR_GPCM_EAD 0x00000001 194f046ccd1SEran Liberty #define OR_GPCM_EAD_SHIFT 0 195f046ccd1SEran Liberty 196f046ccd1SEran Liberty #define OR_UPM_AM 0xFFFF8000 197f046ccd1SEran Liberty #define OR_UPM_AM_SHIFT 15 198f046ccd1SEran Liberty #define OR_UPM_XAM 0x00006000 199f046ccd1SEran Liberty #define OR_UPM_XAM_SHIFT 13 200f046ccd1SEran Liberty #define OR_UPM_BCTLD 0x00001000 201f046ccd1SEran Liberty #define OR_UPM_BCTLD_SHIFT 12 202f046ccd1SEran Liberty #define OR_UPM_BI 0x00000100 203f046ccd1SEran Liberty #define OR_UPM_BI_SHIFT 8 204f046ccd1SEran Liberty #define OR_UPM_TRLX 0x00000004 205f046ccd1SEran Liberty #define OR_UPM_TRLX_SHIFT 2 206f046ccd1SEran Liberty #define OR_UPM_EHTR 0x00000002 207f046ccd1SEran Liberty #define OR_UPM_EHTR_SHIFT 1 208f046ccd1SEran Liberty #define OR_UPM_EAD 0x00000001 209f046ccd1SEran Liberty #define OR_UPM_EAD_SHIFT 0 210f046ccd1SEran Liberty 211f046ccd1SEran Liberty #define OR_SDRAM_AM 0xFFFF8000 212f046ccd1SEran Liberty #define OR_SDRAM_AM_SHIFT 15 213f046ccd1SEran Liberty #define OR_SDRAM_XAM 0x00006000 214f046ccd1SEran Liberty #define OR_SDRAM_XAM_SHIFT 13 215f046ccd1SEran Liberty #define OR_SDRAM_COLS 0x00001C00 216f046ccd1SEran Liberty #define OR_SDRAM_COLS_SHIFT 10 217f046ccd1SEran Liberty #define OR_SDRAM_ROWS 0x000001C0 218f046ccd1SEran Liberty #define OR_SDRAM_ROWS_SHIFT 6 219f046ccd1SEran Liberty #define OR_SDRAM_PMSEL 0x00000020 220f046ccd1SEran Liberty #define OR_SDRAM_PMSEL_SHIFT 5 221f046ccd1SEran Liberty #define OR_SDRAM_EAD 0x00000001 222f046ccd1SEran Liberty #define OR_SDRAM_EAD_SHIFT 0 223f046ccd1SEran Liberty 224f046ccd1SEran Liberty /* 225f046ccd1SEran Liberty * Hard Reset Configration Word - High 226f046ccd1SEran Liberty */ 227f046ccd1SEran Liberty #define HRCWH_PCI_AGENT 0x00000000 228f046ccd1SEran Liberty #define HRCWH_PCI_HOST 0x80000000 229f046ccd1SEran Liberty 230*5f820439SDave Liu #if defined (CONFIG_MPC8349) 231f046ccd1SEran Liberty #define HRCWH_32_BIT_PCI 0x00000000 232f046ccd1SEran Liberty #define HRCWH_64_BIT_PCI 0x40000000 233*5f820439SDave Liu #endif 234f046ccd1SEran Liberty 235f046ccd1SEran Liberty #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 236f046ccd1SEran Liberty #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 237f046ccd1SEran Liberty 238*5f820439SDave Liu #if defined (CONFIG_MPC8349) 239f046ccd1SEran Liberty #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 240f046ccd1SEran Liberty #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 241*5f820439SDave Liu #elif defined (CONFIG_MPC8360) 242*5f820439SDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 243*5f820439SDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 244*5f820439SDave Liu #endif 245f046ccd1SEran Liberty 246f046ccd1SEran Liberty #define HRCWH_CORE_DISABLE 0x08000000 247f046ccd1SEran Liberty #define HRCWH_CORE_ENABLE 0x00000000 248f046ccd1SEran Liberty 249f046ccd1SEran Liberty #define HRCWH_FROM_0X00000100 0x00000000 250f046ccd1SEran Liberty #define HRCWH_FROM_0XFFF00100 0x04000000 251f046ccd1SEran Liberty 252f046ccd1SEran Liberty #define HRCWH_BOOTSEQ_DISABLE 0x00000000 253f046ccd1SEran Liberty #define HRCWH_BOOTSEQ_NORMAL 0x01000000 254f046ccd1SEran Liberty #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 255f046ccd1SEran Liberty 256f046ccd1SEran Liberty #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 257f046ccd1SEran Liberty #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 258f046ccd1SEran Liberty 259f046ccd1SEran Liberty #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 260f046ccd1SEran Liberty #define HRCWH_ROM_LOC_PCI1 0x00100000 261*5f820439SDave Liu #if defined (CONFIG_MPC8349) 262f046ccd1SEran Liberty #define HRCWH_ROM_LOC_PCI2 0x00200000 263*5f820439SDave Liu #endif 264f046ccd1SEran Liberty #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 265f046ccd1SEran Liberty #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 266f046ccd1SEran Liberty #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 267f046ccd1SEran Liberty 268*5f820439SDave Liu #if defined (CONFIG_MPC8349) 269f046ccd1SEran Liberty #define HRCWH_TSEC1M_IN_RGMII 0x00000000 270f046ccd1SEran Liberty #define HRCWH_TSEC1M_IN_RTBI 0x00004000 271f046ccd1SEran Liberty #define HRCWH_TSEC1M_IN_GMII 0x00008000 272f046ccd1SEran Liberty #define HRCWH_TSEC1M_IN_TBI 0x0000C000 273f046ccd1SEran Liberty 274f046ccd1SEran Liberty #define HRCWH_TSEC2M_IN_RGMII 0x00000000 275f046ccd1SEran Liberty #define HRCWH_TSEC2M_IN_RTBI 0x00001000 276f046ccd1SEran Liberty #define HRCWH_TSEC2M_IN_GMII 0x00002000 277f046ccd1SEran Liberty #define HRCWH_TSEC2M_IN_TBI 0x00003000 278*5f820439SDave Liu #endif 279*5f820439SDave Liu 280*5f820439SDave Liu #if defined (CONFIG_MPC8360) 281*5f820439SDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 282*5f820439SDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 283*5f820439SDave Liu #endif 284f046ccd1SEran Liberty 285f046ccd1SEran Liberty #define HRCWH_BIG_ENDIAN 0x00000000 286f046ccd1SEran Liberty #define HRCWH_LITTLE_ENDIAN 0x00000008 287f046ccd1SEran Liberty 288f6eda7f8SDave Liu #define HRCWH_LALE_NORMAL 0x00000000 289f6eda7f8SDave Liu #define HRCWH_LALE_EARLY 0x00000004 290f6eda7f8SDave Liu 291f6eda7f8SDave Liu #define HRCWH_LDP_SET 0x00000000 292f6eda7f8SDave Liu #define HRCWH_LDP_CLEAR 0x00000002 293f6eda7f8SDave Liu 294f046ccd1SEran Liberty /* 295f046ccd1SEran Liberty * Hard Reset Configration Word - Low 296f046ccd1SEran Liberty */ 297f046ccd1SEran Liberty #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 298f046ccd1SEran Liberty #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 299f046ccd1SEran Liberty 300f046ccd1SEran Liberty #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 301f046ccd1SEran Liberty #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 302f046ccd1SEran Liberty 303f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 304f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 305f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 306f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 307f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 308f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 309f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 310f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 311f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 312f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 313f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 314f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 315f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 316f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 317f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 318f046ccd1SEran Liberty #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 319f046ccd1SEran Liberty 320f046ccd1SEran Liberty #define HRCWL_VCO_BYPASS 0x00000000 321f046ccd1SEran Liberty #define HRCWL_VCO_1X2 0x00000000 322f046ccd1SEran Liberty #define HRCWL_VCO_1X4 0x00200000 323f046ccd1SEran Liberty #define HRCWL_VCO_1X8 0x00400000 324f046ccd1SEran Liberty 325f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 326f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_1X1 0x00020000 327f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 328f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_2X1 0x00040000 329f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 330f046ccd1SEran Liberty #define HRCWL_CORE_TO_CSB_3X1 0x00060000 331f046ccd1SEran Liberty 332*5f820439SDave Liu #if defined (CONFIG_MPC8360) 333*5f820439SDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 334*5f820439SDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 335*5f820439SDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 336*5f820439SDave Liu 337*5f820439SDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 338*5f820439SDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 339*5f820439SDave Liu 340*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 341*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 342*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 343*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 344*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 345*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 346*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 347*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 348*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 349*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 350*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 351*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 352*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 353*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 354*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 355*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 356*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 357*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 358*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 359*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 360*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 361*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 362*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 363*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 364*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 365*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 366*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 367*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 368*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 369*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 370*5f820439SDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 371*5f820439SDave Liu #endif 372*5f820439SDave Liu 373f046ccd1SEran Liberty /* 374f046ccd1SEran Liberty * LCRR - Clock Ratio Register (10.3.1.16) 375f046ccd1SEran Liberty */ 376f046ccd1SEran Liberty #define LCRR_DBYP 0x80000000 377f046ccd1SEran Liberty #define LCRR_DBYP_SHIFT 31 378f046ccd1SEran Liberty #define LCRR_BUFCMDC 0x30000000 379f046ccd1SEran Liberty #define LCRR_BUFCMDC_1 0x10000000 380f046ccd1SEran Liberty #define LCRR_BUFCMDC_2 0x20000000 381f046ccd1SEran Liberty #define LCRR_BUFCMDC_3 0x30000000 382f046ccd1SEran Liberty #define LCRR_BUFCMDC_4 0x00000000 383f046ccd1SEran Liberty #define LCRR_BUFCMDC_SHIFT 28 384f046ccd1SEran Liberty #define LCRR_ECL 0x03000000 385f046ccd1SEran Liberty #define LCRR_ECL_4 0x00000000 386f046ccd1SEran Liberty #define LCRR_ECL_5 0x01000000 387f046ccd1SEran Liberty #define LCRR_ECL_6 0x02000000 388f046ccd1SEran Liberty #define LCRR_ECL_7 0x03000000 389f046ccd1SEran Liberty #define LCRR_ECL_SHIFT 24 390f046ccd1SEran Liberty #define LCRR_EADC 0x00030000 391f046ccd1SEran Liberty #define LCRR_EADC_1 0x00010000 392f046ccd1SEran Liberty #define LCRR_EADC_2 0x00020000 393f046ccd1SEran Liberty #define LCRR_EADC_3 0x00030000 394f046ccd1SEran Liberty #define LCRR_EADC_4 0x00000000 395f046ccd1SEran Liberty #define LCRR_EADC_SHIFT 16 396f046ccd1SEran Liberty #define LCRR_CLKDIV 0x0000000F 397f046ccd1SEran Liberty #define LCRR_CLKDIV_2 0x00000002 398f046ccd1SEran Liberty #define LCRR_CLKDIV_4 0x00000004 399f046ccd1SEran Liberty #define LCRR_CLKDIV_8 0x00000008 400f046ccd1SEran Liberty #define LCRR_CLKDIV_SHIFT 0 401f046ccd1SEran Liberty 402f6eda7f8SDave Liu /* 403f6eda7f8SDave Liu * SCCR-System Clock Control Register 404f6eda7f8SDave Liu */ 405f6eda7f8SDave Liu #define SCCR_TSEC1CM_0 0x00000000 406f6eda7f8SDave Liu #define SCCR_TSEC1CM_1 0x40000000 407f6eda7f8SDave Liu #define SCCR_TSEC1CM_2 0x80000000 408f6eda7f8SDave Liu #define SCCR_TSEC1CM_3 0xC0000000 409f6eda7f8SDave Liu #define SCCR_TSEC2CM_0 0x00000000 410f6eda7f8SDave Liu #define SCCR_TSEC2CM_1 0x10000000 411f6eda7f8SDave Liu #define SCCR_TSEC2CM_2 0x20000000 412f6eda7f8SDave Liu #define SCCR_TSEC2CM_3 0x30000000 413f6eda7f8SDave Liu #define SCCR_ENCCM_0 0x00000000 414f6eda7f8SDave Liu #define SCCR_ENCCM_1 0x01000000 415f6eda7f8SDave Liu #define SCCR_ENCCM_2 0x02000000 416f6eda7f8SDave Liu #define SCCR_ENCCM_3 0x03000000 417f6eda7f8SDave Liu #define SCCR_USBCM_0 0x00000000 418f6eda7f8SDave Liu #define SCCR_USBCM_1 0x00500000 419f6eda7f8SDave Liu #define SCCR_USBCM_2 0x00A00000 420f6eda7f8SDave Liu #define SCCR_USBCM_3 0x00F00000 421f6eda7f8SDave Liu 422f6eda7f8SDave Liu #define SCCR_CLK_MASK ( SCCR_TSEC1CM_3 \ 423f6eda7f8SDave Liu | SCCR_TSEC2CM_3 \ 424f6eda7f8SDave Liu | SCCR_ENCCM_3 \ 425f6eda7f8SDave Liu | SCCR_USBCM_3 ) 426*5f820439SDave Liu 427f6eda7f8SDave Liu #define SCCR_DEFAULT 0xFFFFFFFF 428f6eda7f8SDave Liu 429f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 430