1f046ccd1SEran Liberty /* 2f6eda7f8SDave Liu * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty */ 12f046ccd1SEran Liberty 13f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 14f046ccd1SEran Liberty #define __MPC83XX_H__ 15f046ccd1SEran Liberty 16f6eda7f8SDave Liu #include <config.h> 17f046ccd1SEran Liberty #if defined(CONFIG_E300) 18f046ccd1SEran Liberty #include <asm/e300.h> 19f046ccd1SEran Liberty #endif 20f046ccd1SEran Liberty 21e080313cSDave Liu /* MPC83xx cpu provide RCR register to do reset thing specially 22f046ccd1SEran Liberty */ 23f046ccd1SEran Liberty #define MPC83xx_RESET 24f046ccd1SEran Liberty 25e080313cSDave Liu /* System reset offset (PowerPC standard) 26f046ccd1SEran Liberty */ 27f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 28f046ccd1SEran Liberty 29e080313cSDave Liu /* IMMRBAR - Internal Memory Register Base Address 30f046ccd1SEran Liberty */ 31e080313cSDave Liu #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 32e080313cSDave Liu #define IMMRBAR 0x0000 /* Register offset to immr */ 33e080313cSDave Liu #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 34f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 35f046ccd1SEran Liberty 36e080313cSDave Liu /* LAWBAR - Local Access Window Base Address Register 37f046ccd1SEran Liberty */ 38e080313cSDave Liu #define LBLAWBAR0 0x0020 /* Register offset to immr */ 39f046ccd1SEran Liberty #define LBLAWAR0 0x0024 40f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 41f046ccd1SEran Liberty #define LBLAWAR1 0x002C 42f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 43f046ccd1SEran Liberty #define LBLAWAR2 0x0034 44f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 45f046ccd1SEran Liberty #define LBLAWAR3 0x003C 46e080313cSDave Liu #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 47f046ccd1SEran Liberty 48e080313cSDave Liu /* SPRIDR - System Part and Revision ID Register 49f6eda7f8SDave Liu */ 50e080313cSDave Liu #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ 51e080313cSDave Liu #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ 52e080313cSDave Liu 53f6eda7f8SDave Liu #define SPR_8349E_REV10 0x80300100 545f820439SDave Liu #define SPR_8349_REV10 0x80310100 555f820439SDave Liu #define SPR_8347E_REV10_TBGA 0x80320100 565f820439SDave Liu #define SPR_8347_REV10_TBGA 0x80330100 575f820439SDave Liu #define SPR_8347E_REV10_PBGA 0x80340100 585f820439SDave Liu #define SPR_8347_REV10_PBGA 0x80350100 595f820439SDave Liu #define SPR_8343E_REV10 0x80360100 605f820439SDave Liu #define SPR_8343_REV10 0x80370100 615f820439SDave Liu 62f6eda7f8SDave Liu #define SPR_8349E_REV11 0x80300101 635f820439SDave Liu #define SPR_8349_REV11 0x80310101 645f820439SDave Liu #define SPR_8347E_REV11_TBGA 0x80320101 655f820439SDave Liu #define SPR_8347_REV11_TBGA 0x80330101 665f820439SDave Liu #define SPR_8347E_REV11_PBGA 0x80340101 675f820439SDave Liu #define SPR_8347_REV11_PBGA 0x80350101 685f820439SDave Liu #define SPR_8343E_REV11 0x80360101 695f820439SDave Liu #define SPR_8343_REV11 0x80370101 705f820439SDave Liu 718d172c0fSXie Xiaobo #define SPR_8349E_REV31 0x80300300 728d172c0fSXie Xiaobo #define SPR_8349_REV31 0x80310300 738d172c0fSXie Xiaobo #define SPR_8347E_REV31_TBGA 0x80320300 748d172c0fSXie Xiaobo #define SPR_8347_REV31_TBGA 0x80330300 758d172c0fSXie Xiaobo #define SPR_8347E_REV31_PBGA 0x80340300 768d172c0fSXie Xiaobo #define SPR_8347_REV31_PBGA 0x80350300 778d172c0fSXie Xiaobo #define SPR_8343E_REV31 0x80360300 788d172c0fSXie Xiaobo #define SPR_8343_REV31 0x80370300 798d172c0fSXie Xiaobo 805f820439SDave Liu #define SPR_8360E_REV10 0x80480010 815f820439SDave Liu #define SPR_8360_REV10 0x80490010 825f820439SDave Liu #define SPR_8360E_REV11 0x80480011 835f820439SDave Liu #define SPR_8360_REV11 0x80490011 845f820439SDave Liu #define SPR_8360E_REV12 0x80480012 855f820439SDave Liu #define SPR_8360_REV12 0x80490012 86b110f40bSXie Xiaobo #define SPR_8360E_REV20 0x80480020 87b110f40bSXie Xiaobo #define SPR_8360_REV20 0x80490020 88f046ccd1SEran Liberty 8924c3aca3SDave Liu #define SPR_8323E_REV10 0x80620010 9024c3aca3SDave Liu #define SPR_8323_REV10 0x80630010 9124c3aca3SDave Liu #define SPR_8321E_REV10 0x80660010 9224c3aca3SDave Liu #define SPR_8321_REV10 0x80670010 9324c3aca3SDave Liu #define SPR_8323E_REV11 0x80620011 9424c3aca3SDave Liu #define SPR_8323_REV11 0x80630011 9524c3aca3SDave Liu #define SPR_8321E_REV11 0x80660011 9624c3aca3SDave Liu #define SPR_8321_REV11 0x80670011 9724c3aca3SDave Liu 98e080313cSDave Liu /* SPCR - System Priority Configuration Register 99f046ccd1SEran Liberty */ 100e080313cSDave Liu #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 101e080313cSDave Liu #define SPCR_PCIHPE_SHIFT (31-3) 102e080313cSDave Liu #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 103e080313cSDave Liu #define SPCR_PCIPR_SHIFT (31-7) 104e080313cSDave Liu #define SPCR_OPT 0x00800000 /* Optimize */ 105e080313cSDave Liu #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 106e080313cSDave Liu #define SPCR_TBEN_SHIFT (31-9) 107e080313cSDave Liu #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 108e080313cSDave Liu #define SPCR_COREPR_SHIFT (31-11) 109e080313cSDave Liu 1103e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 111e080313cSDave Liu /* SPCR bits - MPC8349 specific */ 112e080313cSDave Liu #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 113e080313cSDave Liu #define SPCR_TSEC1DP_SHIFT (31-19) 114e080313cSDave Liu #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 115e080313cSDave Liu #define SPCR_TSEC1BDP_SHIFT (31-21) 116e080313cSDave Liu #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 117e080313cSDave Liu #define SPCR_TSEC1EP_SHIFT (31-23) 118e080313cSDave Liu #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 119e080313cSDave Liu #define SPCR_TSEC2DP_SHIFT (31-27) 120e080313cSDave Liu #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 121e080313cSDave Liu #define SPCR_TSEC2BDP_SHIFT (31-29) 122e080313cSDave Liu #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 123e080313cSDave Liu #define SPCR_TSEC2EP_SHIFT (31-31) 124e080313cSDave Liu #endif 125e080313cSDave Liu 126e080313cSDave Liu /* SICRL/H - System I/O Configuration Register Low/High 127e080313cSDave Liu */ 1283e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 129e080313cSDave Liu /* SICRL bits - MPC8349 specific */ 130e080313cSDave Liu #define SICRL_LDP_A 0x80000000 131e080313cSDave Liu #define SICRL_USB1 0x40000000 132e080313cSDave Liu #define SICRL_USB0 0x20000000 133e080313cSDave Liu #define SICRL_UART 0x0C000000 134e080313cSDave Liu #define SICRL_GPIO1_A 0x02000000 135e080313cSDave Liu #define SICRL_GPIO1_B 0x01000000 136e080313cSDave Liu #define SICRL_GPIO1_C 0x00800000 137e080313cSDave Liu #define SICRL_GPIO1_D 0x00400000 138e080313cSDave Liu #define SICRL_GPIO1_E 0x00200000 139e080313cSDave Liu #define SICRL_GPIO1_F 0x00180000 140e080313cSDave Liu #define SICRL_GPIO1_G 0x00040000 141e080313cSDave Liu #define SICRL_GPIO1_H 0x00020000 142e080313cSDave Liu #define SICRL_GPIO1_I 0x00010000 143e080313cSDave Liu #define SICRL_GPIO1_J 0x00008000 144e080313cSDave Liu #define SICRL_GPIO1_K 0x00004000 145e080313cSDave Liu #define SICRL_GPIO1_L 0x00003000 146e080313cSDave Liu 147e080313cSDave Liu /* SICRH bits - MPC8349 specific */ 148e080313cSDave Liu #define SICRH_DDR 0x80000000 149e080313cSDave Liu #define SICRH_TSEC1_A 0x10000000 150e080313cSDave Liu #define SICRH_TSEC1_B 0x08000000 151e080313cSDave Liu #define SICRH_TSEC1_C 0x04000000 152e080313cSDave Liu #define SICRH_TSEC1_D 0x02000000 153e080313cSDave Liu #define SICRH_TSEC1_E 0x01000000 154e080313cSDave Liu #define SICRH_TSEC1_F 0x00800000 155e080313cSDave Liu #define SICRH_TSEC2_A 0x00400000 156e080313cSDave Liu #define SICRH_TSEC2_B 0x00200000 157e080313cSDave Liu #define SICRH_TSEC2_C 0x00100000 158e080313cSDave Liu #define SICRH_TSEC2_D 0x00080000 159e080313cSDave Liu #define SICRH_TSEC2_E 0x00040000 160e080313cSDave Liu #define SICRH_TSEC2_F 0x00020000 161e080313cSDave Liu #define SICRH_TSEC2_G 0x00010000 162e080313cSDave Liu #define SICRH_TSEC2_H 0x00008000 163e080313cSDave Liu #define SICRH_GPIO2_A 0x00004000 164e080313cSDave Liu #define SICRH_GPIO2_B 0x00002000 165e080313cSDave Liu #define SICRH_GPIO2_C 0x00001000 166e080313cSDave Liu #define SICRH_GPIO2_D 0x00000800 167e080313cSDave Liu #define SICRH_GPIO2_E 0x00000400 168e080313cSDave Liu #define SICRH_GPIO2_F 0x00000200 169e080313cSDave Liu #define SICRH_GPIO2_G 0x00000180 170e080313cSDave Liu #define SICRH_GPIO2_H 0x00000060 171e080313cSDave Liu #define SICRH_TSOBI1 0x00000002 172e080313cSDave Liu #define SICRH_TSOBI2 0x00000001 173e080313cSDave Liu 174e080313cSDave Liu #elif defined(CONFIG_MPC8360) 175e080313cSDave Liu /* SICRL bits - MPC8360 specific */ 176e080313cSDave Liu #define SICRL_LDP_A 0xC0000000 177e080313cSDave Liu #define SICRL_LCLK_1 0x10000000 178e080313cSDave Liu #define SICRL_LCLK_2 0x08000000 179e080313cSDave Liu #define SICRL_SRCID_A 0x03000000 180e080313cSDave Liu #define SICRL_IRQ_CKSTP_A 0x00C00000 181e080313cSDave Liu 182e080313cSDave Liu /* SICRH bits - MPC8360 specific */ 183e080313cSDave Liu #define SICRH_DDR 0x80000000 184e080313cSDave Liu #define SICRH_SECONDARY_DDR 0x40000000 185e080313cSDave Liu #define SICRH_SDDROE 0x20000000 186e080313cSDave Liu #define SICRH_IRQ3 0x10000000 187e080313cSDave Liu #define SICRH_UC1EOBI 0x00000004 188e080313cSDave Liu #define SICRH_UC2E1OBI 0x00000002 189e080313cSDave Liu #define SICRH_UC2E2OBI 0x00000001 19024c3aca3SDave Liu 19124c3aca3SDave Liu #elif defined(CONFIG_MPC832X) 19224c3aca3SDave Liu /* SICRL bits - MPC832X specific */ 19324c3aca3SDave Liu #define SICRL_LDP_LCS_A 0x80000000 19424c3aca3SDave Liu #define SICRL_IRQ_CKS 0x20000000 19524c3aca3SDave Liu #define SICRL_PCI_MSRC 0x10000000 19624c3aca3SDave Liu #define SICRL_URT_CTPR 0x06000000 19724c3aca3SDave Liu #define SICRL_IRQ_CTPR 0x00C00000 198e080313cSDave Liu #endif 199e080313cSDave Liu 200e080313cSDave Liu /* SWCRR - System Watchdog Control Register 201e080313cSDave Liu */ 202e080313cSDave Liu #define SWCRR 0x0204 /* Register offset to immr */ 203e080313cSDave Liu #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 204e080313cSDave Liu #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 205e080313cSDave Liu #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 206e080313cSDave Liu #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 207e080313cSDave Liu #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 208e080313cSDave Liu 209e080313cSDave Liu /* SWCNR - System Watchdog Counter Register 210e080313cSDave Liu */ 211e080313cSDave Liu #define SWCNR 0x0208 /* Register offset to immr */ 212e080313cSDave Liu #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 213e080313cSDave Liu #define SWCNR_RES ~(SWCNR_SWCN) 214e080313cSDave Liu 215e080313cSDave Liu /* SWSRR - System Watchdog Service Register 216e080313cSDave Liu */ 217e080313cSDave Liu #define SWSRR 0x020E /* Register offset to immr */ 218e080313cSDave Liu 219e080313cSDave Liu /* ACR - Arbiter Configuration Register 220e080313cSDave Liu */ 221e080313cSDave Liu #define ACR_COREDIS 0x10000000 /* Core disable */ 222e080313cSDave Liu #define ACR_COREDIS_SHIFT (31-7) 223e080313cSDave Liu #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 224e080313cSDave Liu #define ACR_PIPE_DEP_SHIFT (31-15) 225e080313cSDave Liu #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 226e080313cSDave Liu #define ACR_PCI_RPTCNT_SHIFT (31-19) 227e080313cSDave Liu #define ACR_RPTCNT 0x00000700 /* Repeat count */ 228e080313cSDave Liu #define ACR_RPTCNT_SHIFT (31-23) 229e080313cSDave Liu #define ACR_APARK 0x00000030 /* Address parking */ 230e080313cSDave Liu #define ACR_APARK_SHIFT (31-27) 231e080313cSDave Liu #define ACR_PARKM 0x0000000F /* Parking master */ 232e080313cSDave Liu #define ACR_PARKM_SHIFT (31-31) 233e080313cSDave Liu 234e080313cSDave Liu /* ATR - Arbiter Timers Register 235e080313cSDave Liu */ 236e080313cSDave Liu #define ATR_DTO 0x00FF0000 /* Data time out */ 237e080313cSDave Liu #define ATR_ATO 0x000000FF /* Address time out */ 238e080313cSDave Liu 239e080313cSDave Liu /* AER - Arbiter Event Register 240e080313cSDave Liu */ 241e080313cSDave Liu #define AER_ETEA 0x00000020 /* Transfer error */ 242e080313cSDave Liu #define AER_RES 0x00000010 /* Reserved transfer type */ 243e080313cSDave Liu #define AER_ECW 0x00000008 /* External control word transfer type */ 244e080313cSDave Liu #define AER_AO 0x00000004 /* Address Only transfer type */ 245e080313cSDave Liu #define AER_DTO 0x00000002 /* Data time out */ 246e080313cSDave Liu #define AER_ATO 0x00000001 /* Address time out */ 247e080313cSDave Liu 248e080313cSDave Liu /* AEATR - Arbiter Event Address Register 249e080313cSDave Liu */ 250e080313cSDave Liu #define AEATR_EVENT 0x07000000 /* Event type */ 251e080313cSDave Liu #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 252e080313cSDave Liu #define AEATR_TBST 0x00000800 /* Transfer burst */ 253e080313cSDave Liu #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 254e080313cSDave Liu #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 255e080313cSDave Liu 256e080313cSDave Liu /* HRCWL - Hard Reset Configuration Word Low 257e080313cSDave Liu */ 258e080313cSDave Liu #define HRCWL_LBIUCM 0x80000000 259e080313cSDave Liu #define HRCWL_LBIUCM_SHIFT 31 260e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 261e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 262e080313cSDave Liu 263e080313cSDave Liu #define HRCWL_DDRCM 0x40000000 264e080313cSDave Liu #define HRCWL_DDRCM_SHIFT 30 265e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 266e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 267e080313cSDave Liu 268e080313cSDave Liu #define HRCWL_SPMF 0x0f000000 269e080313cSDave Liu #define HRCWL_SPMF_SHIFT 24 270e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 271e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 272e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 273e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 274e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 275e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 276e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 277e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 278e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 279e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 280e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 281e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 282e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 283e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 284e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 285e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 286e080313cSDave Liu 287e080313cSDave Liu #define HRCWL_VCO_BYPASS 0x00000000 288e080313cSDave Liu #define HRCWL_VCO_1X2 0x00000000 289e080313cSDave Liu #define HRCWL_VCO_1X4 0x00200000 290e080313cSDave Liu #define HRCWL_VCO_1X8 0x00400000 291e080313cSDave Liu 292e080313cSDave Liu #define HRCWL_COREPLL 0x007F0000 293e080313cSDave Liu #define HRCWL_COREPLL_SHIFT 16 294e080313cSDave Liu #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 295e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1X1 0x00020000 296e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 297e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2X1 0x00040000 298e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 299e080313cSDave Liu #define HRCWL_CORE_TO_CSB_3X1 0x00060000 300e080313cSDave Liu 30124c3aca3SDave Liu #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 302e080313cSDave Liu #define HRCWL_CEVCOD 0x000000C0 303e080313cSDave Liu #define HRCWL_CEVCOD_SHIFT 6 304e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 305e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 306e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 307e080313cSDave Liu 308e080313cSDave Liu #define HRCWL_CEPDF 0x00000020 309e080313cSDave Liu #define HRCWL_CEPDF_SHIFT 5 310e080313cSDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 311e080313cSDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 312e080313cSDave Liu 313e080313cSDave Liu #define HRCWL_CEPMF 0x0000001F 314e080313cSDave Liu #define HRCWL_CEPMF_SHIFT 0 315e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 316e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 317e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 318e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 319e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 320e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 321e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 322e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 323e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 324e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 325e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 326e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 327e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 328e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 329e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 330e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 331e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 332e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 333e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 334e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 335e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 336e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 337e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 338e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 339e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 340e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 341e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 342e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 343e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 344e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 345e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 346e080313cSDave Liu #endif 347e080313cSDave Liu 348e080313cSDave Liu /* HRCWH - Hardware Reset Configuration Word High 349e080313cSDave Liu */ 350e080313cSDave Liu #define HRCWH_PCI_HOST 0x80000000 351e080313cSDave Liu #define HRCWH_PCI_HOST_SHIFT 31 352e080313cSDave Liu #define HRCWH_PCI_AGENT 0x00000000 353e080313cSDave Liu 3543e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 355e080313cSDave Liu #define HRCWH_32_BIT_PCI 0x00000000 356e080313cSDave Liu #define HRCWH_64_BIT_PCI 0x40000000 357e080313cSDave Liu #endif 358e080313cSDave Liu 359e080313cSDave Liu #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 360e080313cSDave Liu #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 361e080313cSDave Liu 362e080313cSDave Liu #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 363e080313cSDave Liu #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 364e080313cSDave Liu 3653e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 366e080313cSDave Liu #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 367e080313cSDave Liu #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 368e080313cSDave Liu 369e080313cSDave Liu #elif defined(CONFIG_MPC8360) 370e080313cSDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 371e080313cSDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 372e080313cSDave Liu #endif 373e080313cSDave Liu 374e080313cSDave Liu #define HRCWH_CORE_DISABLE 0x08000000 375e080313cSDave Liu #define HRCWH_CORE_ENABLE 0x00000000 376e080313cSDave Liu 377e080313cSDave Liu #define HRCWH_FROM_0X00000100 0x00000000 378e080313cSDave Liu #define HRCWH_FROM_0XFFF00100 0x04000000 379e080313cSDave Liu 380e080313cSDave Liu #define HRCWH_BOOTSEQ_DISABLE 0x00000000 381e080313cSDave Liu #define HRCWH_BOOTSEQ_NORMAL 0x01000000 382e080313cSDave Liu #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 383e080313cSDave Liu 384e080313cSDave Liu #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 385e080313cSDave Liu #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 386e080313cSDave Liu 387e080313cSDave Liu #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 388e080313cSDave Liu #define HRCWH_ROM_LOC_PCI1 0x00100000 3893e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 390e080313cSDave Liu #define HRCWH_ROM_LOC_PCI2 0x00200000 391e080313cSDave Liu #endif 392e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 393e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 394e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 395e080313cSDave Liu 3963e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 397e080313cSDave Liu #define HRCWH_TSEC1M_IN_RGMII 0x00000000 398e080313cSDave Liu #define HRCWH_TSEC1M_IN_RTBI 0x00004000 399e080313cSDave Liu #define HRCWH_TSEC1M_IN_GMII 0x00008000 400e080313cSDave Liu #define HRCWH_TSEC1M_IN_TBI 0x0000C000 401e080313cSDave Liu #define HRCWH_TSEC2M_IN_RGMII 0x00000000 402e080313cSDave Liu #define HRCWH_TSEC2M_IN_RTBI 0x00001000 403e080313cSDave Liu #define HRCWH_TSEC2M_IN_GMII 0x00002000 404e080313cSDave Liu #define HRCWH_TSEC2M_IN_TBI 0x00003000 405e080313cSDave Liu #endif 406e080313cSDave Liu 407e080313cSDave Liu #if defined(CONFIG_MPC8360) 408e080313cSDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 409e080313cSDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 410e080313cSDave Liu #endif 411e080313cSDave Liu 412e080313cSDave Liu #define HRCWH_BIG_ENDIAN 0x00000000 413e080313cSDave Liu #define HRCWH_LITTLE_ENDIAN 0x00000008 414e080313cSDave Liu 415e080313cSDave Liu #define HRCWH_LALE_NORMAL 0x00000000 416e080313cSDave Liu #define HRCWH_LALE_EARLY 0x00000004 417e080313cSDave Liu 418e080313cSDave Liu #define HRCWH_LDP_SET 0x00000000 419e080313cSDave Liu #define HRCWH_LDP_CLEAR 0x00000002 420e080313cSDave Liu 421e080313cSDave Liu /* RSR - Reset Status Register 422e080313cSDave Liu */ 423e080313cSDave Liu #define RSR_RSTSRC 0xE0000000 /* Reset source */ 424e080313cSDave Liu #define RSR_RSTSRC_SHIFT 29 425e080313cSDave Liu #define RSR_BSF 0x00010000 /* Boot seq. fail */ 426e080313cSDave Liu #define RSR_BSF_SHIFT 16 427e080313cSDave Liu #define RSR_SWSR 0x00002000 /* software soft reset */ 428e080313cSDave Liu #define RSR_SWSR_SHIFT 13 429e080313cSDave Liu #define RSR_SWHR 0x00001000 /* software hard reset */ 430e080313cSDave Liu #define RSR_SWHR_SHIFT 12 431e080313cSDave Liu #define RSR_JHRS 0x00000200 /* jtag hreset */ 432e080313cSDave Liu #define RSR_JHRS_SHIFT 9 433e080313cSDave Liu #define RSR_JSRS 0x00000100 /* jtag sreset status */ 434e080313cSDave Liu #define RSR_JSRS_SHIFT 8 435e080313cSDave Liu #define RSR_CSHR 0x00000010 /* checkstop reset status */ 436e080313cSDave Liu #define RSR_CSHR_SHIFT 4 437e080313cSDave Liu #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 438e080313cSDave Liu #define RSR_SWRS_SHIFT 3 439e080313cSDave Liu #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 440e080313cSDave Liu #define RSR_BMRS_SHIFT 2 441e080313cSDave Liu #define RSR_SRS 0x00000002 /* soft reset status */ 442e080313cSDave Liu #define RSR_SRS_SHIFT 1 443e080313cSDave Liu #define RSR_HRS 0x00000001 /* hard reset status */ 444e080313cSDave Liu #define RSR_HRS_SHIFT 0 445e080313cSDave Liu #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 446e080313cSDave Liu RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 447e080313cSDave Liu RSR_BMRS | RSR_SRS | RSR_HRS) 448e080313cSDave Liu /* RMR - Reset Mode Register 449e080313cSDave Liu */ 450e080313cSDave Liu #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 451e080313cSDave Liu #define RMR_CSRE_SHIFT 0 452e080313cSDave Liu #define RMR_RES ~(RMR_CSRE) 453e080313cSDave Liu 454e080313cSDave Liu /* RCR - Reset Control Register 455e080313cSDave Liu */ 456e080313cSDave Liu #define RCR_SWHR 0x00000002 /* software hard reset */ 457e080313cSDave Liu #define RCR_SWSR 0x00000001 /* software soft reset */ 458e080313cSDave Liu #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 459e080313cSDave Liu 460e080313cSDave Liu /* RCER - Reset Control Enable Register 461e080313cSDave Liu */ 462e080313cSDave Liu #define RCER_CRE 0x00000001 /* software hard reset */ 463e080313cSDave Liu #define RCER_RES ~(RCER_CRE) 464e080313cSDave Liu 465e080313cSDave Liu /* SPMR - System PLL Mode Register 466e080313cSDave Liu */ 467e080313cSDave Liu #define SPMR_LBIUCM 0x80000000 468e080313cSDave Liu #define SPMR_DDRCM 0x40000000 469e080313cSDave Liu #define SPMR_SPMF 0x0F000000 470e080313cSDave Liu #define SPMR_CKID 0x00800000 471e080313cSDave Liu #define SPMR_CKID_SHIFT 23 472e080313cSDave Liu #define SPMR_COREPLL 0x007F0000 473e080313cSDave Liu #define SPMR_CEVCOD 0x000000C0 474e080313cSDave Liu #define SPMR_CEPDF 0x00000020 475e080313cSDave Liu #define SPMR_CEPMF 0x0000001F 476e080313cSDave Liu 477e080313cSDave Liu /* OCCR - Output Clock Control Register 478e080313cSDave Liu */ 479e080313cSDave Liu #define OCCR_PCICOE0 0x80000000 480e080313cSDave Liu #define OCCR_PCICOE1 0x40000000 481e080313cSDave Liu #define OCCR_PCICOE2 0x20000000 482e080313cSDave Liu #define OCCR_PCICOE3 0x10000000 483e080313cSDave Liu #define OCCR_PCICOE4 0x08000000 484e080313cSDave Liu #define OCCR_PCICOE5 0x04000000 485e080313cSDave Liu #define OCCR_PCICOE6 0x02000000 486e080313cSDave Liu #define OCCR_PCICOE7 0x01000000 487e080313cSDave Liu #define OCCR_PCICD0 0x00800000 488e080313cSDave Liu #define OCCR_PCICD1 0x00400000 489e080313cSDave Liu #define OCCR_PCICD2 0x00200000 490e080313cSDave Liu #define OCCR_PCICD3 0x00100000 491e080313cSDave Liu #define OCCR_PCICD4 0x00080000 492e080313cSDave Liu #define OCCR_PCICD5 0x00040000 493e080313cSDave Liu #define OCCR_PCICD6 0x00020000 494e080313cSDave Liu #define OCCR_PCICD7 0x00010000 495e080313cSDave Liu #define OCCR_PCI1CR 0x00000002 496e080313cSDave Liu #define OCCR_PCI2CR 0x00000001 497e080313cSDave Liu #define OCCR_PCICR OCCR_PCI1CR 498e080313cSDave Liu 499e080313cSDave Liu /* SCCR - System Clock Control Register 500e080313cSDave Liu */ 501e080313cSDave Liu #define SCCR_ENCCM 0x03000000 502e080313cSDave Liu #define SCCR_ENCCM_SHIFT 24 503e080313cSDave Liu #define SCCR_ENCCM_0 0x00000000 504e080313cSDave Liu #define SCCR_ENCCM_1 0x01000000 505e080313cSDave Liu #define SCCR_ENCCM_2 0x02000000 506e080313cSDave Liu #define SCCR_ENCCM_3 0x03000000 507e080313cSDave Liu 508e080313cSDave Liu #define SCCR_PCICM 0x00010000 509e080313cSDave Liu #define SCCR_PCICM_SHIFT 16 510e080313cSDave Liu 511e080313cSDave Liu /* SCCR bits - MPC8349 specific */ 512*4feab4deSKumar Gala #ifdef CONFIG_MPC834X 513e080313cSDave Liu #define SCCR_TSEC1CM 0xc0000000 514e080313cSDave Liu #define SCCR_TSEC1CM_SHIFT 30 515e080313cSDave Liu #define SCCR_TSEC1CM_0 0x00000000 516e080313cSDave Liu #define SCCR_TSEC1CM_1 0x40000000 517e080313cSDave Liu #define SCCR_TSEC1CM_2 0x80000000 518e080313cSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 519e080313cSDave Liu 520e080313cSDave Liu #define SCCR_TSEC2CM 0x30000000 521e080313cSDave Liu #define SCCR_TSEC2CM_SHIFT 28 522e080313cSDave Liu #define SCCR_TSEC2CM_0 0x00000000 523e080313cSDave Liu #define SCCR_TSEC2CM_1 0x10000000 524e080313cSDave Liu #define SCCR_TSEC2CM_2 0x20000000 525e080313cSDave Liu #define SCCR_TSEC2CM_3 0x30000000 526*4feab4deSKumar Gala #endif 527e080313cSDave Liu 528e080313cSDave Liu #define SCCR_USBMPHCM 0x00c00000 529e080313cSDave Liu #define SCCR_USBMPHCM_SHIFT 22 530e080313cSDave Liu #define SCCR_USBDRCM 0x00300000 531e080313cSDave Liu #define SCCR_USBDRCM_SHIFT 20 532e080313cSDave Liu 533e080313cSDave Liu #define SCCR_USBCM_0 0x00000000 534e080313cSDave Liu #define SCCR_USBCM_1 0x00500000 535e080313cSDave Liu #define SCCR_USBCM_2 0x00A00000 536e080313cSDave Liu #define SCCR_USBCM_3 0x00F00000 537e080313cSDave Liu 538e080313cSDave Liu /* CSn_BDNS - Chip Select memory Bounds Register 539e080313cSDave Liu */ 540e080313cSDave Liu #define CSBNDS_SA 0x00FF0000 541e080313cSDave Liu #define CSBNDS_SA_SHIFT 8 542e080313cSDave Liu #define CSBNDS_EA 0x000000FF 543e080313cSDave Liu #define CSBNDS_EA_SHIFT 24 544e080313cSDave Liu 545e080313cSDave Liu /* CSn_CONFIG - Chip Select Configuration Register 546e080313cSDave Liu */ 547e080313cSDave Liu #define CSCONFIG_EN 0x80000000 548e080313cSDave Liu #define CSCONFIG_AP 0x00800000 549e080313cSDave Liu #define CSCONFIG_ROW_BIT 0x00000700 550e080313cSDave Liu #define CSCONFIG_ROW_BIT_12 0x00000000 551e080313cSDave Liu #define CSCONFIG_ROW_BIT_13 0x00000100 552e080313cSDave Liu #define CSCONFIG_ROW_BIT_14 0x00000200 553e080313cSDave Liu #define CSCONFIG_COL_BIT 0x00000007 554e080313cSDave Liu #define CSCONFIG_COL_BIT_8 0x00000000 555e080313cSDave Liu #define CSCONFIG_COL_BIT_9 0x00000001 556e080313cSDave Liu #define CSCONFIG_COL_BIT_10 0x00000002 557e080313cSDave Liu #define CSCONFIG_COL_BIT_11 0x00000003 558e080313cSDave Liu 559e080313cSDave Liu /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 560e080313cSDave Liu */ 561e080313cSDave Liu #define TIMING_CFG1_PRETOACT 0x70000000 562e080313cSDave Liu #define TIMING_CFG1_PRETOACT_SHIFT 28 563e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE 0x0F000000 564e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE_SHIFT 24 565e080313cSDave Liu #define TIMING_CFG1_ACTTORW 0x00700000 566e080313cSDave Liu #define TIMING_CFG1_ACTTORW_SHIFT 20 567e080313cSDave Liu #define TIMING_CFG1_CASLAT 0x00070000 568e080313cSDave Liu #define TIMING_CFG1_CASLAT_SHIFT 16 569e080313cSDave Liu #define TIMING_CFG1_REFREC 0x0000F000 570e080313cSDave Liu #define TIMING_CFG1_REFREC_SHIFT 12 571e080313cSDave Liu #define TIMING_CFG1_WRREC 0x00000700 572e080313cSDave Liu #define TIMING_CFG1_WRREC_SHIFT 8 573e080313cSDave Liu #define TIMING_CFG1_ACTTOACT 0x00000070 574e080313cSDave Liu #define TIMING_CFG1_ACTTOACT_SHIFT 4 575e080313cSDave Liu #define TIMING_CFG1_WRTORD 0x00000007 576e080313cSDave Liu #define TIMING_CFG1_WRTORD_SHIFT 0 577e080313cSDave Liu #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 578e080313cSDave Liu #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 579e080313cSDave Liu 580e080313cSDave Liu /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 581e080313cSDave Liu */ 5828d172c0fSXie Xiaobo #define TIMING_CFG2_CPO 0x0F800000 5838d172c0fSXie Xiaobo #define TIMING_CFG2_CPO_SHIFT 23 584e080313cSDave Liu #define TIMING_CFG2_ACSM 0x00080000 585e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 586e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 587e080313cSDave Liu #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 588e080313cSDave Liu 589e080313cSDave Liu /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 590e080313cSDave Liu */ 591e080313cSDave Liu #define SDRAM_CFG_MEM_EN 0x80000000 592e080313cSDave Liu #define SDRAM_CFG_SREN 0x40000000 593e080313cSDave Liu #define SDRAM_CFG_ECC_EN 0x20000000 594e080313cSDave Liu #define SDRAM_CFG_RD_EN 0x10000000 595e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE 0x03000000 596e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 597e080313cSDave Liu #define SDRAM_CFG_DYN_PWR 0x00200000 598e080313cSDave Liu #define SDRAM_CFG_32_BE 0x00080000 599e080313cSDave Liu #define SDRAM_CFG_8_BE 0x00040000 600e080313cSDave Liu #define SDRAM_CFG_NCAP 0x00020000 601e080313cSDave Liu #define SDRAM_CFG_2T_EN 0x00008000 602e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 603e080313cSDave Liu 604e080313cSDave Liu /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 605e080313cSDave Liu */ 606e080313cSDave Liu #define SDRAM_MODE_ESD 0xFFFF0000 607e080313cSDave Liu #define SDRAM_MODE_ESD_SHIFT 16 608e080313cSDave Liu #define SDRAM_MODE_SD 0x0000FFFF 609e080313cSDave Liu #define SDRAM_MODE_SD_SHIFT 0 610e080313cSDave Liu #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 611e080313cSDave Liu #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 612e080313cSDave Liu #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 613e080313cSDave Liu #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 614e080313cSDave Liu #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 615e080313cSDave Liu #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 616e080313cSDave Liu #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 617e080313cSDave Liu #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 618e080313cSDave Liu #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 619e080313cSDave Liu #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 620e080313cSDave Liu #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 621e080313cSDave Liu #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 622e080313cSDave Liu #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 623e080313cSDave Liu #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 624e080313cSDave Liu #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 625e080313cSDave Liu #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 626e080313cSDave Liu #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 627e080313cSDave Liu #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 628e080313cSDave Liu #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 629e080313cSDave Liu 630e080313cSDave Liu /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 631e080313cSDave Liu */ 632e080313cSDave Liu #define SDRAM_INTERVAL_REFINT 0x3FFF0000 633e080313cSDave Liu #define SDRAM_INTERVAL_REFINT_SHIFT 16 634e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 635e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 636e080313cSDave Liu 637e080313cSDave Liu /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 638e080313cSDave Liu */ 639e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 640e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 641e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 642e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 643e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 644e080313cSDave Liu 645e080313cSDave Liu /* ECC_ERR_INJECT - Memory data path error injection mask ECC 646e080313cSDave Liu */ 647e080313cSDave Liu #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 648e080313cSDave Liu #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 649e080313cSDave Liu #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 650e080313cSDave Liu #define ECC_ERR_INJECT_EEIM_SHIFT 0 651e080313cSDave Liu 652e080313cSDave Liu /* CAPTURE_ECC - Memory data path read capture ECC 653e080313cSDave Liu */ 654e080313cSDave Liu #define CAPTURE_ECC_ECE (0xff000000>>24) 655e080313cSDave Liu #define CAPTURE_ECC_ECE_SHIFT 0 656e080313cSDave Liu 657e080313cSDave Liu /* ERR_DETECT - Memory error detect 658e080313cSDave Liu */ 659e080313cSDave Liu #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 660e080313cSDave Liu #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 661e080313cSDave Liu #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 662e080313cSDave Liu #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 663e080313cSDave Liu 664e080313cSDave Liu /* ERR_DISABLE - Memory error disable 665e080313cSDave Liu */ 666e080313cSDave Liu #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 667e080313cSDave Liu #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 668e080313cSDave Liu #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 669e080313cSDave Liu #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 670e080313cSDave Liu ECC_ERROR_DISABLE_MBED) 671e080313cSDave Liu /* ERR_INT_EN - Memory error interrupt enable 672e080313cSDave Liu */ 673e080313cSDave Liu #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 674e080313cSDave Liu #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 675e080313cSDave Liu #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 676e080313cSDave Liu #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 677e080313cSDave Liu ECC_ERR_INT_EN_MSEE) 678e080313cSDave Liu /* CAPTURE_ATTRIBUTES - Memory error attributes capture 679e080313cSDave Liu */ 680e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 681e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM_SHIFT 28 682e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 683e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 684e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 685e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 686e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 687e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 688e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 689e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 690e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 691e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 692e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 693e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 694e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 695e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_I2C 0x9 696e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 697e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 698e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 699e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_DMA 0xF 700e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_SHIFT 16 701e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 702e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 703e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_READ 0x2 704e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 705e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_SHIFT 12 706e080313cSDave Liu #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 707e080313cSDave Liu 708e080313cSDave Liu /* ERR_SBE - Single bit ECC memory error management 709e080313cSDave Liu */ 710e080313cSDave Liu #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 711e080313cSDave Liu #define ECC_ERROR_MAN_SBET_SHIFT 16 712e080313cSDave Liu #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 713e080313cSDave Liu #define ECC_ERROR_MAN_SBEC_SHIFT 0 714e080313cSDave Liu 715e080313cSDave Liu /* BR - Base Registers 716e080313cSDave Liu */ 717e080313cSDave Liu #define BR0 0x5000 /* Register offset to immr */ 718f046ccd1SEran Liberty #define BR1 0x5008 719f046ccd1SEran Liberty #define BR2 0x5010 720f046ccd1SEran Liberty #define BR3 0x5018 721f046ccd1SEran Liberty #define BR4 0x5020 722f046ccd1SEran Liberty #define BR5 0x5028 723f046ccd1SEran Liberty #define BR6 0x5030 724f046ccd1SEran Liberty #define BR7 0x5038 725f046ccd1SEran Liberty 726f046ccd1SEran Liberty #define BR_BA 0xFFFF8000 727f046ccd1SEran Liberty #define BR_BA_SHIFT 15 728f046ccd1SEran Liberty #define BR_PS 0x00001800 729f046ccd1SEran Liberty #define BR_PS_SHIFT 11 730e6f2e902SMarian Balakowicz #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 731e6f2e902SMarian Balakowicz #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 732e6f2e902SMarian Balakowicz #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 733f046ccd1SEran Liberty #define BR_DECC 0x00000600 734f046ccd1SEran Liberty #define BR_DECC_SHIFT 9 735f046ccd1SEran Liberty #define BR_WP 0x00000100 736f046ccd1SEran Liberty #define BR_WP_SHIFT 8 737f046ccd1SEran Liberty #define BR_MSEL 0x000000E0 738f046ccd1SEran Liberty #define BR_MSEL_SHIFT 5 739e6f2e902SMarian Balakowicz #define BR_MS_GPCM 0x00000000 /* GPCM */ 740e6f2e902SMarian Balakowicz #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 741e6f2e902SMarian Balakowicz #define BR_MS_UPMA 0x00000080 /* UPMA */ 742e6f2e902SMarian Balakowicz #define BR_MS_UPMB 0x000000A0 /* UPMB */ 743e6f2e902SMarian Balakowicz #define BR_MS_UPMC 0x000000C0 /* UPMC */ 74424c3aca3SDave Liu #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 7455f820439SDave Liu #define BR_ATOM 0x0000000C 7465f820439SDave Liu #define BR_ATOM_SHIFT 2 7475f820439SDave Liu #endif 748f046ccd1SEran Liberty #define BR_V 0x00000001 749f046ccd1SEran Liberty #define BR_V_SHIFT 0 750e080313cSDave Liu 7513e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 752f046ccd1SEran Liberty #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) 7535f820439SDave Liu #elif defined(CONFIG_MPC8360) 7545f820439SDave Liu #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) 7555f820439SDave Liu #endif 756f046ccd1SEran Liberty 757e080313cSDave Liu /* OR - Option Registers 758e080313cSDave Liu */ 759e080313cSDave Liu #define OR0 0x5004 /* Register offset to immr */ 760f046ccd1SEran Liberty #define OR1 0x500C 761f046ccd1SEran Liberty #define OR2 0x5014 762f046ccd1SEran Liberty #define OR3 0x501C 763f046ccd1SEran Liberty #define OR4 0x5024 764f046ccd1SEran Liberty #define OR5 0x502C 765f046ccd1SEran Liberty #define OR6 0x5034 766f046ccd1SEran Liberty #define OR7 0x503C 767f046ccd1SEran Liberty 768f046ccd1SEran Liberty #define OR_GPCM_AM 0xFFFF8000 769f046ccd1SEran Liberty #define OR_GPCM_AM_SHIFT 15 770f046ccd1SEran Liberty #define OR_GPCM_BCTLD 0x00001000 771f046ccd1SEran Liberty #define OR_GPCM_BCTLD_SHIFT 12 772f046ccd1SEran Liberty #define OR_GPCM_CSNT 0x00000800 773f046ccd1SEran Liberty #define OR_GPCM_CSNT_SHIFT 11 774f046ccd1SEran Liberty #define OR_GPCM_ACS 0x00000600 775f046ccd1SEran Liberty #define OR_GPCM_ACS_SHIFT 9 776e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b10 0x00000400 777e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b11 0x00000600 778f046ccd1SEran Liberty #define OR_GPCM_XACS 0x00000100 779f046ccd1SEran Liberty #define OR_GPCM_XACS_SHIFT 8 780f046ccd1SEran Liberty #define OR_GPCM_SCY 0x000000F0 781f046ccd1SEran Liberty #define OR_GPCM_SCY_SHIFT 4 782e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_1 0x00000010 783e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_2 0x00000020 784e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_3 0x00000030 785e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_4 0x00000040 786e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_5 0x00000050 787e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_6 0x00000060 788e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_7 0x00000070 789e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_8 0x00000080 790e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_9 0x00000090 791e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_10 0x000000a0 792e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_11 0x000000b0 793e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_12 0x000000c0 794e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_13 0x000000d0 795e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_14 0x000000e0 796e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_15 0x000000f0 797f046ccd1SEran Liberty #define OR_GPCM_SETA 0x00000008 798f046ccd1SEran Liberty #define OR_GPCM_SETA_SHIFT 3 799f046ccd1SEran Liberty #define OR_GPCM_TRLX 0x00000004 800f046ccd1SEran Liberty #define OR_GPCM_TRLX_SHIFT 2 801f046ccd1SEran Liberty #define OR_GPCM_EHTR 0x00000002 802f046ccd1SEran Liberty #define OR_GPCM_EHTR_SHIFT 1 803f046ccd1SEran Liberty #define OR_GPCM_EAD 0x00000001 804f046ccd1SEran Liberty #define OR_GPCM_EAD_SHIFT 0 805f046ccd1SEran Liberty 806f046ccd1SEran Liberty #define OR_UPM_AM 0xFFFF8000 807f046ccd1SEran Liberty #define OR_UPM_AM_SHIFT 15 808f046ccd1SEran Liberty #define OR_UPM_XAM 0x00006000 809f046ccd1SEran Liberty #define OR_UPM_XAM_SHIFT 13 810f046ccd1SEran Liberty #define OR_UPM_BCTLD 0x00001000 811f046ccd1SEran Liberty #define OR_UPM_BCTLD_SHIFT 12 812f046ccd1SEran Liberty #define OR_UPM_BI 0x00000100 813f046ccd1SEran Liberty #define OR_UPM_BI_SHIFT 8 814f046ccd1SEran Liberty #define OR_UPM_TRLX 0x00000004 815f046ccd1SEran Liberty #define OR_UPM_TRLX_SHIFT 2 816f046ccd1SEran Liberty #define OR_UPM_EHTR 0x00000002 817f046ccd1SEran Liberty #define OR_UPM_EHTR_SHIFT 1 818f046ccd1SEran Liberty #define OR_UPM_EAD 0x00000001 819f046ccd1SEran Liberty #define OR_UPM_EAD_SHIFT 0 820f046ccd1SEran Liberty 821f046ccd1SEran Liberty #define OR_SDRAM_AM 0xFFFF8000 822f046ccd1SEran Liberty #define OR_SDRAM_AM_SHIFT 15 823f046ccd1SEran Liberty #define OR_SDRAM_XAM 0x00006000 824f046ccd1SEran Liberty #define OR_SDRAM_XAM_SHIFT 13 825f046ccd1SEran Liberty #define OR_SDRAM_COLS 0x00001C00 826f046ccd1SEran Liberty #define OR_SDRAM_COLS_SHIFT 10 827f046ccd1SEran Liberty #define OR_SDRAM_ROWS 0x000001C0 828f046ccd1SEran Liberty #define OR_SDRAM_ROWS_SHIFT 6 829f046ccd1SEran Liberty #define OR_SDRAM_PMSEL 0x00000020 830f046ccd1SEran Liberty #define OR_SDRAM_PMSEL_SHIFT 5 831f046ccd1SEran Liberty #define OR_SDRAM_EAD 0x00000001 832f046ccd1SEran Liberty #define OR_SDRAM_EAD_SHIFT 0 833f046ccd1SEran Liberty 8347a78f148STimur Tabi #define OR_AM_32KB 0xFFFF8000 8357a78f148STimur Tabi #define OR_AM_64KB 0xFFFF0000 8367a78f148STimur Tabi #define OR_AM_128KB 0xFFFE0000 8377a78f148STimur Tabi #define OR_AM_256KB 0xFFFC0000 8387a78f148STimur Tabi #define OR_AM_512KB 0xFFF80000 8397a78f148STimur Tabi #define OR_AM_1MB 0xFFF00000 8407a78f148STimur Tabi #define OR_AM_2MB 0xFFE00000 8417a78f148STimur Tabi #define OR_AM_4MB 0xFFC00000 8427a78f148STimur Tabi #define OR_AM_8MB 0xFF800000 8437a78f148STimur Tabi #define OR_AM_16MB 0xFF000000 8447a78f148STimur Tabi #define OR_AM_32MB 0xFE000000 8457a78f148STimur Tabi #define OR_AM_64MB 0xFC000000 8467a78f148STimur Tabi #define OR_AM_128MB 0xF8000000 8477a78f148STimur Tabi #define OR_AM_256MB 0xF0000000 8487a78f148STimur Tabi #define OR_AM_512MB 0xE0000000 8497a78f148STimur Tabi #define OR_AM_1GB 0xC0000000 8507a78f148STimur Tabi #define OR_AM_2GB 0x80000000 8517a78f148STimur Tabi #define OR_AM_4GB 0x00000000 8527a78f148STimur Tabi 8537a78f148STimur Tabi #define LBLAWAR_EN 0x80000000 8547a78f148STimur Tabi #define LBLAWAR_4KB 0x0000000B 8557a78f148STimur Tabi #define LBLAWAR_8KB 0x0000000C 8567a78f148STimur Tabi #define LBLAWAR_16KB 0x0000000D 8577a78f148STimur Tabi #define LBLAWAR_32KB 0x0000000E 8587a78f148STimur Tabi #define LBLAWAR_64KB 0x0000000F 8597a78f148STimur Tabi #define LBLAWAR_128KB 0x00000010 8607a78f148STimur Tabi #define LBLAWAR_256KB 0x00000011 8617a78f148STimur Tabi #define LBLAWAR_512KB 0x00000012 8627a78f148STimur Tabi #define LBLAWAR_1MB 0x00000013 8637a78f148STimur Tabi #define LBLAWAR_2MB 0x00000014 8647a78f148STimur Tabi #define LBLAWAR_4MB 0x00000015 8657a78f148STimur Tabi #define LBLAWAR_8MB 0x00000016 8667a78f148STimur Tabi #define LBLAWAR_16MB 0x00000017 8677a78f148STimur Tabi #define LBLAWAR_32MB 0x00000018 8687a78f148STimur Tabi #define LBLAWAR_64MB 0x00000019 8697a78f148STimur Tabi #define LBLAWAR_128MB 0x0000001A 8707a78f148STimur Tabi #define LBLAWAR_256MB 0x0000001B 8717a78f148STimur Tabi #define LBLAWAR_512MB 0x0000001C 8727a78f148STimur Tabi #define LBLAWAR_1GB 0x0000001D 8737a78f148STimur Tabi #define LBLAWAR_2GB 0x0000001E 8747a78f148STimur Tabi 875e080313cSDave Liu /* LBCR - Local Bus Configuration Register 876f046ccd1SEran Liberty */ 877e080313cSDave Liu #define LBCR_LDIS 0x80000000 878e080313cSDave Liu #define LBCR_LDIS_SHIFT 31 879e080313cSDave Liu #define LBCR_BCTLC 0x00C00000 880e080313cSDave Liu #define LBCR_BCTLC_SHIFT 22 881e080313cSDave Liu #define LBCR_LPBSE 0x00020000 882e080313cSDave Liu #define LBCR_LPBSE_SHIFT 17 883e080313cSDave Liu #define LBCR_EPAR 0x00010000 884e080313cSDave Liu #define LBCR_EPAR_SHIFT 16 885e080313cSDave Liu #define LBCR_BMT 0x0000FF00 886e080313cSDave Liu #define LBCR_BMT_SHIFT 8 887f046ccd1SEran Liberty 888e080313cSDave Liu /* LCRR - Clock Ratio Register 889f046ccd1SEran Liberty */ 890f046ccd1SEran Liberty #define LCRR_DBYP 0x80000000 891f046ccd1SEran Liberty #define LCRR_DBYP_SHIFT 31 892f046ccd1SEran Liberty #define LCRR_BUFCMDC 0x30000000 893e080313cSDave Liu #define LCRR_BUFCMDC_SHIFT 28 894f046ccd1SEran Liberty #define LCRR_BUFCMDC_1 0x10000000 895f046ccd1SEran Liberty #define LCRR_BUFCMDC_2 0x20000000 896f046ccd1SEran Liberty #define LCRR_BUFCMDC_3 0x30000000 897f046ccd1SEran Liberty #define LCRR_BUFCMDC_4 0x00000000 898f046ccd1SEran Liberty #define LCRR_ECL 0x03000000 899e080313cSDave Liu #define LCRR_ECL_SHIFT 24 900f046ccd1SEran Liberty #define LCRR_ECL_4 0x00000000 901f046ccd1SEran Liberty #define LCRR_ECL_5 0x01000000 902f046ccd1SEran Liberty #define LCRR_ECL_6 0x02000000 903f046ccd1SEran Liberty #define LCRR_ECL_7 0x03000000 904f046ccd1SEran Liberty #define LCRR_EADC 0x00030000 905e080313cSDave Liu #define LCRR_EADC_SHIFT 16 906f046ccd1SEran Liberty #define LCRR_EADC_1 0x00010000 907f046ccd1SEran Liberty #define LCRR_EADC_2 0x00020000 908f046ccd1SEran Liberty #define LCRR_EADC_3 0x00030000 909f046ccd1SEran Liberty #define LCRR_EADC_4 0x00000000 910f046ccd1SEran Liberty #define LCRR_CLKDIV 0x0000000F 911e080313cSDave Liu #define LCRR_CLKDIV_SHIFT 0 912f046ccd1SEran Liberty #define LCRR_CLKDIV_2 0x00000002 913f046ccd1SEran Liberty #define LCRR_CLKDIV_4 0x00000004 914f046ccd1SEran Liberty #define LCRR_CLKDIV_8 0x00000008 915f046ccd1SEran Liberty 916e080313cSDave Liu /* DMAMR - DMA Mode Register 917f6eda7f8SDave Liu */ 918e080313cSDave Liu #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 919e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 920e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 921e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 922e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 923e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 924e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 925e080313cSDave Liu #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 926f6eda7f8SDave Liu 927e080313cSDave Liu /* DMASR - DMA Status Register 928e080313cSDave Liu */ 929e080313cSDave Liu #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 930e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 9315f820439SDave Liu 932e080313cSDave Liu /* CONFIG_ADDRESS - PCI Config Address Register 933e080313cSDave Liu */ 934e080313cSDave Liu #define PCI_CONFIG_ADDRESS_EN 0x80000000 935e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 936e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 937e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 938e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 939e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 940e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 941e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 942e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 943e080313cSDave Liu 944e080313cSDave Liu /* POTAR - PCI Outbound Translation Address Register 945e080313cSDave Liu */ 946e080313cSDave Liu #define POTAR_TA_MASK 0x000fffff 947e080313cSDave Liu 948e080313cSDave Liu /* POBAR - PCI Outbound Base Address Register 949e080313cSDave Liu */ 950e080313cSDave Liu #define POBAR_BA_MASK 0x000fffff 951e080313cSDave Liu 952e080313cSDave Liu /* POCMR - PCI Outbound Comparision Mask Register 953e080313cSDave Liu */ 954e080313cSDave Liu #define POCMR_EN 0x80000000 955e080313cSDave Liu #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 956e080313cSDave Liu #define POCMR_SE 0x20000000 /* streaming enable */ 957e080313cSDave Liu #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 958e080313cSDave Liu #define POCMR_CM_MASK 0x000fffff 959e080313cSDave Liu #define POCMR_CM_4G 0x00000000 960e080313cSDave Liu #define POCMR_CM_2G 0x00080000 961e080313cSDave Liu #define POCMR_CM_1G 0x000C0000 962e080313cSDave Liu #define POCMR_CM_512M 0x000E0000 963e080313cSDave Liu #define POCMR_CM_256M 0x000F0000 964e080313cSDave Liu #define POCMR_CM_128M 0x000F8000 965e080313cSDave Liu #define POCMR_CM_64M 0x000FC000 966e080313cSDave Liu #define POCMR_CM_32M 0x000FE000 967e080313cSDave Liu #define POCMR_CM_16M 0x000FF000 968e080313cSDave Liu #define POCMR_CM_8M 0x000FF800 969e080313cSDave Liu #define POCMR_CM_4M 0x000FFC00 970e080313cSDave Liu #define POCMR_CM_2M 0x000FFE00 971e080313cSDave Liu #define POCMR_CM_1M 0x000FFF00 972e080313cSDave Liu #define POCMR_CM_512K 0x000FFF80 973e080313cSDave Liu #define POCMR_CM_256K 0x000FFFC0 974e080313cSDave Liu #define POCMR_CM_128K 0x000FFFE0 975e080313cSDave Liu #define POCMR_CM_64K 0x000FFFF0 976e080313cSDave Liu #define POCMR_CM_32K 0x000FFFF8 977e080313cSDave Liu #define POCMR_CM_16K 0x000FFFFC 978e080313cSDave Liu #define POCMR_CM_8K 0x000FFFFE 979e080313cSDave Liu #define POCMR_CM_4K 0x000FFFFF 980e080313cSDave Liu 981e080313cSDave Liu /* PITAR - PCI Inbound Translation Address Register 982e080313cSDave Liu */ 983e080313cSDave Liu #define PITAR_TA_MASK 0x000fffff 984e080313cSDave Liu 985e080313cSDave Liu /* PIBAR - PCI Inbound Base/Extended Address Register 986e080313cSDave Liu */ 987e080313cSDave Liu #define PIBAR_MASK 0xffffffff 988e080313cSDave Liu #define PIEBAR_EBA_MASK 0x000fffff 989e080313cSDave Liu 990e080313cSDave Liu /* PIWAR - PCI Inbound Windows Attributes Register 991e080313cSDave Liu */ 992e080313cSDave Liu #define PIWAR_EN 0x80000000 993e080313cSDave Liu #define PIWAR_PF 0x20000000 994e080313cSDave Liu #define PIWAR_RTT_MASK 0x000f0000 995e080313cSDave Liu #define PIWAR_RTT_NO_SNOOP 0x00040000 996e080313cSDave Liu #define PIWAR_RTT_SNOOP 0x00050000 997e080313cSDave Liu #define PIWAR_WTT_MASK 0x0000f000 998e080313cSDave Liu #define PIWAR_WTT_NO_SNOOP 0x00004000 999e080313cSDave Liu #define PIWAR_WTT_SNOOP 0x00005000 1000e080313cSDave Liu #define PIWAR_IWS_MASK 0x0000003F 1001e080313cSDave Liu #define PIWAR_IWS_4K 0x0000000B 1002e080313cSDave Liu #define PIWAR_IWS_8K 0x0000000C 1003e080313cSDave Liu #define PIWAR_IWS_16K 0x0000000D 1004e080313cSDave Liu #define PIWAR_IWS_32K 0x0000000E 1005e080313cSDave Liu #define PIWAR_IWS_64K 0x0000000F 1006e080313cSDave Liu #define PIWAR_IWS_128K 0x00000010 1007e080313cSDave Liu #define PIWAR_IWS_256K 0x00000011 1008e080313cSDave Liu #define PIWAR_IWS_512K 0x00000012 1009e080313cSDave Liu #define PIWAR_IWS_1M 0x00000013 1010e080313cSDave Liu #define PIWAR_IWS_2M 0x00000014 1011e080313cSDave Liu #define PIWAR_IWS_4M 0x00000015 1012e080313cSDave Liu #define PIWAR_IWS_8M 0x00000016 1013e080313cSDave Liu #define PIWAR_IWS_16M 0x00000017 1014e080313cSDave Liu #define PIWAR_IWS_32M 0x00000018 1015e080313cSDave Liu #define PIWAR_IWS_64M 0x00000019 1016e080313cSDave Liu #define PIWAR_IWS_128M 0x0000001A 1017e080313cSDave Liu #define PIWAR_IWS_256M 0x0000001B 1018e080313cSDave Liu #define PIWAR_IWS_512M 0x0000001C 1019e080313cSDave Liu #define PIWAR_IWS_1G 0x0000001D 1020e080313cSDave Liu #define PIWAR_IWS_2G 0x0000001E 1021f6eda7f8SDave Liu 1022f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 1023