1f046ccd1SEran Liberty /* 203051c3dSDave Liu * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty */ 12f046ccd1SEran Liberty 13f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 14f046ccd1SEran Liberty #define __MPC83XX_H__ 15f046ccd1SEran Liberty 16f6eda7f8SDave Liu #include <config.h> 17bf30bb1fSAnton Vorontsov #include <asm/fsl_lbc.h> 18f046ccd1SEran Liberty #if defined(CONFIG_E300) 19f046ccd1SEran Liberty #include <asm/e300.h> 20f046ccd1SEran Liberty #endif 21f046ccd1SEran Liberty 22e080313cSDave Liu /* MPC83xx cpu provide RCR register to do reset thing specially 23f046ccd1SEran Liberty */ 24f046ccd1SEran Liberty #define MPC83xx_RESET 25f046ccd1SEran Liberty 26e080313cSDave Liu /* System reset offset (PowerPC standard) 27f046ccd1SEran Liberty */ 28f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 2902032e8fSRafal Jaworowski #define _START_OFFSET EXC_OFF_SYS_RESET 30f046ccd1SEran Liberty 31e080313cSDave Liu /* IMMRBAR - Internal Memory Register Base Address 32f046ccd1SEran Liberty */ 33e4c09508SScott Wood #ifndef CONFIG_DEFAULT_IMMR 34e080313cSDave Liu #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 35e4c09508SScott Wood #endif 36e080313cSDave Liu #define IMMRBAR 0x0000 /* Register offset to immr */ 37e080313cSDave Liu #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 38f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 39f046ccd1SEran Liberty 40e080313cSDave Liu /* LAWBAR - Local Access Window Base Address Register 41f046ccd1SEran Liberty */ 42e080313cSDave Liu #define LBLAWBAR0 0x0020 /* Register offset to immr */ 43f046ccd1SEran Liberty #define LBLAWAR0 0x0024 44f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 45f046ccd1SEran Liberty #define LBLAWAR1 0x002C 46f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 47f046ccd1SEran Liberty #define LBLAWAR2 0x0034 48f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 49f046ccd1SEran Liberty #define LBLAWAR3 0x003C 50e080313cSDave Liu #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 51f046ccd1SEran Liberty 52e080313cSDave Liu /* SPRIDR - System Part and Revision ID Register 53f6eda7f8SDave Liu */ 54e5c4ade4SKim Phillips #define SPRIDR_PARTID 0xFFFF0000 /* Part Id */ 55e5c4ade4SKim Phillips #define SPRIDR_REVID 0x0000FFFF /* Revision Id */ 56e080313cSDave Liu 57e5c4ade4SKim Phillips #if defined(CONFIG_MPC834X) 58e5c4ade4SKim Phillips #define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8) 59e5c4ade4SKim Phillips #define REVID_MINOR(spridr) (spridr & 0x000000FF) 60e5c4ade4SKim Phillips #else 61e5c4ade4SKim Phillips #define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4) 62e5c4ade4SKim Phillips #define REVID_MINOR(spridr) (spridr & 0x0000000F) 63e5c4ade4SKim Phillips #endif 645f820439SDave Liu 65e5c4ade4SKim Phillips #define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16) 666b70ffb9SKim Phillips #define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20) 675f820439SDave Liu 686b70ffb9SKim Phillips #define SPR_831X_FAMILY 0x80B 69e5c4ade4SKim Phillips #define SPR_8311 0x80B2 70e5c4ade4SKim Phillips #define SPR_8313 0x80B0 71e5c4ade4SKim Phillips #define SPR_8314 0x80B6 72e5c4ade4SKim Phillips #define SPR_8315 0x80B4 736b70ffb9SKim Phillips #define SPR_832X_FAMILY 0x806 74e5c4ade4SKim Phillips #define SPR_8321 0x8066 75e5c4ade4SKim Phillips #define SPR_8323 0x8062 766b70ffb9SKim Phillips #define SPR_834X_FAMILY 0x803 77e5c4ade4SKim Phillips #define SPR_8343 0x8036 78e5c4ade4SKim Phillips #define SPR_8347_TBGA_ 0x8032 79e5c4ade4SKim Phillips #define SPR_8347_PBGA_ 0x8034 80e5c4ade4SKim Phillips #define SPR_8349 0x8030 816b70ffb9SKim Phillips #define SPR_836X_FAMILY 0x804 82e5c4ade4SKim Phillips #define SPR_8358_TBGA_ 0x804A 83e5c4ade4SKim Phillips #define SPR_8358_PBGA_ 0x804E 84e5c4ade4SKim Phillips #define SPR_8360 0x8048 856b70ffb9SKim Phillips #define SPR_837X_FAMILY 0x80C 86e5c4ade4SKim Phillips #define SPR_8377 0x80C6 87e5c4ade4SKim Phillips #define SPR_8378 0x80C4 88e5c4ade4SKim Phillips #define SPR_8379 0x80C2 89d87c57b2SScott Wood 90e080313cSDave Liu /* SPCR - System Priority Configuration Register 91f046ccd1SEran Liberty */ 92e080313cSDave Liu #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 93e080313cSDave Liu #define SPCR_PCIHPE_SHIFT (31-3) 94e080313cSDave Liu #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 95e080313cSDave Liu #define SPCR_PCIPR_SHIFT (31-7) 96e080313cSDave Liu #define SPCR_OPT 0x00800000 /* Optimize */ 975bbeea86SMichael Barkowski #define SPCR_OPT_SHIFT (31-8) 98e080313cSDave Liu #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 99e080313cSDave Liu #define SPCR_TBEN_SHIFT (31-9) 100e080313cSDave Liu #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 101e080313cSDave Liu #define SPCR_COREPR_SHIFT (31-11) 102e080313cSDave Liu 1033e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 104e080313cSDave Liu /* SPCR bits - MPC8349 specific */ 105e080313cSDave Liu #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 106e080313cSDave Liu #define SPCR_TSEC1DP_SHIFT (31-19) 107e080313cSDave Liu #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 108e080313cSDave Liu #define SPCR_TSEC1BDP_SHIFT (31-21) 109e080313cSDave Liu #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 110e080313cSDave Liu #define SPCR_TSEC1EP_SHIFT (31-23) 111e080313cSDave Liu #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 112e080313cSDave Liu #define SPCR_TSEC2DP_SHIFT (31-27) 113e080313cSDave Liu #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 114e080313cSDave Liu #define SPCR_TSEC2BDP_SHIFT (31-29) 115e080313cSDave Liu #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 116e080313cSDave Liu #define SPCR_TSEC2EP_SHIFT (31-31) 117d87c57b2SScott Wood 11803051c3dSDave Liu #elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 11903051c3dSDave Liu /* SPCR bits - MPC831x and MPC837x specific */ 120d87c57b2SScott Wood #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 121d87c57b2SScott Wood #define SPCR_TSECDP_SHIFT (31-19) 122ec2638eaSDave Liu #define SPCR_TSECBDP 0x00000C00 /* TSEC buffer descriptor priority */ 123ec2638eaSDave Liu #define SPCR_TSECBDP_SHIFT (31-21) 124ec2638eaSDave Liu #define SPCR_TSECEP 0x00000300 /* TSEC emergency priority */ 125ec2638eaSDave Liu #define SPCR_TSECEP_SHIFT (31-23) 126e080313cSDave Liu #endif 127e080313cSDave Liu 128e080313cSDave Liu /* SICRL/H - System I/O Configuration Register Low/High 129e080313cSDave Liu */ 1303e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 131e080313cSDave Liu /* SICRL bits - MPC8349 specific */ 132e080313cSDave Liu #define SICRL_LDP_A 0x80000000 133e080313cSDave Liu #define SICRL_USB1 0x40000000 134e080313cSDave Liu #define SICRL_USB0 0x20000000 135e080313cSDave Liu #define SICRL_UART 0x0C000000 136e080313cSDave Liu #define SICRL_GPIO1_A 0x02000000 137e080313cSDave Liu #define SICRL_GPIO1_B 0x01000000 138e080313cSDave Liu #define SICRL_GPIO1_C 0x00800000 139e080313cSDave Liu #define SICRL_GPIO1_D 0x00400000 140e080313cSDave Liu #define SICRL_GPIO1_E 0x00200000 141e080313cSDave Liu #define SICRL_GPIO1_F 0x00180000 142e080313cSDave Liu #define SICRL_GPIO1_G 0x00040000 143e080313cSDave Liu #define SICRL_GPIO1_H 0x00020000 144e080313cSDave Liu #define SICRL_GPIO1_I 0x00010000 145e080313cSDave Liu #define SICRL_GPIO1_J 0x00008000 146e080313cSDave Liu #define SICRL_GPIO1_K 0x00004000 147e080313cSDave Liu #define SICRL_GPIO1_L 0x00003000 148e080313cSDave Liu 149e080313cSDave Liu /* SICRH bits - MPC8349 specific */ 150e080313cSDave Liu #define SICRH_DDR 0x80000000 151e080313cSDave Liu #define SICRH_TSEC1_A 0x10000000 152e080313cSDave Liu #define SICRH_TSEC1_B 0x08000000 153e080313cSDave Liu #define SICRH_TSEC1_C 0x04000000 154e080313cSDave Liu #define SICRH_TSEC1_D 0x02000000 155e080313cSDave Liu #define SICRH_TSEC1_E 0x01000000 156e080313cSDave Liu #define SICRH_TSEC1_F 0x00800000 157e080313cSDave Liu #define SICRH_TSEC2_A 0x00400000 158e080313cSDave Liu #define SICRH_TSEC2_B 0x00200000 159e080313cSDave Liu #define SICRH_TSEC2_C 0x00100000 160e080313cSDave Liu #define SICRH_TSEC2_D 0x00080000 161e080313cSDave Liu #define SICRH_TSEC2_E 0x00040000 162e080313cSDave Liu #define SICRH_TSEC2_F 0x00020000 163e080313cSDave Liu #define SICRH_TSEC2_G 0x00010000 164e080313cSDave Liu #define SICRH_TSEC2_H 0x00008000 165e080313cSDave Liu #define SICRH_GPIO2_A 0x00004000 166e080313cSDave Liu #define SICRH_GPIO2_B 0x00002000 167e080313cSDave Liu #define SICRH_GPIO2_C 0x00001000 168e080313cSDave Liu #define SICRH_GPIO2_D 0x00000800 169e080313cSDave Liu #define SICRH_GPIO2_E 0x00000400 170e080313cSDave Liu #define SICRH_GPIO2_F 0x00000200 171e080313cSDave Liu #define SICRH_GPIO2_G 0x00000180 172e080313cSDave Liu #define SICRH_GPIO2_H 0x00000060 173e080313cSDave Liu #define SICRH_TSOBI1 0x00000002 174e080313cSDave Liu #define SICRH_TSOBI2 0x00000001 175e080313cSDave Liu 176e080313cSDave Liu #elif defined(CONFIG_MPC8360) 177e080313cSDave Liu /* SICRL bits - MPC8360 specific */ 178e080313cSDave Liu #define SICRL_LDP_A 0xC0000000 179e080313cSDave Liu #define SICRL_LCLK_1 0x10000000 180e080313cSDave Liu #define SICRL_LCLK_2 0x08000000 181e080313cSDave Liu #define SICRL_SRCID_A 0x03000000 182e080313cSDave Liu #define SICRL_IRQ_CKSTP_A 0x00C00000 183e080313cSDave Liu 184e080313cSDave Liu /* SICRH bits - MPC8360 specific */ 185e080313cSDave Liu #define SICRH_DDR 0x80000000 186e080313cSDave Liu #define SICRH_SECONDARY_DDR 0x40000000 187e080313cSDave Liu #define SICRH_SDDROE 0x20000000 188e080313cSDave Liu #define SICRH_IRQ3 0x10000000 189e080313cSDave Liu #define SICRH_UC1EOBI 0x00000004 190e080313cSDave Liu #define SICRH_UC2E1OBI 0x00000002 191e080313cSDave Liu #define SICRH_UC2E2OBI 0x00000001 19224c3aca3SDave Liu 19324c3aca3SDave Liu #elif defined(CONFIG_MPC832X) 19424c3aca3SDave Liu /* SICRL bits - MPC832X specific */ 19524c3aca3SDave Liu #define SICRL_LDP_LCS_A 0x80000000 19624c3aca3SDave Liu #define SICRL_IRQ_CKS 0x20000000 19724c3aca3SDave Liu #define SICRL_PCI_MSRC 0x10000000 19824c3aca3SDave Liu #define SICRL_URT_CTPR 0x06000000 19924c3aca3SDave Liu #define SICRL_IRQ_CTPR 0x00C00000 200d87c57b2SScott Wood 201555da617SDave Liu #elif defined(CONFIG_MPC8313) 202555da617SDave Liu /* SICRL bits - MPC8313 specific */ 203d87c57b2SScott Wood #define SICRL_LBC 0x30000000 204d87c57b2SScott Wood #define SICRL_UART 0x0C000000 205d87c57b2SScott Wood #define SICRL_SPI_A 0x03000000 206d87c57b2SScott Wood #define SICRL_SPI_B 0x00C00000 207d87c57b2SScott Wood #define SICRL_SPI_C 0x00300000 208d87c57b2SScott Wood #define SICRL_SPI_D 0x000C0000 209d87c57b2SScott Wood #define SICRL_USBDR 0x00000C00 210d87c57b2SScott Wood #define SICRL_ETSEC1_A 0x0000000C 211d87c57b2SScott Wood #define SICRL_ETSEC2_A 0x00000003 212d87c57b2SScott Wood 213555da617SDave Liu /* SICRH bits - MPC8313 specific */ 214d87c57b2SScott Wood #define SICRH_INTR_A 0x02000000 215d87c57b2SScott Wood #define SICRH_INTR_B 0x00C00000 216d87c57b2SScott Wood #define SICRH_IIC 0x00300000 217d87c57b2SScott Wood #define SICRH_ETSEC2_B 0x000C0000 218d87c57b2SScott Wood #define SICRH_ETSEC2_C 0x00030000 219d87c57b2SScott Wood #define SICRH_ETSEC2_D 0x0000C000 220d87c57b2SScott Wood #define SICRH_ETSEC2_E 0x00003000 221d87c57b2SScott Wood #define SICRH_ETSEC2_F 0x00000C00 222d87c57b2SScott Wood #define SICRH_ETSEC2_G 0x00000300 223d87c57b2SScott Wood #define SICRH_ETSEC1_B 0x00000080 224d87c57b2SScott Wood #define SICRH_ETSEC1_C 0x00000060 225d87c57b2SScott Wood #define SICRH_GTX1_DLY 0x00000008 226d87c57b2SScott Wood #define SICRH_GTX2_DLY 0x00000004 227d87c57b2SScott Wood #define SICRH_TSOBI1 0x00000002 228d87c57b2SScott Wood #define SICRH_TSOBI2 0x00000001 229d87c57b2SScott Wood 230555da617SDave Liu #elif defined(CONFIG_MPC8315) 231555da617SDave Liu /* SICRL bits - MPC8315 specific */ 232555da617SDave Liu #define SICRL_DMA_CH0 0xc0000000 233555da617SDave Liu #define SICRL_DMA_SPI 0x30000000 234555da617SDave Liu #define SICRL_UART 0x0c000000 235555da617SDave Liu #define SICRL_IRQ4 0x02000000 236555da617SDave Liu #define SICRL_IRQ5 0x01800000 237555da617SDave Liu #define SICRL_IRQ6_7 0x00400000 238555da617SDave Liu #define SICRL_IIC1 0x00300000 239555da617SDave Liu #define SICRL_TDM 0x000c0000 240555da617SDave Liu #define SICRL_TDM_SHARED 0x00030000 241555da617SDave Liu #define SICRL_PCI_A 0x0000c000 242555da617SDave Liu #define SICRL_ELBC_A 0x00003000 243555da617SDave Liu #define SICRL_ETSEC1_A 0x000000c0 244555da617SDave Liu #define SICRL_ETSEC1_B 0x00000030 245555da617SDave Liu #define SICRL_ETSEC1_C 0x0000000c 246555da617SDave Liu #define SICRL_TSEXPOBI 0x00000001 247555da617SDave Liu 248555da617SDave Liu /* SICRH bits - MPC8315 specific */ 249555da617SDave Liu #define SICRH_GPIO_0 0xc0000000 250555da617SDave Liu #define SICRH_GPIO_1 0x30000000 251555da617SDave Liu #define SICRH_GPIO_2 0x0c000000 252555da617SDave Liu #define SICRH_GPIO_3 0x03000000 253555da617SDave Liu #define SICRH_GPIO_4 0x00c00000 254555da617SDave Liu #define SICRH_GPIO_5 0x00300000 255555da617SDave Liu #define SICRH_GPIO_6 0x000c0000 256555da617SDave Liu #define SICRH_GPIO_7 0x00030000 257555da617SDave Liu #define SICRH_GPIO_8 0x0000c000 258555da617SDave Liu #define SICRH_GPIO_9 0x00003000 259555da617SDave Liu #define SICRH_GPIO_10 0x00000c00 260555da617SDave Liu #define SICRH_GPIO_11 0x00000300 261555da617SDave Liu #define SICRH_ETSEC2_A 0x000000c0 262555da617SDave Liu #define SICRH_TSOBI1 0x00000002 263555da617SDave Liu #define SICRH_TSOBI2 0x00000001 264555da617SDave Liu 26503051c3dSDave Liu #elif defined(CONFIG_MPC837X) 26603051c3dSDave Liu /* SICRL bits - MPC837x specific */ 26703051c3dSDave Liu #define SICRL_USB_A 0xC0000000 26803051c3dSDave Liu #define SICRL_USB_B 0x30000000 26903051c3dSDave Liu #define SICRL_UART 0x0C000000 27003051c3dSDave Liu #define SICRL_GPIO_A 0x02000000 27103051c3dSDave Liu #define SICRL_GPIO_B 0x01000000 27203051c3dSDave Liu #define SICRL_GPIO_C 0x00800000 27303051c3dSDave Liu #define SICRL_GPIO_D 0x00400000 27403051c3dSDave Liu #define SICRL_GPIO_E 0x00200000 27503051c3dSDave Liu #define SICRL_GPIO_F 0x00180000 27603051c3dSDave Liu #define SICRL_GPIO_G 0x00040000 27703051c3dSDave Liu #define SICRL_GPIO_H 0x00020000 27803051c3dSDave Liu #define SICRL_GPIO_I 0x00010000 27903051c3dSDave Liu #define SICRL_GPIO_J 0x00008000 28003051c3dSDave Liu #define SICRL_GPIO_K 0x00004000 28103051c3dSDave Liu #define SICRL_GPIO_L 0x00003000 28203051c3dSDave Liu #define SICRL_DMA_A 0x00000800 28303051c3dSDave Liu #define SICRL_DMA_B 0x00000400 28403051c3dSDave Liu #define SICRL_DMA_C 0x00000200 28503051c3dSDave Liu #define SICRL_DMA_D 0x00000100 28603051c3dSDave Liu #define SICRL_DMA_E 0x00000080 28703051c3dSDave Liu #define SICRL_DMA_F 0x00000040 28803051c3dSDave Liu #define SICRL_DMA_G 0x00000020 28903051c3dSDave Liu #define SICRL_DMA_H 0x00000010 29003051c3dSDave Liu #define SICRL_DMA_I 0x00000008 29103051c3dSDave Liu #define SICRL_DMA_J 0x00000004 29203051c3dSDave Liu #define SICRL_LDP_A 0x00000002 29303051c3dSDave Liu #define SICRL_LDP_B 0x00000001 29403051c3dSDave Liu 29503051c3dSDave Liu /* SICRH bits - MPC837x specific */ 29603051c3dSDave Liu #define SICRH_DDR 0x80000000 29703051c3dSDave Liu #define SICRH_TSEC1_A 0x10000000 29803051c3dSDave Liu #define SICRH_TSEC1_B 0x08000000 29903051c3dSDave Liu #define SICRH_TSEC2_A 0x00400000 30003051c3dSDave Liu #define SICRH_TSEC2_B 0x00200000 30103051c3dSDave Liu #define SICRH_TSEC2_C 0x00100000 30203051c3dSDave Liu #define SICRH_TSEC2_D 0x00080000 30303051c3dSDave Liu #define SICRH_TSEC2_E 0x00040000 30403051c3dSDave Liu #define SICRH_TMR 0x00010000 30503051c3dSDave Liu #define SICRH_GPIO2_A 0x00008000 30603051c3dSDave Liu #define SICRH_GPIO2_B 0x00004000 30703051c3dSDave Liu #define SICRH_GPIO2_C 0x00002000 30803051c3dSDave Liu #define SICRH_GPIO2_D 0x00001000 30903051c3dSDave Liu #define SICRH_GPIO2_E 0x00000C00 31003051c3dSDave Liu #define SICRH_GPIO2_F 0x00000300 31103051c3dSDave Liu #define SICRH_GPIO2_G 0x000000C0 31203051c3dSDave Liu #define SICRH_GPIO2_H 0x00000030 31303051c3dSDave Liu #define SICRH_SPI 0x00000003 314e080313cSDave Liu #endif 315e080313cSDave Liu 316e080313cSDave Liu /* SWCRR - System Watchdog Control Register 317e080313cSDave Liu */ 318e080313cSDave Liu #define SWCRR 0x0204 /* Register offset to immr */ 319e080313cSDave Liu #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 320e080313cSDave Liu #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 321e080313cSDave Liu #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 322e080313cSDave Liu #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 323e080313cSDave Liu #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 324e080313cSDave Liu 325e080313cSDave Liu /* SWCNR - System Watchdog Counter Register 326e080313cSDave Liu */ 327e080313cSDave Liu #define SWCNR 0x0208 /* Register offset to immr */ 328e080313cSDave Liu #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 329e080313cSDave Liu #define SWCNR_RES ~(SWCNR_SWCN) 330e080313cSDave Liu 331e080313cSDave Liu /* SWSRR - System Watchdog Service Register 332e080313cSDave Liu */ 333e080313cSDave Liu #define SWSRR 0x020E /* Register offset to immr */ 334e080313cSDave Liu 335e080313cSDave Liu /* ACR - Arbiter Configuration Register 336e080313cSDave Liu */ 337e080313cSDave Liu #define ACR_COREDIS 0x10000000 /* Core disable */ 338e080313cSDave Liu #define ACR_COREDIS_SHIFT (31-7) 339e080313cSDave Liu #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 340e080313cSDave Liu #define ACR_PIPE_DEP_SHIFT (31-15) 341e080313cSDave Liu #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 342e080313cSDave Liu #define ACR_PCI_RPTCNT_SHIFT (31-19) 343e080313cSDave Liu #define ACR_RPTCNT 0x00000700 /* Repeat count */ 344e080313cSDave Liu #define ACR_RPTCNT_SHIFT (31-23) 345e080313cSDave Liu #define ACR_APARK 0x00000030 /* Address parking */ 346e080313cSDave Liu #define ACR_APARK_SHIFT (31-27) 347e080313cSDave Liu #define ACR_PARKM 0x0000000F /* Parking master */ 348e080313cSDave Liu #define ACR_PARKM_SHIFT (31-31) 349e080313cSDave Liu 350e080313cSDave Liu /* ATR - Arbiter Timers Register 351e080313cSDave Liu */ 352e080313cSDave Liu #define ATR_DTO 0x00FF0000 /* Data time out */ 353002d27caSNick Spence #define ATR_DTO_SHIFT 16 354e080313cSDave Liu #define ATR_ATO 0x000000FF /* Address time out */ 355002d27caSNick Spence #define ATR_ATO_SHIFT 0 356e080313cSDave Liu 357e080313cSDave Liu /* AER - Arbiter Event Register 358e080313cSDave Liu */ 359e080313cSDave Liu #define AER_ETEA 0x00000020 /* Transfer error */ 360e080313cSDave Liu #define AER_RES 0x00000010 /* Reserved transfer type */ 361e080313cSDave Liu #define AER_ECW 0x00000008 /* External control word transfer type */ 362e080313cSDave Liu #define AER_AO 0x00000004 /* Address Only transfer type */ 363e080313cSDave Liu #define AER_DTO 0x00000002 /* Data time out */ 364e080313cSDave Liu #define AER_ATO 0x00000001 /* Address time out */ 365e080313cSDave Liu 366e080313cSDave Liu /* AEATR - Arbiter Event Address Register 367e080313cSDave Liu */ 368e080313cSDave Liu #define AEATR_EVENT 0x07000000 /* Event type */ 369002d27caSNick Spence #define AEATR_EVENT_SHIFT 24 370e080313cSDave Liu #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 371002d27caSNick Spence #define AEATR_MSTR_ID_SHIFT 16 372e080313cSDave Liu #define AEATR_TBST 0x00000800 /* Transfer burst */ 373002d27caSNick Spence #define AEATR_TBST_SHIFT 11 374e080313cSDave Liu #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 375002d27caSNick Spence #define AEATR_TSIZE_SHIFT 8 376e080313cSDave Liu #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 377002d27caSNick Spence #define AEATR_TTYPE_SHIFT 0 378e080313cSDave Liu 379e080313cSDave Liu /* HRCWL - Hard Reset Configuration Word Low 380e080313cSDave Liu */ 381e080313cSDave Liu #define HRCWL_LBIUCM 0x80000000 382e080313cSDave Liu #define HRCWL_LBIUCM_SHIFT 31 383e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 384e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 385e080313cSDave Liu 386e080313cSDave Liu #define HRCWL_DDRCM 0x40000000 387e080313cSDave Liu #define HRCWL_DDRCM_SHIFT 30 388e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 389e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 390e080313cSDave Liu 391e080313cSDave Liu #define HRCWL_SPMF 0x0f000000 392e080313cSDave Liu #define HRCWL_SPMF_SHIFT 24 393e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 394e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 395e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 396e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 397e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 398e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 399e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 400e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 401e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 402e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 403e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 404e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 405e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 406e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 407e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 408e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 409e080313cSDave Liu 410e080313cSDave Liu #define HRCWL_VCO_BYPASS 0x00000000 411e080313cSDave Liu #define HRCWL_VCO_1X2 0x00000000 412e080313cSDave Liu #define HRCWL_VCO_1X4 0x00200000 413e080313cSDave Liu #define HRCWL_VCO_1X8 0x00400000 414e080313cSDave Liu 415e080313cSDave Liu #define HRCWL_COREPLL 0x007F0000 416e080313cSDave Liu #define HRCWL_COREPLL_SHIFT 16 417e080313cSDave Liu #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 418e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1X1 0x00020000 419e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 420e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2X1 0x00040000 421e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 422e080313cSDave Liu #define HRCWL_CORE_TO_CSB_3X1 0x00060000 423e080313cSDave Liu 42424c3aca3SDave Liu #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 425e080313cSDave Liu #define HRCWL_CEVCOD 0x000000C0 426e080313cSDave Liu #define HRCWL_CEVCOD_SHIFT 6 427e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 428e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 429e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 430e080313cSDave Liu 431e080313cSDave Liu #define HRCWL_CEPDF 0x00000020 432e080313cSDave Liu #define HRCWL_CEPDF_SHIFT 5 433e080313cSDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 434e080313cSDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 435e080313cSDave Liu 436e080313cSDave Liu #define HRCWL_CEPMF 0x0000001F 437e080313cSDave Liu #define HRCWL_CEPMF_SHIFT 0 438e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 439e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 440e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 441e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 442e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 443e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 444e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 445e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 446e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 447e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 448e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 449e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 450e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 451e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 452e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 453e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 454e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 455e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 456e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 457e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 458e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 459e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 460e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 461e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 462e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 463e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 464e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 465e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 466e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 467e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 468e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 46903051c3dSDave Liu 4706f3931a2SDave Liu #elif defined(CONFIG_MPC8315) 4716f3931a2SDave Liu #define HRCWL_SVCOD 0x30000000 4726f3931a2SDave Liu #define HRCWL_SVCOD_SHIFT 28 4736f3931a2SDave Liu #define HRCWL_SVCOD_DIV_2 0x00000000 4746f3931a2SDave Liu #define HRCWL_SVCOD_DIV_4 0x10000000 4756f3931a2SDave Liu #define HRCWL_SVCOD_DIV_8 0x20000000 4766f3931a2SDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 4776f3931a2SDave Liu 4786f3931a2SDave Liu #elif defined(CONFIG_MPC837X) 47903051c3dSDave Liu #define HRCWL_SVCOD 0x30000000 48003051c3dSDave Liu #define HRCWL_SVCOD_SHIFT 28 48103051c3dSDave Liu #define HRCWL_SVCOD_DIV_4 0x00000000 48203051c3dSDave Liu #define HRCWL_SVCOD_DIV_8 0x10000000 48303051c3dSDave Liu #define HRCWL_SVCOD_DIV_2 0x20000000 48403051c3dSDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 485e080313cSDave Liu #endif 486e080313cSDave Liu 487e080313cSDave Liu /* HRCWH - Hardware Reset Configuration Word High 488e080313cSDave Liu */ 489e080313cSDave Liu #define HRCWH_PCI_HOST 0x80000000 490e080313cSDave Liu #define HRCWH_PCI_HOST_SHIFT 31 491e080313cSDave Liu #define HRCWH_PCI_AGENT 0x00000000 492e080313cSDave Liu 4933e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 494e080313cSDave Liu #define HRCWH_32_BIT_PCI 0x00000000 495e080313cSDave Liu #define HRCWH_64_BIT_PCI 0x40000000 496e080313cSDave Liu #endif 497e080313cSDave Liu 498e080313cSDave Liu #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 499e080313cSDave Liu #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 500e080313cSDave Liu 501e080313cSDave Liu #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 502e080313cSDave Liu #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 503e080313cSDave Liu 5043e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 505e080313cSDave Liu #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 506e080313cSDave Liu #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 507e080313cSDave Liu 508e080313cSDave Liu #elif defined(CONFIG_MPC8360) 509e080313cSDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 510e080313cSDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 511e080313cSDave Liu #endif 512e080313cSDave Liu 513e080313cSDave Liu #define HRCWH_CORE_DISABLE 0x08000000 514e080313cSDave Liu #define HRCWH_CORE_ENABLE 0x00000000 515e080313cSDave Liu 516e080313cSDave Liu #define HRCWH_FROM_0X00000100 0x00000000 517e080313cSDave Liu #define HRCWH_FROM_0XFFF00100 0x04000000 518e080313cSDave Liu 519e080313cSDave Liu #define HRCWH_BOOTSEQ_DISABLE 0x00000000 520e080313cSDave Liu #define HRCWH_BOOTSEQ_NORMAL 0x01000000 521e080313cSDave Liu #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 522e080313cSDave Liu 523e080313cSDave Liu #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 524e080313cSDave Liu #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 525e080313cSDave Liu 526e080313cSDave Liu #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 527e080313cSDave Liu #define HRCWH_ROM_LOC_PCI1 0x00100000 5283e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 529e080313cSDave Liu #define HRCWH_ROM_LOC_PCI2 0x00200000 530e080313cSDave Liu #endif 531*2fb29c52SNobuhiro Iwamatsu #if defined(CONFIG_MPC837X) 53203051c3dSDave Liu #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 53303051c3dSDave Liu #endif 534e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 535e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 536e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 537e080313cSDave Liu 53803051c3dSDave Liu #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 539d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 540d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 541d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 542d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 543d87c57b2SScott Wood 544d87c57b2SScott Wood #define HRCWH_RL_EXT_LEGACY 0x00000000 545d87c57b2SScott Wood #define HRCWH_RL_EXT_NAND 0x00040000 546d87c57b2SScott Wood 547d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_MII 0x00000000 548d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RMII 0x00002000 549d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RGMII 0x00006000 550d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 551d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 552d87c57b2SScott Wood 553d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_MII 0x00000000 554d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RMII 0x00000400 555d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 556d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RTBI 0x00001400 557d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_SGMII 0x00001800 558d87c57b2SScott Wood #endif 559d87c57b2SScott Wood 5603e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 561e080313cSDave Liu #define HRCWH_TSEC1M_IN_RGMII 0x00000000 562e080313cSDave Liu #define HRCWH_TSEC1M_IN_RTBI 0x00004000 563e080313cSDave Liu #define HRCWH_TSEC1M_IN_GMII 0x00008000 564e080313cSDave Liu #define HRCWH_TSEC1M_IN_TBI 0x0000C000 565e080313cSDave Liu #define HRCWH_TSEC2M_IN_RGMII 0x00000000 566e080313cSDave Liu #define HRCWH_TSEC2M_IN_RTBI 0x00001000 567e080313cSDave Liu #define HRCWH_TSEC2M_IN_GMII 0x00002000 568e080313cSDave Liu #define HRCWH_TSEC2M_IN_TBI 0x00003000 569e080313cSDave Liu #endif 570e080313cSDave Liu 571e080313cSDave Liu #if defined(CONFIG_MPC8360) 572e080313cSDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 573e080313cSDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 574e080313cSDave Liu #endif 575e080313cSDave Liu 576e080313cSDave Liu #define HRCWH_BIG_ENDIAN 0x00000000 577e080313cSDave Liu #define HRCWH_LITTLE_ENDIAN 0x00000008 578e080313cSDave Liu 579e080313cSDave Liu #define HRCWH_LALE_NORMAL 0x00000000 580e080313cSDave Liu #define HRCWH_LALE_EARLY 0x00000004 581e080313cSDave Liu 582e080313cSDave Liu #define HRCWH_LDP_SET 0x00000000 583e080313cSDave Liu #define HRCWH_LDP_CLEAR 0x00000002 584e080313cSDave Liu 585e080313cSDave Liu /* RSR - Reset Status Register 586e080313cSDave Liu */ 587555da617SDave Liu #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 58803051c3dSDave Liu #define RSR_RSTSRC 0xF0000000 /* Reset source */ 58903051c3dSDave Liu #define RSR_RSTSRC_SHIFT 28 59003051c3dSDave Liu #else 591e080313cSDave Liu #define RSR_RSTSRC 0xE0000000 /* Reset source */ 592e080313cSDave Liu #define RSR_RSTSRC_SHIFT 29 59303051c3dSDave Liu #endif 594e080313cSDave Liu #define RSR_BSF 0x00010000 /* Boot seq. fail */ 595e080313cSDave Liu #define RSR_BSF_SHIFT 16 596e080313cSDave Liu #define RSR_SWSR 0x00002000 /* software soft reset */ 597e080313cSDave Liu #define RSR_SWSR_SHIFT 13 598e080313cSDave Liu #define RSR_SWHR 0x00001000 /* software hard reset */ 599e080313cSDave Liu #define RSR_SWHR_SHIFT 12 600e080313cSDave Liu #define RSR_JHRS 0x00000200 /* jtag hreset */ 601e080313cSDave Liu #define RSR_JHRS_SHIFT 9 602e080313cSDave Liu #define RSR_JSRS 0x00000100 /* jtag sreset status */ 603e080313cSDave Liu #define RSR_JSRS_SHIFT 8 604e080313cSDave Liu #define RSR_CSHR 0x00000010 /* checkstop reset status */ 605e080313cSDave Liu #define RSR_CSHR_SHIFT 4 606e080313cSDave Liu #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 607e080313cSDave Liu #define RSR_SWRS_SHIFT 3 608e080313cSDave Liu #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 609e080313cSDave Liu #define RSR_BMRS_SHIFT 2 610e080313cSDave Liu #define RSR_SRS 0x00000002 /* soft reset status */ 611e080313cSDave Liu #define RSR_SRS_SHIFT 1 612e080313cSDave Liu #define RSR_HRS 0x00000001 /* hard reset status */ 613e080313cSDave Liu #define RSR_HRS_SHIFT 0 614e080313cSDave Liu #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 615e080313cSDave Liu RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 616e080313cSDave Liu RSR_BMRS | RSR_SRS | RSR_HRS) 617e080313cSDave Liu /* RMR - Reset Mode Register 618e080313cSDave Liu */ 619e080313cSDave Liu #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 620e080313cSDave Liu #define RMR_CSRE_SHIFT 0 621e080313cSDave Liu #define RMR_RES ~(RMR_CSRE) 622e080313cSDave Liu 623e080313cSDave Liu /* RCR - Reset Control Register 624e080313cSDave Liu */ 625e080313cSDave Liu #define RCR_SWHR 0x00000002 /* software hard reset */ 626e080313cSDave Liu #define RCR_SWSR 0x00000001 /* software soft reset */ 627e080313cSDave Liu #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 628e080313cSDave Liu 629e080313cSDave Liu /* RCER - Reset Control Enable Register 630e080313cSDave Liu */ 631e080313cSDave Liu #define RCER_CRE 0x00000001 /* software hard reset */ 632e080313cSDave Liu #define RCER_RES ~(RCER_CRE) 633e080313cSDave Liu 634e080313cSDave Liu /* SPMR - System PLL Mode Register 635e080313cSDave Liu */ 636e080313cSDave Liu #define SPMR_LBIUCM 0x80000000 637e080313cSDave Liu #define SPMR_DDRCM 0x40000000 638e080313cSDave Liu #define SPMR_SPMF 0x0F000000 639e080313cSDave Liu #define SPMR_CKID 0x00800000 640e080313cSDave Liu #define SPMR_CKID_SHIFT 23 641e080313cSDave Liu #define SPMR_COREPLL 0x007F0000 642e080313cSDave Liu #define SPMR_CEVCOD 0x000000C0 643e080313cSDave Liu #define SPMR_CEPDF 0x00000020 644e080313cSDave Liu #define SPMR_CEPMF 0x0000001F 645e080313cSDave Liu 646e080313cSDave Liu /* OCCR - Output Clock Control Register 647e080313cSDave Liu */ 648e080313cSDave Liu #define OCCR_PCICOE0 0x80000000 649e080313cSDave Liu #define OCCR_PCICOE1 0x40000000 650e080313cSDave Liu #define OCCR_PCICOE2 0x20000000 651e080313cSDave Liu #define OCCR_PCICOE3 0x10000000 652e080313cSDave Liu #define OCCR_PCICOE4 0x08000000 653e080313cSDave Liu #define OCCR_PCICOE5 0x04000000 654e080313cSDave Liu #define OCCR_PCICOE6 0x02000000 655e080313cSDave Liu #define OCCR_PCICOE7 0x01000000 656e080313cSDave Liu #define OCCR_PCICD0 0x00800000 657e080313cSDave Liu #define OCCR_PCICD1 0x00400000 658e080313cSDave Liu #define OCCR_PCICD2 0x00200000 659e080313cSDave Liu #define OCCR_PCICD3 0x00100000 660e080313cSDave Liu #define OCCR_PCICD4 0x00080000 661e080313cSDave Liu #define OCCR_PCICD5 0x00040000 662e080313cSDave Liu #define OCCR_PCICD6 0x00020000 663e080313cSDave Liu #define OCCR_PCICD7 0x00010000 664e080313cSDave Liu #define OCCR_PCI1CR 0x00000002 665e080313cSDave Liu #define OCCR_PCI2CR 0x00000001 666e080313cSDave Liu #define OCCR_PCICR OCCR_PCI1CR 667e080313cSDave Liu 668e080313cSDave Liu /* SCCR - System Clock Control Register 669e080313cSDave Liu */ 670e080313cSDave Liu #define SCCR_ENCCM 0x03000000 671e080313cSDave Liu #define SCCR_ENCCM_SHIFT 24 672e080313cSDave Liu #define SCCR_ENCCM_0 0x00000000 673e080313cSDave Liu #define SCCR_ENCCM_1 0x01000000 674e080313cSDave Liu #define SCCR_ENCCM_2 0x02000000 675e080313cSDave Liu #define SCCR_ENCCM_3 0x03000000 676e080313cSDave Liu 677e080313cSDave Liu #define SCCR_PCICM 0x00010000 678e080313cSDave Liu #define SCCR_PCICM_SHIFT 16 679e080313cSDave Liu 68003051c3dSDave Liu #if defined(CONFIG_MPC834X) 68103051c3dSDave Liu /* SCCR bits - MPC834x specific */ 682e080313cSDave Liu #define SCCR_TSEC1CM 0xc0000000 683e080313cSDave Liu #define SCCR_TSEC1CM_SHIFT 30 684e080313cSDave Liu #define SCCR_TSEC1CM_0 0x00000000 685e080313cSDave Liu #define SCCR_TSEC1CM_1 0x40000000 686e080313cSDave Liu #define SCCR_TSEC1CM_2 0x80000000 687e080313cSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 688e080313cSDave Liu 689e080313cSDave Liu #define SCCR_TSEC2CM 0x30000000 690e080313cSDave Liu #define SCCR_TSEC2CM_SHIFT 28 691e080313cSDave Liu #define SCCR_TSEC2CM_0 0x00000000 692e080313cSDave Liu #define SCCR_TSEC2CM_1 0x10000000 693e080313cSDave Liu #define SCCR_TSEC2CM_2 0x20000000 694e080313cSDave Liu #define SCCR_TSEC2CM_3 0x30000000 695d87c57b2SScott Wood 69603051c3dSDave Liu /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 69703051c3dSDave Liu #define SCCR_USBMPHCM 0x00c00000 69803051c3dSDave Liu #define SCCR_USBMPHCM_SHIFT 22 69903051c3dSDave Liu #define SCCR_USBDRCM 0x00300000 70003051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 20 70103051c3dSDave Liu #define SCCR_USBCM 0x00f00000 70203051c3dSDave Liu #define SCCR_USBCM_SHIFT 20 70303051c3dSDave Liu #define SCCR_USBCM_0 0x00000000 70403051c3dSDave Liu #define SCCR_USBCM_1 0x00500000 70503051c3dSDave Liu #define SCCR_USBCM_2 0x00A00000 70603051c3dSDave Liu #define SCCR_USBCM_3 0x00F00000 70703051c3dSDave Liu 708555da617SDave Liu #elif defined(CONFIG_MPC8313) 709a8cb43a8SDave Liu /* TSEC1 bits are for TSEC2 as well */ 710d87c57b2SScott Wood #define SCCR_TSEC1CM 0xc0000000 711d87c57b2SScott Wood #define SCCR_TSEC1CM_SHIFT 30 7129e896478SKim Phillips #define SCCR_TSEC1CM_0 0x00000000 713d87c57b2SScott Wood #define SCCR_TSEC1CM_1 0x40000000 714d87c57b2SScott Wood #define SCCR_TSEC1CM_2 0x80000000 715d87c57b2SScott Wood #define SCCR_TSEC1CM_3 0xC0000000 716d87c57b2SScott Wood 717d87c57b2SScott Wood #define SCCR_TSEC1ON 0x20000000 718df33f6b4STimur Tabi #define SCCR_TSEC1ON_SHIFT 29 719d87c57b2SScott Wood #define SCCR_TSEC2ON 0x10000000 720df33f6b4STimur Tabi #define SCCR_TSEC2ON_SHIFT 28 721d87c57b2SScott Wood 722e080313cSDave Liu #define SCCR_USBDRCM 0x00300000 723e080313cSDave Liu #define SCCR_USBDRCM_SHIFT 20 72403051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 72503051c3dSDave Liu #define SCCR_USBDRCM_1 0x00100000 72603051c3dSDave Liu #define SCCR_USBDRCM_2 0x00200000 72703051c3dSDave Liu #define SCCR_USBDRCM_3 0x00300000 728e080313cSDave Liu 729555da617SDave Liu #elif defined(CONFIG_MPC8315) 730555da617SDave Liu /* SCCR bits - MPC8315 specific */ 731555da617SDave Liu #define SCCR_TSEC1CM 0xc0000000 732555da617SDave Liu #define SCCR_TSEC1CM_SHIFT 30 733555da617SDave Liu #define SCCR_TSEC1CM_0 0x00000000 734555da617SDave Liu #define SCCR_TSEC1CM_1 0x40000000 735555da617SDave Liu #define SCCR_TSEC1CM_2 0x80000000 736555da617SDave Liu #define SCCR_TSEC1CM_3 0xC0000000 737555da617SDave Liu 738555da617SDave Liu #define SCCR_TSEC2CM 0x30000000 739555da617SDave Liu #define SCCR_TSEC2CM_SHIFT 28 740555da617SDave Liu #define SCCR_TSEC2CM_0 0x00000000 741555da617SDave Liu #define SCCR_TSEC2CM_1 0x10000000 742555da617SDave Liu #define SCCR_TSEC2CM_2 0x20000000 743555da617SDave Liu #define SCCR_TSEC2CM_3 0x30000000 744555da617SDave Liu 7456f3931a2SDave Liu #define SCCR_USBDRCM 0x00c00000 7466f3931a2SDave Liu #define SCCR_USBDRCM_SHIFT 22 747555da617SDave Liu #define SCCR_USBDRCM_0 0x00000000 7486f3931a2SDave Liu #define SCCR_USBDRCM_1 0x00400000 7496f3931a2SDave Liu #define SCCR_USBDRCM_2 0x00800000 7506f3931a2SDave Liu #define SCCR_USBDRCM_3 0x00c00000 751555da617SDave Liu 7526f3931a2SDave Liu #define SCCR_PCIEXP1CM 0x00300000 7536f3931a2SDave Liu #define SCCR_PCIEXP2CM 0x000c0000 754555da617SDave Liu 7556f3931a2SDave Liu #define SCCR_SATA1CM 0x00003000 7566f3931a2SDave Liu #define SCCR_SATA1CM_SHIFT 12 7576f3931a2SDave Liu #define SCCR_SATACM 0x00003c00 7586f3931a2SDave Liu #define SCCR_SATACM_SHIFT 10 759555da617SDave Liu #define SCCR_SATACM_0 0x00000000 7606f3931a2SDave Liu #define SCCR_SATACM_1 0x00001400 7616f3931a2SDave Liu #define SCCR_SATACM_2 0x00002800 7626f3931a2SDave Liu #define SCCR_SATACM_3 0x00003c00 763555da617SDave Liu 7646f3931a2SDave Liu #define SCCR_TDMCM 0x00000030 7656f3931a2SDave Liu #define SCCR_TDMCM_SHIFT 4 766555da617SDave Liu #define SCCR_TDMCM_0 0x00000000 7676f3931a2SDave Liu #define SCCR_TDMCM_1 0x00000010 7686f3931a2SDave Liu #define SCCR_TDMCM_2 0x00000020 7696f3931a2SDave Liu #define SCCR_TDMCM_3 0x00000030 770555da617SDave Liu 77103051c3dSDave Liu #elif defined(CONFIG_MPC837X) 77203051c3dSDave Liu /* SCCR bits - MPC837x specific */ 77303051c3dSDave Liu #define SCCR_TSEC1CM 0xc0000000 77403051c3dSDave Liu #define SCCR_TSEC1CM_SHIFT 30 77503051c3dSDave Liu #define SCCR_TSEC1CM_0 0x00000000 77603051c3dSDave Liu #define SCCR_TSEC1CM_1 0x40000000 77703051c3dSDave Liu #define SCCR_TSEC1CM_2 0x80000000 77803051c3dSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 77903051c3dSDave Liu 78003051c3dSDave Liu #define SCCR_TSEC2CM 0x30000000 78103051c3dSDave Liu #define SCCR_TSEC2CM_SHIFT 28 78203051c3dSDave Liu #define SCCR_TSEC2CM_0 0x00000000 78303051c3dSDave Liu #define SCCR_TSEC2CM_1 0x10000000 78403051c3dSDave Liu #define SCCR_TSEC2CM_2 0x20000000 78503051c3dSDave Liu #define SCCR_TSEC2CM_3 0x30000000 78603051c3dSDave Liu 78703051c3dSDave Liu #define SCCR_SDHCCM 0x0c000000 78803051c3dSDave Liu #define SCCR_SDHCCM_SHIFT 26 78903051c3dSDave Liu #define SCCR_SDHCCM_0 0x00000000 79003051c3dSDave Liu #define SCCR_SDHCCM_1 0x04000000 79103051c3dSDave Liu #define SCCR_SDHCCM_2 0x08000000 79203051c3dSDave Liu #define SCCR_SDHCCM_3 0x0c000000 79303051c3dSDave Liu 79403051c3dSDave Liu #define SCCR_USBDRCM 0x00c00000 79503051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 22 79603051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 79703051c3dSDave Liu #define SCCR_USBDRCM_1 0x00400000 79803051c3dSDave Liu #define SCCR_USBDRCM_2 0x00800000 79903051c3dSDave Liu #define SCCR_USBDRCM_3 0x00c00000 80003051c3dSDave Liu 80103051c3dSDave Liu #define SCCR_PCIEXP1CM 0x00300000 80203051c3dSDave Liu #define SCCR_PCIEXP1CM_SHIFT 20 80303051c3dSDave Liu #define SCCR_PCIEXP1CM_0 0x00000000 80403051c3dSDave Liu #define SCCR_PCIEXP1CM_1 0x00100000 80503051c3dSDave Liu #define SCCR_PCIEXP1CM_2 0x00200000 80603051c3dSDave Liu #define SCCR_PCIEXP1CM_3 0x00300000 80703051c3dSDave Liu 80803051c3dSDave Liu #define SCCR_PCIEXP2CM 0x000c0000 80903051c3dSDave Liu #define SCCR_PCIEXP2CM_SHIFT 18 81003051c3dSDave Liu #define SCCR_PCIEXP2CM_0 0x00000000 81103051c3dSDave Liu #define SCCR_PCIEXP2CM_1 0x00040000 81203051c3dSDave Liu #define SCCR_PCIEXP2CM_2 0x00080000 81303051c3dSDave Liu #define SCCR_PCIEXP2CM_3 0x000c0000 81403051c3dSDave Liu 81503051c3dSDave Liu /* All of the four SATA controllers must have the same clock ratio */ 816a8cb43a8SDave Liu #define SCCR_SATA1CM 0x000000c0 817a8cb43a8SDave Liu #define SCCR_SATA1CM_SHIFT 6 81803051c3dSDave Liu #define SCCR_SATACM 0x000000ff 81903051c3dSDave Liu #define SCCR_SATACM_SHIFT 0 82003051c3dSDave Liu #define SCCR_SATACM_0 0x00000000 82103051c3dSDave Liu #define SCCR_SATACM_1 0x00000055 82203051c3dSDave Liu #define SCCR_SATACM_2 0x000000aa 82303051c3dSDave Liu #define SCCR_SATACM_3 0x000000ff 82403051c3dSDave Liu #endif 825e080313cSDave Liu 826e080313cSDave Liu /* CSn_BDNS - Chip Select memory Bounds Register 827e080313cSDave Liu */ 828e080313cSDave Liu #define CSBNDS_SA 0x00FF0000 829e080313cSDave Liu #define CSBNDS_SA_SHIFT 8 830e080313cSDave Liu #define CSBNDS_EA 0x000000FF 831e080313cSDave Liu #define CSBNDS_EA_SHIFT 24 832e080313cSDave Liu 833e080313cSDave Liu /* CSn_CONFIG - Chip Select Configuration Register 834e080313cSDave Liu */ 835e080313cSDave Liu #define CSCONFIG_EN 0x80000000 836e080313cSDave Liu #define CSCONFIG_AP 0x00800000 8379e896478SKim Phillips #define CSCONFIG_ODT_WR_ACS 0x00010000 838d82b4fc0STor Krill #define CSCONFIG_BANK_BIT_3 0x00004000 839e080313cSDave Liu #define CSCONFIG_ROW_BIT 0x00000700 840e080313cSDave Liu #define CSCONFIG_ROW_BIT_12 0x00000000 841e080313cSDave Liu #define CSCONFIG_ROW_BIT_13 0x00000100 842e080313cSDave Liu #define CSCONFIG_ROW_BIT_14 0x00000200 843e080313cSDave Liu #define CSCONFIG_COL_BIT 0x00000007 844e080313cSDave Liu #define CSCONFIG_COL_BIT_8 0x00000000 845e080313cSDave Liu #define CSCONFIG_COL_BIT_9 0x00000001 846e080313cSDave Liu #define CSCONFIG_COL_BIT_10 0x00000002 847e080313cSDave Liu #define CSCONFIG_COL_BIT_11 0x00000003 848e080313cSDave Liu 849d87c57b2SScott Wood /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 850d87c57b2SScott Wood */ 851d87c57b2SScott Wood #define TIMING_CFG0_RWT 0xC0000000 852d87c57b2SScott Wood #define TIMING_CFG0_RWT_SHIFT 30 853d87c57b2SScott Wood #define TIMING_CFG0_WRT 0x30000000 854d87c57b2SScott Wood #define TIMING_CFG0_WRT_SHIFT 28 855d87c57b2SScott Wood #define TIMING_CFG0_RRT 0x0C000000 856d87c57b2SScott Wood #define TIMING_CFG0_RRT_SHIFT 26 857d87c57b2SScott Wood #define TIMING_CFG0_WWT 0x03000000 858d87c57b2SScott Wood #define TIMING_CFG0_WWT_SHIFT 24 859d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 860d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 861d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 862d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 863d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 864d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 865d892b2dbSAnton Vorontsov #define TIMING_CFG0_MRS_CYC 0x0000000F 866d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC_SHIFT 0 867d87c57b2SScott Wood 868e080313cSDave Liu /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 869e080313cSDave Liu */ 870e080313cSDave Liu #define TIMING_CFG1_PRETOACT 0x70000000 871e080313cSDave Liu #define TIMING_CFG1_PRETOACT_SHIFT 28 872e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE 0x0F000000 873e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE_SHIFT 24 874e080313cSDave Liu #define TIMING_CFG1_ACTTORW 0x00700000 875e080313cSDave Liu #define TIMING_CFG1_ACTTORW_SHIFT 20 876e080313cSDave Liu #define TIMING_CFG1_CASLAT 0x00070000 877e080313cSDave Liu #define TIMING_CFG1_CASLAT_SHIFT 16 878e080313cSDave Liu #define TIMING_CFG1_REFREC 0x0000F000 879e080313cSDave Liu #define TIMING_CFG1_REFREC_SHIFT 12 880e080313cSDave Liu #define TIMING_CFG1_WRREC 0x00000700 881e080313cSDave Liu #define TIMING_CFG1_WRREC_SHIFT 8 882e080313cSDave Liu #define TIMING_CFG1_ACTTOACT 0x00000070 883e080313cSDave Liu #define TIMING_CFG1_ACTTOACT_SHIFT 4 884e080313cSDave Liu #define TIMING_CFG1_WRTORD 0x00000007 885e080313cSDave Liu #define TIMING_CFG1_WRTORD_SHIFT 0 886e080313cSDave Liu #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 887e080313cSDave Liu #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 888d892b2dbSAnton Vorontsov #define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 2.5 */ 889e080313cSDave Liu 890e080313cSDave Liu /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 891e080313cSDave Liu */ 8928d172c0fSXie Xiaobo #define TIMING_CFG2_CPO 0x0F800000 8938d172c0fSXie Xiaobo #define TIMING_CFG2_CPO_SHIFT 23 894e080313cSDave Liu #define TIMING_CFG2_ACSM 0x00080000 895e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 896e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 897e080313cSDave Liu #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 898e080313cSDave Liu 899d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT 0x70000000 900d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT_SHIFT 28 901d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 902d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 903d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE 0x0000E000 904d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 905d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS 0x000001C0 906d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS_SHIFT 6 907d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT 0x0000003F 908d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT_SHIFT 0 909d87c57b2SScott Wood 910e080313cSDave Liu /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 911e080313cSDave Liu */ 912e080313cSDave Liu #define SDRAM_CFG_MEM_EN 0x80000000 913e080313cSDave Liu #define SDRAM_CFG_SREN 0x40000000 914e080313cSDave Liu #define SDRAM_CFG_ECC_EN 0x20000000 915e080313cSDave Liu #define SDRAM_CFG_RD_EN 0x10000000 916bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 917bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 918bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 919e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 920e080313cSDave Liu #define SDRAM_CFG_DYN_PWR 0x00200000 921e080313cSDave Liu #define SDRAM_CFG_32_BE 0x00080000 922e080313cSDave Liu #define SDRAM_CFG_8_BE 0x00040000 923e080313cSDave Liu #define SDRAM_CFG_NCAP 0x00020000 924e080313cSDave Liu #define SDRAM_CFG_2T_EN 0x00008000 925d87c57b2SScott Wood #define SDRAM_CFG_BI 0x00000001 926e080313cSDave Liu 927e080313cSDave Liu /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 928e080313cSDave Liu */ 929e080313cSDave Liu #define SDRAM_MODE_ESD 0xFFFF0000 930e080313cSDave Liu #define SDRAM_MODE_ESD_SHIFT 16 931e080313cSDave Liu #define SDRAM_MODE_SD 0x0000FFFF 932e080313cSDave Liu #define SDRAM_MODE_SD_SHIFT 0 933e080313cSDave Liu #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 934e080313cSDave Liu #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 935e080313cSDave Liu #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 936e080313cSDave Liu #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 937e080313cSDave Liu #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 938e080313cSDave Liu #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 939e080313cSDave Liu #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 940e080313cSDave Liu #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 941e080313cSDave Liu #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 942e080313cSDave Liu #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 943e080313cSDave Liu #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 944e080313cSDave Liu #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 945e080313cSDave Liu #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 946e080313cSDave Liu #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 947e080313cSDave Liu #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 948e080313cSDave Liu #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 949e080313cSDave Liu #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 950e080313cSDave Liu #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 951e080313cSDave Liu #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 952e080313cSDave Liu 953e080313cSDave Liu /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 954e080313cSDave Liu */ 955e080313cSDave Liu #define SDRAM_INTERVAL_REFINT 0x3FFF0000 956e080313cSDave Liu #define SDRAM_INTERVAL_REFINT_SHIFT 16 957e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 958e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 959e080313cSDave Liu 960e080313cSDave Liu /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 961e080313cSDave Liu */ 962e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 963e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 964e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 965e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 966e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 967e080313cSDave Liu 968e080313cSDave Liu /* ECC_ERR_INJECT - Memory data path error injection mask ECC 969e080313cSDave Liu */ 970e080313cSDave Liu #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 971e080313cSDave Liu #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 972e080313cSDave Liu #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 973e080313cSDave Liu #define ECC_ERR_INJECT_EEIM_SHIFT 0 974e080313cSDave Liu 975e080313cSDave Liu /* CAPTURE_ECC - Memory data path read capture ECC 976e080313cSDave Liu */ 977e080313cSDave Liu #define CAPTURE_ECC_ECE (0xff000000>>24) 978e080313cSDave Liu #define CAPTURE_ECC_ECE_SHIFT 0 979e080313cSDave Liu 980e080313cSDave Liu /* ERR_DETECT - Memory error detect 981e080313cSDave Liu */ 982e080313cSDave Liu #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 983e080313cSDave Liu #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 984e080313cSDave Liu #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 985e080313cSDave Liu #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 986e080313cSDave Liu 987e080313cSDave Liu /* ERR_DISABLE - Memory error disable 988e080313cSDave Liu */ 989e080313cSDave Liu #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 990e080313cSDave Liu #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 991e080313cSDave Liu #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 992e080313cSDave Liu #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 993e080313cSDave Liu ECC_ERROR_DISABLE_MBED) 994e080313cSDave Liu /* ERR_INT_EN - Memory error interrupt enable 995e080313cSDave Liu */ 996e080313cSDave Liu #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 997e080313cSDave Liu #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 998e080313cSDave Liu #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 999e080313cSDave Liu #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 1000e080313cSDave Liu ECC_ERR_INT_EN_MSEE) 1001e080313cSDave Liu /* CAPTURE_ATTRIBUTES - Memory error attributes capture 1002e080313cSDave Liu */ 1003e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 1004e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM_SHIFT 28 1005e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 1006e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 1007e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 1008e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 1009e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 1010e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 1011e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 1012e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 1013e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 1014e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 1015e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 1016e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 1017e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 1018e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_I2C 0x9 1019e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 1020e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 1021e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 1022e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_DMA 0xF 1023e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_SHIFT 16 1024e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 1025e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 1026e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_READ 0x2 1027e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 1028e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_SHIFT 12 1029e080313cSDave Liu #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 1030e080313cSDave Liu 1031e080313cSDave Liu /* ERR_SBE - Single bit ECC memory error management 1032e080313cSDave Liu */ 1033e080313cSDave Liu #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 1034e080313cSDave Liu #define ECC_ERROR_MAN_SBET_SHIFT 16 1035e080313cSDave Liu #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 1036e080313cSDave Liu #define ECC_ERROR_MAN_SBEC_SHIFT 0 1037e080313cSDave Liu 1038e080313cSDave Liu /* DMAMR - DMA Mode Register 1039f6eda7f8SDave Liu */ 1040e080313cSDave Liu #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 1041e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 1042e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 1043e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 1044e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 1045e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 1046e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 1047e080313cSDave Liu #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 1048f6eda7f8SDave Liu 1049e080313cSDave Liu /* DMASR - DMA Status Register 1050e080313cSDave Liu */ 1051e080313cSDave Liu #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 1052e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 10535f820439SDave Liu 1054e080313cSDave Liu /* CONFIG_ADDRESS - PCI Config Address Register 1055e080313cSDave Liu */ 1056e080313cSDave Liu #define PCI_CONFIG_ADDRESS_EN 0x80000000 1057e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1058e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1059e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1060e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1061e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1062e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1063e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1064e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1065e080313cSDave Liu 1066e080313cSDave Liu /* POTAR - PCI Outbound Translation Address Register 1067e080313cSDave Liu */ 1068e080313cSDave Liu #define POTAR_TA_MASK 0x000fffff 1069e080313cSDave Liu 1070e080313cSDave Liu /* POBAR - PCI Outbound Base Address Register 1071e080313cSDave Liu */ 1072e080313cSDave Liu #define POBAR_BA_MASK 0x000fffff 1073e080313cSDave Liu 1074e080313cSDave Liu /* POCMR - PCI Outbound Comparision Mask Register 1075e080313cSDave Liu */ 1076e080313cSDave Liu #define POCMR_EN 0x80000000 1077e080313cSDave Liu #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1078e080313cSDave Liu #define POCMR_SE 0x20000000 /* streaming enable */ 1079e080313cSDave Liu #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1080e080313cSDave Liu #define POCMR_CM_MASK 0x000fffff 1081e080313cSDave Liu #define POCMR_CM_4G 0x00000000 1082e080313cSDave Liu #define POCMR_CM_2G 0x00080000 1083e080313cSDave Liu #define POCMR_CM_1G 0x000C0000 1084e080313cSDave Liu #define POCMR_CM_512M 0x000E0000 1085e080313cSDave Liu #define POCMR_CM_256M 0x000F0000 1086e080313cSDave Liu #define POCMR_CM_128M 0x000F8000 1087e080313cSDave Liu #define POCMR_CM_64M 0x000FC000 1088e080313cSDave Liu #define POCMR_CM_32M 0x000FE000 1089e080313cSDave Liu #define POCMR_CM_16M 0x000FF000 1090e080313cSDave Liu #define POCMR_CM_8M 0x000FF800 1091e080313cSDave Liu #define POCMR_CM_4M 0x000FFC00 1092e080313cSDave Liu #define POCMR_CM_2M 0x000FFE00 1093e080313cSDave Liu #define POCMR_CM_1M 0x000FFF00 1094e080313cSDave Liu #define POCMR_CM_512K 0x000FFF80 1095e080313cSDave Liu #define POCMR_CM_256K 0x000FFFC0 1096e080313cSDave Liu #define POCMR_CM_128K 0x000FFFE0 1097e080313cSDave Liu #define POCMR_CM_64K 0x000FFFF0 1098e080313cSDave Liu #define POCMR_CM_32K 0x000FFFF8 1099e080313cSDave Liu #define POCMR_CM_16K 0x000FFFFC 1100e080313cSDave Liu #define POCMR_CM_8K 0x000FFFFE 1101e080313cSDave Liu #define POCMR_CM_4K 0x000FFFFF 1102e080313cSDave Liu 1103e080313cSDave Liu /* PITAR - PCI Inbound Translation Address Register 1104e080313cSDave Liu */ 1105e080313cSDave Liu #define PITAR_TA_MASK 0x000fffff 1106e080313cSDave Liu 1107e080313cSDave Liu /* PIBAR - PCI Inbound Base/Extended Address Register 1108e080313cSDave Liu */ 1109e080313cSDave Liu #define PIBAR_MASK 0xffffffff 1110e080313cSDave Liu #define PIEBAR_EBA_MASK 0x000fffff 1111e080313cSDave Liu 1112e080313cSDave Liu /* PIWAR - PCI Inbound Windows Attributes Register 1113e080313cSDave Liu */ 1114e080313cSDave Liu #define PIWAR_EN 0x80000000 1115e080313cSDave Liu #define PIWAR_PF 0x20000000 1116e080313cSDave Liu #define PIWAR_RTT_MASK 0x000f0000 1117e080313cSDave Liu #define PIWAR_RTT_NO_SNOOP 0x00040000 1118e080313cSDave Liu #define PIWAR_RTT_SNOOP 0x00050000 1119e080313cSDave Liu #define PIWAR_WTT_MASK 0x0000f000 1120e080313cSDave Liu #define PIWAR_WTT_NO_SNOOP 0x00004000 1121e080313cSDave Liu #define PIWAR_WTT_SNOOP 0x00005000 1122e080313cSDave Liu #define PIWAR_IWS_MASK 0x0000003F 1123e080313cSDave Liu #define PIWAR_IWS_4K 0x0000000B 1124e080313cSDave Liu #define PIWAR_IWS_8K 0x0000000C 1125e080313cSDave Liu #define PIWAR_IWS_16K 0x0000000D 1126e080313cSDave Liu #define PIWAR_IWS_32K 0x0000000E 1127e080313cSDave Liu #define PIWAR_IWS_64K 0x0000000F 1128e080313cSDave Liu #define PIWAR_IWS_128K 0x00000010 1129e080313cSDave Liu #define PIWAR_IWS_256K 0x00000011 1130e080313cSDave Liu #define PIWAR_IWS_512K 0x00000012 1131e080313cSDave Liu #define PIWAR_IWS_1M 0x00000013 1132e080313cSDave Liu #define PIWAR_IWS_2M 0x00000014 1133e080313cSDave Liu #define PIWAR_IWS_4M 0x00000015 1134e080313cSDave Liu #define PIWAR_IWS_8M 0x00000016 1135e080313cSDave Liu #define PIWAR_IWS_16M 0x00000017 1136e080313cSDave Liu #define PIWAR_IWS_32M 0x00000018 1137e080313cSDave Liu #define PIWAR_IWS_64M 0x00000019 1138e080313cSDave Liu #define PIWAR_IWS_128M 0x0000001A 1139e080313cSDave Liu #define PIWAR_IWS_256M 0x0000001B 1140e080313cSDave Liu #define PIWAR_IWS_512M 0x0000001C 1141e080313cSDave Liu #define PIWAR_IWS_1G 0x0000001D 1142e080313cSDave Liu #define PIWAR_IWS_2G 0x0000001E 1143f6eda7f8SDave Liu 1144d87c57b2SScott Wood /* PMCCR1 - PCI Configuration Register 1 1145d87c57b2SScott Wood */ 1146d87c57b2SScott Wood #define PMCCR1_POWER_OFF 0x00000020 1147d87c57b2SScott Wood 1148d87c57b2SScott Wood /* FMR - Flash Mode Register 1149d87c57b2SScott Wood */ 1150d87c57b2SScott Wood #define FMR_CWTO 0x0000F000 1151d87c57b2SScott Wood #define FMR_CWTO_SHIFT 12 1152d87c57b2SScott Wood #define FMR_BOOT 0x00000800 1153d87c57b2SScott Wood #define FMR_ECCM 0x00000100 1154d87c57b2SScott Wood #define FMR_AL 0x00000030 1155d87c57b2SScott Wood #define FMR_AL_SHIFT 4 1156d87c57b2SScott Wood #define FMR_OP 0x00000003 1157d87c57b2SScott Wood #define FMR_OP_SHIFT 0 1158d87c57b2SScott Wood 1159d87c57b2SScott Wood /* FIR - Flash Instruction Register 1160d87c57b2SScott Wood */ 1161d87c57b2SScott Wood #define FIR_OP0 0xF0000000 1162d87c57b2SScott Wood #define FIR_OP0_SHIFT 28 1163d87c57b2SScott Wood #define FIR_OP1 0x0F000000 1164d87c57b2SScott Wood #define FIR_OP1_SHIFT 24 1165d87c57b2SScott Wood #define FIR_OP2 0x00F00000 1166d87c57b2SScott Wood #define FIR_OP2_SHIFT 20 1167d87c57b2SScott Wood #define FIR_OP3 0x000F0000 1168d87c57b2SScott Wood #define FIR_OP3_SHIFT 16 1169d87c57b2SScott Wood #define FIR_OP4 0x0000F000 1170d87c57b2SScott Wood #define FIR_OP4_SHIFT 12 1171d87c57b2SScott Wood #define FIR_OP5 0x00000F00 1172d87c57b2SScott Wood #define FIR_OP5_SHIFT 8 1173d87c57b2SScott Wood #define FIR_OP6 0x000000F0 1174d87c57b2SScott Wood #define FIR_OP6_SHIFT 4 1175d87c57b2SScott Wood #define FIR_OP7 0x0000000F 1176d87c57b2SScott Wood #define FIR_OP7_SHIFT 0 1177d87c57b2SScott Wood #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 1178d87c57b2SScott Wood #define FIR_OP_CA 0x1 /* Issue current column address */ 1179d87c57b2SScott Wood #define FIR_OP_PA 0x2 /* Issue current block+page address */ 1180d87c57b2SScott Wood #define FIR_OP_UA 0x3 /* Issue user defined address */ 1181d87c57b2SScott Wood #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 1182d87c57b2SScott Wood #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 1183d87c57b2SScott Wood #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 1184d87c57b2SScott Wood #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 1185d87c57b2SScott Wood #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 1186d87c57b2SScott Wood #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 1187d87c57b2SScott Wood #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 1188d87c57b2SScott Wood #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 1189d87c57b2SScott Wood #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 1190d87c57b2SScott Wood #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 1191d87c57b2SScott Wood #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 1192d87c57b2SScott Wood #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 1193d87c57b2SScott Wood 1194d87c57b2SScott Wood /* FCR - Flash Command Register 1195d87c57b2SScott Wood */ 1196d87c57b2SScott Wood #define FCR_CMD0 0xFF000000 1197d87c57b2SScott Wood #define FCR_CMD0_SHIFT 24 1198d87c57b2SScott Wood #define FCR_CMD1 0x00FF0000 1199d87c57b2SScott Wood #define FCR_CMD1_SHIFT 16 1200d87c57b2SScott Wood #define FCR_CMD2 0x0000FF00 1201d87c57b2SScott Wood #define FCR_CMD2_SHIFT 8 1202d87c57b2SScott Wood #define FCR_CMD3 0x000000FF 1203d87c57b2SScott Wood #define FCR_CMD3_SHIFT 0 1204d87c57b2SScott Wood 1205d87c57b2SScott Wood /* FBAR - Flash Block Address Register 1206d87c57b2SScott Wood */ 1207d87c57b2SScott Wood #define FBAR_BLK 0x00FFFFFF 1208d87c57b2SScott Wood 1209d87c57b2SScott Wood /* FPAR - Flash Page Address Register 1210d87c57b2SScott Wood */ 1211d87c57b2SScott Wood #define FPAR_SP_PI 0x00007C00 1212d87c57b2SScott Wood #define FPAR_SP_PI_SHIFT 10 1213d87c57b2SScott Wood #define FPAR_SP_MS 0x00000200 1214d87c57b2SScott Wood #define FPAR_SP_CI 0x000001FF 1215d87c57b2SScott Wood #define FPAR_SP_CI_SHIFT 0 1216d87c57b2SScott Wood #define FPAR_LP_PI 0x0003F000 1217d87c57b2SScott Wood #define FPAR_LP_PI_SHIFT 12 1218d87c57b2SScott Wood #define FPAR_LP_MS 0x00000800 1219d87c57b2SScott Wood #define FPAR_LP_CI 0x000007FF 1220d87c57b2SScott Wood #define FPAR_LP_CI_SHIFT 0 1221d87c57b2SScott Wood 1222d87c57b2SScott Wood /* LTESR - Transfer Error Status Register 1223d87c57b2SScott Wood */ 1224d87c57b2SScott Wood #define LTESR_BM 0x80000000 1225d87c57b2SScott Wood #define LTESR_FCT 0x40000000 1226d87c57b2SScott Wood #define LTESR_PAR 0x20000000 1227d87c57b2SScott Wood #define LTESR_WP 0x04000000 1228d87c57b2SScott Wood #define LTESR_ATMW 0x00800000 1229d87c57b2SScott Wood #define LTESR_ATMR 0x00400000 1230d87c57b2SScott Wood #define LTESR_CS 0x00080000 1231d87c57b2SScott Wood #define LTESR_CC 0x00000001 1232d87c57b2SScott Wood 123303051c3dSDave Liu /* DDRCDR - DDR Control Driver Register 1234d87c57b2SScott Wood */ 12359e896478SKim Phillips #define DDRCDR_DHC_EN 0x80000000 1236d87c57b2SScott Wood #define DDRCDR_EN 0x40000000 1237d87c57b2SScott Wood #define DDRCDR_PZ 0x3C000000 1238d87c57b2SScott Wood #define DDRCDR_PZ_MAXZ 0x00000000 1239d87c57b2SScott Wood #define DDRCDR_PZ_HIZ 0x20000000 1240d87c57b2SScott Wood #define DDRCDR_PZ_NOMZ 0x30000000 1241d87c57b2SScott Wood #define DDRCDR_PZ_LOZ 0x38000000 1242d87c57b2SScott Wood #define DDRCDR_PZ_MINZ 0x3C000000 1243d87c57b2SScott Wood #define DDRCDR_NZ 0x3C000000 1244d87c57b2SScott Wood #define DDRCDR_NZ_MAXZ 0x00000000 1245d87c57b2SScott Wood #define DDRCDR_NZ_HIZ 0x02000000 1246d87c57b2SScott Wood #define DDRCDR_NZ_NOMZ 0x03000000 1247d87c57b2SScott Wood #define DDRCDR_NZ_LOZ 0x03800000 1248d87c57b2SScott Wood #define DDRCDR_NZ_MINZ 0x03C00000 1249d87c57b2SScott Wood #define DDRCDR_ODT 0x00080000 1250d87c57b2SScott Wood #define DDRCDR_DDR_CFG 0x00040000 1251d87c57b2SScott Wood #define DDRCDR_M_ODR 0x00000002 1252d87c57b2SScott Wood #define DDRCDR_Q_DRN 0x00000001 1253d87c57b2SScott Wood 125449ea3b6eSScott Wood #ifndef __ASSEMBLY__ 125549ea3b6eSScott Wood struct pci_region; 125649ea3b6eSScott Wood void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 125749ea3b6eSScott Wood #endif 125849ea3b6eSScott Wood 1259f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 1260