1f046ccd1SEran Liberty /* 2*03051c3dSDave Liu * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty */ 12f046ccd1SEran Liberty 13f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 14f046ccd1SEran Liberty #define __MPC83XX_H__ 15f046ccd1SEran Liberty 16f6eda7f8SDave Liu #include <config.h> 17f046ccd1SEran Liberty #if defined(CONFIG_E300) 18f046ccd1SEran Liberty #include <asm/e300.h> 19f046ccd1SEran Liberty #endif 20f046ccd1SEran Liberty 21e080313cSDave Liu /* MPC83xx cpu provide RCR register to do reset thing specially 22f046ccd1SEran Liberty */ 23f046ccd1SEran Liberty #define MPC83xx_RESET 24f046ccd1SEran Liberty 25e080313cSDave Liu /* System reset offset (PowerPC standard) 26f046ccd1SEran Liberty */ 27f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 2802032e8fSRafal Jaworowski #define _START_OFFSET EXC_OFF_SYS_RESET 29f046ccd1SEran Liberty 30e080313cSDave Liu /* IMMRBAR - Internal Memory Register Base Address 31f046ccd1SEran Liberty */ 32e080313cSDave Liu #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 33e080313cSDave Liu #define IMMRBAR 0x0000 /* Register offset to immr */ 34e080313cSDave Liu #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 35f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 36f046ccd1SEran Liberty 37e080313cSDave Liu /* LAWBAR - Local Access Window Base Address Register 38f046ccd1SEran Liberty */ 39e080313cSDave Liu #define LBLAWBAR0 0x0020 /* Register offset to immr */ 40f046ccd1SEran Liberty #define LBLAWAR0 0x0024 41f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 42f046ccd1SEran Liberty #define LBLAWAR1 0x002C 43f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 44f046ccd1SEran Liberty #define LBLAWAR2 0x0034 45f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 46f046ccd1SEran Liberty #define LBLAWAR3 0x003C 47e080313cSDave Liu #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 48f046ccd1SEran Liberty 49e080313cSDave Liu /* SPRIDR - System Part and Revision ID Register 50f6eda7f8SDave Liu */ 51e080313cSDave Liu #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ 52e080313cSDave Liu #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ 53e080313cSDave Liu 54f6eda7f8SDave Liu #define SPR_8349E_REV10 0x80300100 555f820439SDave Liu #define SPR_8349_REV10 0x80310100 565f820439SDave Liu #define SPR_8347E_REV10_TBGA 0x80320100 575f820439SDave Liu #define SPR_8347_REV10_TBGA 0x80330100 585f820439SDave Liu #define SPR_8347E_REV10_PBGA 0x80340100 595f820439SDave Liu #define SPR_8347_REV10_PBGA 0x80350100 605f820439SDave Liu #define SPR_8343E_REV10 0x80360100 615f820439SDave Liu #define SPR_8343_REV10 0x80370100 625f820439SDave Liu 63f6eda7f8SDave Liu #define SPR_8349E_REV11 0x80300101 645f820439SDave Liu #define SPR_8349_REV11 0x80310101 655f820439SDave Liu #define SPR_8347E_REV11_TBGA 0x80320101 665f820439SDave Liu #define SPR_8347_REV11_TBGA 0x80330101 675f820439SDave Liu #define SPR_8347E_REV11_PBGA 0x80340101 685f820439SDave Liu #define SPR_8347_REV11_PBGA 0x80350101 695f820439SDave Liu #define SPR_8343E_REV11 0x80360101 705f820439SDave Liu #define SPR_8343_REV11 0x80370101 715f820439SDave Liu 728d172c0fSXie Xiaobo #define SPR_8349E_REV31 0x80300300 738d172c0fSXie Xiaobo #define SPR_8349_REV31 0x80310300 748d172c0fSXie Xiaobo #define SPR_8347E_REV31_TBGA 0x80320300 758d172c0fSXie Xiaobo #define SPR_8347_REV31_TBGA 0x80330300 768d172c0fSXie Xiaobo #define SPR_8347E_REV31_PBGA 0x80340300 778d172c0fSXie Xiaobo #define SPR_8347_REV31_PBGA 0x80350300 788d172c0fSXie Xiaobo #define SPR_8343E_REV31 0x80360300 798d172c0fSXie Xiaobo #define SPR_8343_REV31 0x80370300 808d172c0fSXie Xiaobo 815f820439SDave Liu #define SPR_8360E_REV10 0x80480010 825f820439SDave Liu #define SPR_8360_REV10 0x80490010 835f820439SDave Liu #define SPR_8360E_REV11 0x80480011 845f820439SDave Liu #define SPR_8360_REV11 0x80490011 855f820439SDave Liu #define SPR_8360E_REV12 0x80480012 865f820439SDave Liu #define SPR_8360_REV12 0x80490012 87b110f40bSXie Xiaobo #define SPR_8360E_REV20 0x80480020 88b110f40bSXie Xiaobo #define SPR_8360_REV20 0x80490020 891ded0242SLee Nipper #define SPR_8360E_REV21 0x80480021 901ded0242SLee Nipper #define SPR_8360_REV21 0x80490021 91f046ccd1SEran Liberty 9224c3aca3SDave Liu #define SPR_8323E_REV10 0x80620010 9324c3aca3SDave Liu #define SPR_8323_REV10 0x80630010 9424c3aca3SDave Liu #define SPR_8321E_REV10 0x80660010 9524c3aca3SDave Liu #define SPR_8321_REV10 0x80670010 9624c3aca3SDave Liu #define SPR_8323E_REV11 0x80620011 9724c3aca3SDave Liu #define SPR_8323_REV11 0x80630011 9824c3aca3SDave Liu #define SPR_8321E_REV11 0x80660011 9924c3aca3SDave Liu #define SPR_8321_REV11 0x80670011 10024c3aca3SDave Liu 101d87c57b2SScott Wood #define SPR_8313E_REV10 0x80B00010 102*03051c3dSDave Liu #define SPR_8313_REV10 0x80B10010 103*03051c3dSDave Liu #define SPR_8311E_REV10 0x80B20010 104*03051c3dSDave Liu #define SPR_8311_REV10 0x80B30010 105*03051c3dSDave Liu 106*03051c3dSDave Liu #define SPR_8379E_REV10 0x80C20010 107*03051c3dSDave Liu #define SPR_8379_REV10 0x80C30010 108*03051c3dSDave Liu #define SPR_8378E_REV10 0x80C40010 109*03051c3dSDave Liu #define SPR_8378_REV10 0x80C50010 110*03051c3dSDave Liu #define SPR_8377E_REV10 0x80C60010 111*03051c3dSDave Liu #define SPR_8377_REV10 0x80C70010 112d87c57b2SScott Wood 113e080313cSDave Liu /* SPCR - System Priority Configuration Register 114f046ccd1SEran Liberty */ 115e080313cSDave Liu #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 116e080313cSDave Liu #define SPCR_PCIHPE_SHIFT (31-3) 117e080313cSDave Liu #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 118e080313cSDave Liu #define SPCR_PCIPR_SHIFT (31-7) 119e080313cSDave Liu #define SPCR_OPT 0x00800000 /* Optimize */ 120e080313cSDave Liu #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 121e080313cSDave Liu #define SPCR_TBEN_SHIFT (31-9) 122e080313cSDave Liu #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 123e080313cSDave Liu #define SPCR_COREPR_SHIFT (31-11) 124e080313cSDave Liu 1253e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 126e080313cSDave Liu /* SPCR bits - MPC8349 specific */ 127e080313cSDave Liu #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 128e080313cSDave Liu #define SPCR_TSEC1DP_SHIFT (31-19) 129e080313cSDave Liu #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 130e080313cSDave Liu #define SPCR_TSEC1BDP_SHIFT (31-21) 131e080313cSDave Liu #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 132e080313cSDave Liu #define SPCR_TSEC1EP_SHIFT (31-23) 133e080313cSDave Liu #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 134e080313cSDave Liu #define SPCR_TSEC2DP_SHIFT (31-27) 135e080313cSDave Liu #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 136e080313cSDave Liu #define SPCR_TSEC2BDP_SHIFT (31-29) 137e080313cSDave Liu #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 138e080313cSDave Liu #define SPCR_TSEC2EP_SHIFT (31-31) 139d87c57b2SScott Wood 140*03051c3dSDave Liu #elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 141*03051c3dSDave Liu /* SPCR bits - MPC831x and MPC837x specific */ 142d87c57b2SScott Wood #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 143d87c57b2SScott Wood #define SPCR_TSECDP_SHIFT (31-19) 144d87c57b2SScott Wood #define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */ 145d87c57b2SScott Wood #define SPCR_TSECEP_SHIFT (31-21) 146d87c57b2SScott Wood #define SPCR_TSECBDP 0x00000300 /* TSEC buffer descriptor priority */ 147d87c57b2SScott Wood #define SPCR_TSECBDP_SHIFT (31-23) 148e080313cSDave Liu #endif 149e080313cSDave Liu 150e080313cSDave Liu /* SICRL/H - System I/O Configuration Register Low/High 151e080313cSDave Liu */ 1523e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 153e080313cSDave Liu /* SICRL bits - MPC8349 specific */ 154e080313cSDave Liu #define SICRL_LDP_A 0x80000000 155e080313cSDave Liu #define SICRL_USB1 0x40000000 156e080313cSDave Liu #define SICRL_USB0 0x20000000 157e080313cSDave Liu #define SICRL_UART 0x0C000000 158e080313cSDave Liu #define SICRL_GPIO1_A 0x02000000 159e080313cSDave Liu #define SICRL_GPIO1_B 0x01000000 160e080313cSDave Liu #define SICRL_GPIO1_C 0x00800000 161e080313cSDave Liu #define SICRL_GPIO1_D 0x00400000 162e080313cSDave Liu #define SICRL_GPIO1_E 0x00200000 163e080313cSDave Liu #define SICRL_GPIO1_F 0x00180000 164e080313cSDave Liu #define SICRL_GPIO1_G 0x00040000 165e080313cSDave Liu #define SICRL_GPIO1_H 0x00020000 166e080313cSDave Liu #define SICRL_GPIO1_I 0x00010000 167e080313cSDave Liu #define SICRL_GPIO1_J 0x00008000 168e080313cSDave Liu #define SICRL_GPIO1_K 0x00004000 169e080313cSDave Liu #define SICRL_GPIO1_L 0x00003000 170e080313cSDave Liu 171e080313cSDave Liu /* SICRH bits - MPC8349 specific */ 172e080313cSDave Liu #define SICRH_DDR 0x80000000 173e080313cSDave Liu #define SICRH_TSEC1_A 0x10000000 174e080313cSDave Liu #define SICRH_TSEC1_B 0x08000000 175e080313cSDave Liu #define SICRH_TSEC1_C 0x04000000 176e080313cSDave Liu #define SICRH_TSEC1_D 0x02000000 177e080313cSDave Liu #define SICRH_TSEC1_E 0x01000000 178e080313cSDave Liu #define SICRH_TSEC1_F 0x00800000 179e080313cSDave Liu #define SICRH_TSEC2_A 0x00400000 180e080313cSDave Liu #define SICRH_TSEC2_B 0x00200000 181e080313cSDave Liu #define SICRH_TSEC2_C 0x00100000 182e080313cSDave Liu #define SICRH_TSEC2_D 0x00080000 183e080313cSDave Liu #define SICRH_TSEC2_E 0x00040000 184e080313cSDave Liu #define SICRH_TSEC2_F 0x00020000 185e080313cSDave Liu #define SICRH_TSEC2_G 0x00010000 186e080313cSDave Liu #define SICRH_TSEC2_H 0x00008000 187e080313cSDave Liu #define SICRH_GPIO2_A 0x00004000 188e080313cSDave Liu #define SICRH_GPIO2_B 0x00002000 189e080313cSDave Liu #define SICRH_GPIO2_C 0x00001000 190e080313cSDave Liu #define SICRH_GPIO2_D 0x00000800 191e080313cSDave Liu #define SICRH_GPIO2_E 0x00000400 192e080313cSDave Liu #define SICRH_GPIO2_F 0x00000200 193e080313cSDave Liu #define SICRH_GPIO2_G 0x00000180 194e080313cSDave Liu #define SICRH_GPIO2_H 0x00000060 195e080313cSDave Liu #define SICRH_TSOBI1 0x00000002 196e080313cSDave Liu #define SICRH_TSOBI2 0x00000001 197e080313cSDave Liu 198e080313cSDave Liu #elif defined(CONFIG_MPC8360) 199e080313cSDave Liu /* SICRL bits - MPC8360 specific */ 200e080313cSDave Liu #define SICRL_LDP_A 0xC0000000 201e080313cSDave Liu #define SICRL_LCLK_1 0x10000000 202e080313cSDave Liu #define SICRL_LCLK_2 0x08000000 203e080313cSDave Liu #define SICRL_SRCID_A 0x03000000 204e080313cSDave Liu #define SICRL_IRQ_CKSTP_A 0x00C00000 205e080313cSDave Liu 206e080313cSDave Liu /* SICRH bits - MPC8360 specific */ 207e080313cSDave Liu #define SICRH_DDR 0x80000000 208e080313cSDave Liu #define SICRH_SECONDARY_DDR 0x40000000 209e080313cSDave Liu #define SICRH_SDDROE 0x20000000 210e080313cSDave Liu #define SICRH_IRQ3 0x10000000 211e080313cSDave Liu #define SICRH_UC1EOBI 0x00000004 212e080313cSDave Liu #define SICRH_UC2E1OBI 0x00000002 213e080313cSDave Liu #define SICRH_UC2E2OBI 0x00000001 21424c3aca3SDave Liu 21524c3aca3SDave Liu #elif defined(CONFIG_MPC832X) 21624c3aca3SDave Liu /* SICRL bits - MPC832X specific */ 21724c3aca3SDave Liu #define SICRL_LDP_LCS_A 0x80000000 21824c3aca3SDave Liu #define SICRL_IRQ_CKS 0x20000000 21924c3aca3SDave Liu #define SICRL_PCI_MSRC 0x10000000 22024c3aca3SDave Liu #define SICRL_URT_CTPR 0x06000000 22124c3aca3SDave Liu #define SICRL_IRQ_CTPR 0x00C00000 222d87c57b2SScott Wood 223d87c57b2SScott Wood #elif defined(CONFIG_MPC831X) 224d87c57b2SScott Wood /* SICRL bits - MPC831x specific */ 225d87c57b2SScott Wood #define SICRL_LBC 0x30000000 226d87c57b2SScott Wood #define SICRL_UART 0x0C000000 227d87c57b2SScott Wood #define SICRL_SPI_A 0x03000000 228d87c57b2SScott Wood #define SICRL_SPI_B 0x00C00000 229d87c57b2SScott Wood #define SICRL_SPI_C 0x00300000 230d87c57b2SScott Wood #define SICRL_SPI_D 0x000C0000 231d87c57b2SScott Wood #define SICRL_USBDR 0x00000C00 232d87c57b2SScott Wood #define SICRL_ETSEC1_A 0x0000000C 233d87c57b2SScott Wood #define SICRL_ETSEC2_A 0x00000003 234d87c57b2SScott Wood 235d87c57b2SScott Wood /* SICRH bits - MPC831x specific */ 236d87c57b2SScott Wood #define SICRH_INTR_A 0x02000000 237d87c57b2SScott Wood #define SICRH_INTR_B 0x00C00000 238d87c57b2SScott Wood #define SICRH_IIC 0x00300000 239d87c57b2SScott Wood #define SICRH_ETSEC2_B 0x000C0000 240d87c57b2SScott Wood #define SICRH_ETSEC2_C 0x00030000 241d87c57b2SScott Wood #define SICRH_ETSEC2_D 0x0000C000 242d87c57b2SScott Wood #define SICRH_ETSEC2_E 0x00003000 243d87c57b2SScott Wood #define SICRH_ETSEC2_F 0x00000C00 244d87c57b2SScott Wood #define SICRH_ETSEC2_G 0x00000300 245d87c57b2SScott Wood #define SICRH_ETSEC1_B 0x00000080 246d87c57b2SScott Wood #define SICRH_ETSEC1_C 0x00000060 247d87c57b2SScott Wood #define SICRH_GTX1_DLY 0x00000008 248d87c57b2SScott Wood #define SICRH_GTX2_DLY 0x00000004 249d87c57b2SScott Wood #define SICRH_TSOBI1 0x00000002 250d87c57b2SScott Wood #define SICRH_TSOBI2 0x00000001 251d87c57b2SScott Wood 252*03051c3dSDave Liu #elif defined(CONFIG_MPC837X) 253*03051c3dSDave Liu /* SICRL bits - MPC837x specific */ 254*03051c3dSDave Liu #define SICRL_USB_A 0xC0000000 255*03051c3dSDave Liu #define SICRL_USB_B 0x30000000 256*03051c3dSDave Liu #define SICRL_UART 0x0C000000 257*03051c3dSDave Liu #define SICRL_GPIO_A 0x02000000 258*03051c3dSDave Liu #define SICRL_GPIO_B 0x01000000 259*03051c3dSDave Liu #define SICRL_GPIO_C 0x00800000 260*03051c3dSDave Liu #define SICRL_GPIO_D 0x00400000 261*03051c3dSDave Liu #define SICRL_GPIO_E 0x00200000 262*03051c3dSDave Liu #define SICRL_GPIO_F 0x00180000 263*03051c3dSDave Liu #define SICRL_GPIO_G 0x00040000 264*03051c3dSDave Liu #define SICRL_GPIO_H 0x00020000 265*03051c3dSDave Liu #define SICRL_GPIO_I 0x00010000 266*03051c3dSDave Liu #define SICRL_GPIO_J 0x00008000 267*03051c3dSDave Liu #define SICRL_GPIO_K 0x00004000 268*03051c3dSDave Liu #define SICRL_GPIO_L 0x00003000 269*03051c3dSDave Liu #define SICRL_DMA_A 0x00000800 270*03051c3dSDave Liu #define SICRL_DMA_B 0x00000400 271*03051c3dSDave Liu #define SICRL_DMA_C 0x00000200 272*03051c3dSDave Liu #define SICRL_DMA_D 0x00000100 273*03051c3dSDave Liu #define SICRL_DMA_E 0x00000080 274*03051c3dSDave Liu #define SICRL_DMA_F 0x00000040 275*03051c3dSDave Liu #define SICRL_DMA_G 0x00000020 276*03051c3dSDave Liu #define SICRL_DMA_H 0x00000010 277*03051c3dSDave Liu #define SICRL_DMA_I 0x00000008 278*03051c3dSDave Liu #define SICRL_DMA_J 0x00000004 279*03051c3dSDave Liu #define SICRL_LDP_A 0x00000002 280*03051c3dSDave Liu #define SICRL_LDP_B 0x00000001 281*03051c3dSDave Liu 282*03051c3dSDave Liu /* SICRH bits - MPC837x specific */ 283*03051c3dSDave Liu #define SICRH_DDR 0x80000000 284*03051c3dSDave Liu #define SICRH_TSEC1_A 0x10000000 285*03051c3dSDave Liu #define SICRH_TSEC1_B 0x08000000 286*03051c3dSDave Liu #define SICRH_TSEC2_A 0x00400000 287*03051c3dSDave Liu #define SICRH_TSEC2_B 0x00200000 288*03051c3dSDave Liu #define SICRH_TSEC2_C 0x00100000 289*03051c3dSDave Liu #define SICRH_TSEC2_D 0x00080000 290*03051c3dSDave Liu #define SICRH_TSEC2_E 0x00040000 291*03051c3dSDave Liu #define SICRH_TMR 0x00010000 292*03051c3dSDave Liu #define SICRH_GPIO2_A 0x00008000 293*03051c3dSDave Liu #define SICRH_GPIO2_B 0x00004000 294*03051c3dSDave Liu #define SICRH_GPIO2_C 0x00002000 295*03051c3dSDave Liu #define SICRH_GPIO2_D 0x00001000 296*03051c3dSDave Liu #define SICRH_GPIO2_E 0x00000C00 297*03051c3dSDave Liu #define SICRH_GPIO2_F 0x00000300 298*03051c3dSDave Liu #define SICRH_GPIO2_G 0x000000C0 299*03051c3dSDave Liu #define SICRH_GPIO2_H 0x00000030 300*03051c3dSDave Liu #define SICRH_SPI 0x00000003 301e080313cSDave Liu #endif 302e080313cSDave Liu 303e080313cSDave Liu /* SWCRR - System Watchdog Control Register 304e080313cSDave Liu */ 305e080313cSDave Liu #define SWCRR 0x0204 /* Register offset to immr */ 306e080313cSDave Liu #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 307e080313cSDave Liu #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 308e080313cSDave Liu #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 309e080313cSDave Liu #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 310e080313cSDave Liu #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 311e080313cSDave Liu 312e080313cSDave Liu /* SWCNR - System Watchdog Counter Register 313e080313cSDave Liu */ 314e080313cSDave Liu #define SWCNR 0x0208 /* Register offset to immr */ 315e080313cSDave Liu #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 316e080313cSDave Liu #define SWCNR_RES ~(SWCNR_SWCN) 317e080313cSDave Liu 318e080313cSDave Liu /* SWSRR - System Watchdog Service Register 319e080313cSDave Liu */ 320e080313cSDave Liu #define SWSRR 0x020E /* Register offset to immr */ 321e080313cSDave Liu 322e080313cSDave Liu /* ACR - Arbiter Configuration Register 323e080313cSDave Liu */ 324e080313cSDave Liu #define ACR_COREDIS 0x10000000 /* Core disable */ 325e080313cSDave Liu #define ACR_COREDIS_SHIFT (31-7) 326e080313cSDave Liu #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 327e080313cSDave Liu #define ACR_PIPE_DEP_SHIFT (31-15) 328e080313cSDave Liu #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 329e080313cSDave Liu #define ACR_PCI_RPTCNT_SHIFT (31-19) 330e080313cSDave Liu #define ACR_RPTCNT 0x00000700 /* Repeat count */ 331e080313cSDave Liu #define ACR_RPTCNT_SHIFT (31-23) 332e080313cSDave Liu #define ACR_APARK 0x00000030 /* Address parking */ 333e080313cSDave Liu #define ACR_APARK_SHIFT (31-27) 334e080313cSDave Liu #define ACR_PARKM 0x0000000F /* Parking master */ 335e080313cSDave Liu #define ACR_PARKM_SHIFT (31-31) 336e080313cSDave Liu 337e080313cSDave Liu /* ATR - Arbiter Timers Register 338e080313cSDave Liu */ 339e080313cSDave Liu #define ATR_DTO 0x00FF0000 /* Data time out */ 340e080313cSDave Liu #define ATR_ATO 0x000000FF /* Address time out */ 341e080313cSDave Liu 342e080313cSDave Liu /* AER - Arbiter Event Register 343e080313cSDave Liu */ 344e080313cSDave Liu #define AER_ETEA 0x00000020 /* Transfer error */ 345e080313cSDave Liu #define AER_RES 0x00000010 /* Reserved transfer type */ 346e080313cSDave Liu #define AER_ECW 0x00000008 /* External control word transfer type */ 347e080313cSDave Liu #define AER_AO 0x00000004 /* Address Only transfer type */ 348e080313cSDave Liu #define AER_DTO 0x00000002 /* Data time out */ 349e080313cSDave Liu #define AER_ATO 0x00000001 /* Address time out */ 350e080313cSDave Liu 351e080313cSDave Liu /* AEATR - Arbiter Event Address Register 352e080313cSDave Liu */ 353e080313cSDave Liu #define AEATR_EVENT 0x07000000 /* Event type */ 354e080313cSDave Liu #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 355e080313cSDave Liu #define AEATR_TBST 0x00000800 /* Transfer burst */ 356e080313cSDave Liu #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 357e080313cSDave Liu #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 358e080313cSDave Liu 359e080313cSDave Liu /* HRCWL - Hard Reset Configuration Word Low 360e080313cSDave Liu */ 361e080313cSDave Liu #define HRCWL_LBIUCM 0x80000000 362e080313cSDave Liu #define HRCWL_LBIUCM_SHIFT 31 363e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 364e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 365e080313cSDave Liu 366e080313cSDave Liu #define HRCWL_DDRCM 0x40000000 367e080313cSDave Liu #define HRCWL_DDRCM_SHIFT 30 368e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 369e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 370e080313cSDave Liu 371e080313cSDave Liu #define HRCWL_SPMF 0x0f000000 372e080313cSDave Liu #define HRCWL_SPMF_SHIFT 24 373e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 374e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 375e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 376e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 377e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 378e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 379e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 380e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 381e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 382e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 383e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 384e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 385e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 386e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 387e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 388e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 389e080313cSDave Liu 390e080313cSDave Liu #define HRCWL_VCO_BYPASS 0x00000000 391e080313cSDave Liu #define HRCWL_VCO_1X2 0x00000000 392e080313cSDave Liu #define HRCWL_VCO_1X4 0x00200000 393e080313cSDave Liu #define HRCWL_VCO_1X8 0x00400000 394e080313cSDave Liu 395e080313cSDave Liu #define HRCWL_COREPLL 0x007F0000 396e080313cSDave Liu #define HRCWL_COREPLL_SHIFT 16 397e080313cSDave Liu #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 398e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1X1 0x00020000 399e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 400e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2X1 0x00040000 401e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 402e080313cSDave Liu #define HRCWL_CORE_TO_CSB_3X1 0x00060000 403e080313cSDave Liu 40424c3aca3SDave Liu #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 405e080313cSDave Liu #define HRCWL_CEVCOD 0x000000C0 406e080313cSDave Liu #define HRCWL_CEVCOD_SHIFT 6 407e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 408e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 409e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 410e080313cSDave Liu 411e080313cSDave Liu #define HRCWL_CEPDF 0x00000020 412e080313cSDave Liu #define HRCWL_CEPDF_SHIFT 5 413e080313cSDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 414e080313cSDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 415e080313cSDave Liu 416e080313cSDave Liu #define HRCWL_CEPMF 0x0000001F 417e080313cSDave Liu #define HRCWL_CEPMF_SHIFT 0 418e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 419e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 420e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 421e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 422e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 423e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 424e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 425e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 426e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 427e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 428e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 429e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 430e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 431e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 432e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 433e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 434e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 435e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 436e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 437e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 438e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 439e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 440e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 441e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 442e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 443e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 444e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 445e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 446e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 447e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 448e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 449*03051c3dSDave Liu 450*03051c3dSDave Liu #elif defined(CONFIG_MPC837X) 451*03051c3dSDave Liu #define HRCWL_SVCOD 0x30000000 452*03051c3dSDave Liu #define HRCWL_SVCOD_SHIFT 28 453*03051c3dSDave Liu #define HRCWL_SVCOD_DIV_4 0x00000000 454*03051c3dSDave Liu #define HRCWL_SVCOD_DIV_8 0x10000000 455*03051c3dSDave Liu #define HRCWL_SVCOD_DIV_2 0x20000000 456*03051c3dSDave Liu #define HRCWL_SVCOD_DIV_1 0x30000000 457e080313cSDave Liu #endif 458e080313cSDave Liu 459e080313cSDave Liu /* HRCWH - Hardware Reset Configuration Word High 460e080313cSDave Liu */ 461e080313cSDave Liu #define HRCWH_PCI_HOST 0x80000000 462e080313cSDave Liu #define HRCWH_PCI_HOST_SHIFT 31 463e080313cSDave Liu #define HRCWH_PCI_AGENT 0x00000000 464e080313cSDave Liu 4653e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 466e080313cSDave Liu #define HRCWH_32_BIT_PCI 0x00000000 467e080313cSDave Liu #define HRCWH_64_BIT_PCI 0x40000000 468e080313cSDave Liu #endif 469e080313cSDave Liu 470e080313cSDave Liu #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 471e080313cSDave Liu #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 472e080313cSDave Liu 473e080313cSDave Liu #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 474e080313cSDave Liu #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 475e080313cSDave Liu 4763e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 477e080313cSDave Liu #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 478e080313cSDave Liu #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 479e080313cSDave Liu 480e080313cSDave Liu #elif defined(CONFIG_MPC8360) 481e080313cSDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 482e080313cSDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 483e080313cSDave Liu #endif 484e080313cSDave Liu 485e080313cSDave Liu #define HRCWH_CORE_DISABLE 0x08000000 486e080313cSDave Liu #define HRCWH_CORE_ENABLE 0x00000000 487e080313cSDave Liu 488e080313cSDave Liu #define HRCWH_FROM_0X00000100 0x00000000 489e080313cSDave Liu #define HRCWH_FROM_0XFFF00100 0x04000000 490e080313cSDave Liu 491e080313cSDave Liu #define HRCWH_BOOTSEQ_DISABLE 0x00000000 492e080313cSDave Liu #define HRCWH_BOOTSEQ_NORMAL 0x01000000 493e080313cSDave Liu #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 494e080313cSDave Liu 495e080313cSDave Liu #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 496e080313cSDave Liu #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 497e080313cSDave Liu 498e080313cSDave Liu #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 499e080313cSDave Liu #define HRCWH_ROM_LOC_PCI1 0x00100000 5003e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 501e080313cSDave Liu #define HRCWH_ROM_LOC_PCI2 0x00200000 502e080313cSDave Liu #endif 503*03051c3dSDave Liu #if defined(CONIFG_MPC837X) 504*03051c3dSDave Liu #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000 505*03051c3dSDave Liu #endif 506e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 507e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 508e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 509e080313cSDave Liu 510*03051c3dSDave Liu #if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X) 511d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 512d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 513d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 514d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 515d87c57b2SScott Wood 516d87c57b2SScott Wood #define HRCWH_RL_EXT_LEGACY 0x00000000 517d87c57b2SScott Wood #define HRCWH_RL_EXT_NAND 0x00040000 518d87c57b2SScott Wood 519d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_MII 0x00000000 520d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RMII 0x00002000 521d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RGMII 0x00006000 522d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 523d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 524d87c57b2SScott Wood 525d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_MII 0x00000000 526d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RMII 0x00000400 527d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 528d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RTBI 0x00001400 529d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_SGMII 0x00001800 530d87c57b2SScott Wood #endif 531d87c57b2SScott Wood 5323e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 533e080313cSDave Liu #define HRCWH_TSEC1M_IN_RGMII 0x00000000 534e080313cSDave Liu #define HRCWH_TSEC1M_IN_RTBI 0x00004000 535e080313cSDave Liu #define HRCWH_TSEC1M_IN_GMII 0x00008000 536e080313cSDave Liu #define HRCWH_TSEC1M_IN_TBI 0x0000C000 537e080313cSDave Liu #define HRCWH_TSEC2M_IN_RGMII 0x00000000 538e080313cSDave Liu #define HRCWH_TSEC2M_IN_RTBI 0x00001000 539e080313cSDave Liu #define HRCWH_TSEC2M_IN_GMII 0x00002000 540e080313cSDave Liu #define HRCWH_TSEC2M_IN_TBI 0x00003000 541e080313cSDave Liu #endif 542e080313cSDave Liu 543e080313cSDave Liu #if defined(CONFIG_MPC8360) 544e080313cSDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 545e080313cSDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 546e080313cSDave Liu #endif 547e080313cSDave Liu 548e080313cSDave Liu #define HRCWH_BIG_ENDIAN 0x00000000 549e080313cSDave Liu #define HRCWH_LITTLE_ENDIAN 0x00000008 550e080313cSDave Liu 551e080313cSDave Liu #define HRCWH_LALE_NORMAL 0x00000000 552e080313cSDave Liu #define HRCWH_LALE_EARLY 0x00000004 553e080313cSDave Liu 554e080313cSDave Liu #define HRCWH_LDP_SET 0x00000000 555e080313cSDave Liu #define HRCWH_LDP_CLEAR 0x00000002 556e080313cSDave Liu 557e080313cSDave Liu /* RSR - Reset Status Register 558e080313cSDave Liu */ 559*03051c3dSDave Liu #if defined(CONFIG_MPC837X) 560*03051c3dSDave Liu #define RSR_RSTSRC 0xF0000000 /* Reset source */ 561*03051c3dSDave Liu #define RSR_RSTSRC_SHIFT 28 562*03051c3dSDave Liu #else 563e080313cSDave Liu #define RSR_RSTSRC 0xE0000000 /* Reset source */ 564e080313cSDave Liu #define RSR_RSTSRC_SHIFT 29 565*03051c3dSDave Liu #endif 566e080313cSDave Liu #define RSR_BSF 0x00010000 /* Boot seq. fail */ 567e080313cSDave Liu #define RSR_BSF_SHIFT 16 568e080313cSDave Liu #define RSR_SWSR 0x00002000 /* software soft reset */ 569e080313cSDave Liu #define RSR_SWSR_SHIFT 13 570e080313cSDave Liu #define RSR_SWHR 0x00001000 /* software hard reset */ 571e080313cSDave Liu #define RSR_SWHR_SHIFT 12 572e080313cSDave Liu #define RSR_JHRS 0x00000200 /* jtag hreset */ 573e080313cSDave Liu #define RSR_JHRS_SHIFT 9 574e080313cSDave Liu #define RSR_JSRS 0x00000100 /* jtag sreset status */ 575e080313cSDave Liu #define RSR_JSRS_SHIFT 8 576e080313cSDave Liu #define RSR_CSHR 0x00000010 /* checkstop reset status */ 577e080313cSDave Liu #define RSR_CSHR_SHIFT 4 578e080313cSDave Liu #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 579e080313cSDave Liu #define RSR_SWRS_SHIFT 3 580e080313cSDave Liu #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 581e080313cSDave Liu #define RSR_BMRS_SHIFT 2 582e080313cSDave Liu #define RSR_SRS 0x00000002 /* soft reset status */ 583e080313cSDave Liu #define RSR_SRS_SHIFT 1 584e080313cSDave Liu #define RSR_HRS 0x00000001 /* hard reset status */ 585e080313cSDave Liu #define RSR_HRS_SHIFT 0 586e080313cSDave Liu #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 587e080313cSDave Liu RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 588e080313cSDave Liu RSR_BMRS | RSR_SRS | RSR_HRS) 589e080313cSDave Liu /* RMR - Reset Mode Register 590e080313cSDave Liu */ 591e080313cSDave Liu #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 592e080313cSDave Liu #define RMR_CSRE_SHIFT 0 593e080313cSDave Liu #define RMR_RES ~(RMR_CSRE) 594e080313cSDave Liu 595e080313cSDave Liu /* RCR - Reset Control Register 596e080313cSDave Liu */ 597e080313cSDave Liu #define RCR_SWHR 0x00000002 /* software hard reset */ 598e080313cSDave Liu #define RCR_SWSR 0x00000001 /* software soft reset */ 599e080313cSDave Liu #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 600e080313cSDave Liu 601e080313cSDave Liu /* RCER - Reset Control Enable Register 602e080313cSDave Liu */ 603e080313cSDave Liu #define RCER_CRE 0x00000001 /* software hard reset */ 604e080313cSDave Liu #define RCER_RES ~(RCER_CRE) 605e080313cSDave Liu 606e080313cSDave Liu /* SPMR - System PLL Mode Register 607e080313cSDave Liu */ 608e080313cSDave Liu #define SPMR_LBIUCM 0x80000000 609e080313cSDave Liu #define SPMR_DDRCM 0x40000000 610e080313cSDave Liu #define SPMR_SPMF 0x0F000000 611e080313cSDave Liu #define SPMR_CKID 0x00800000 612e080313cSDave Liu #define SPMR_CKID_SHIFT 23 613e080313cSDave Liu #define SPMR_COREPLL 0x007F0000 614e080313cSDave Liu #define SPMR_CEVCOD 0x000000C0 615e080313cSDave Liu #define SPMR_CEPDF 0x00000020 616e080313cSDave Liu #define SPMR_CEPMF 0x0000001F 617e080313cSDave Liu 618e080313cSDave Liu /* OCCR - Output Clock Control Register 619e080313cSDave Liu */ 620e080313cSDave Liu #define OCCR_PCICOE0 0x80000000 621e080313cSDave Liu #define OCCR_PCICOE1 0x40000000 622e080313cSDave Liu #define OCCR_PCICOE2 0x20000000 623e080313cSDave Liu #define OCCR_PCICOE3 0x10000000 624e080313cSDave Liu #define OCCR_PCICOE4 0x08000000 625e080313cSDave Liu #define OCCR_PCICOE5 0x04000000 626e080313cSDave Liu #define OCCR_PCICOE6 0x02000000 627e080313cSDave Liu #define OCCR_PCICOE7 0x01000000 628e080313cSDave Liu #define OCCR_PCICD0 0x00800000 629e080313cSDave Liu #define OCCR_PCICD1 0x00400000 630e080313cSDave Liu #define OCCR_PCICD2 0x00200000 631e080313cSDave Liu #define OCCR_PCICD3 0x00100000 632e080313cSDave Liu #define OCCR_PCICD4 0x00080000 633e080313cSDave Liu #define OCCR_PCICD5 0x00040000 634e080313cSDave Liu #define OCCR_PCICD6 0x00020000 635e080313cSDave Liu #define OCCR_PCICD7 0x00010000 636e080313cSDave Liu #define OCCR_PCI1CR 0x00000002 637e080313cSDave Liu #define OCCR_PCI2CR 0x00000001 638e080313cSDave Liu #define OCCR_PCICR OCCR_PCI1CR 639e080313cSDave Liu 640e080313cSDave Liu /* SCCR - System Clock Control Register 641e080313cSDave Liu */ 642e080313cSDave Liu #define SCCR_ENCCM 0x03000000 643e080313cSDave Liu #define SCCR_ENCCM_SHIFT 24 644e080313cSDave Liu #define SCCR_ENCCM_0 0x00000000 645e080313cSDave Liu #define SCCR_ENCCM_1 0x01000000 646e080313cSDave Liu #define SCCR_ENCCM_2 0x02000000 647e080313cSDave Liu #define SCCR_ENCCM_3 0x03000000 648e080313cSDave Liu 649e080313cSDave Liu #define SCCR_PCICM 0x00010000 650e080313cSDave Liu #define SCCR_PCICM_SHIFT 16 651e080313cSDave Liu 652*03051c3dSDave Liu #if defined(CONFIG_MPC834X) 653*03051c3dSDave Liu /* SCCR bits - MPC834x specific */ 654e080313cSDave Liu #define SCCR_TSEC1CM 0xc0000000 655e080313cSDave Liu #define SCCR_TSEC1CM_SHIFT 30 656e080313cSDave Liu #define SCCR_TSEC1CM_0 0x00000000 657e080313cSDave Liu #define SCCR_TSEC1CM_1 0x40000000 658e080313cSDave Liu #define SCCR_TSEC1CM_2 0x80000000 659e080313cSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 660e080313cSDave Liu 661e080313cSDave Liu #define SCCR_TSEC2CM 0x30000000 662e080313cSDave Liu #define SCCR_TSEC2CM_SHIFT 28 663e080313cSDave Liu #define SCCR_TSEC2CM_0 0x00000000 664e080313cSDave Liu #define SCCR_TSEC2CM_1 0x10000000 665e080313cSDave Liu #define SCCR_TSEC2CM_2 0x20000000 666e080313cSDave Liu #define SCCR_TSEC2CM_3 0x30000000 667d87c57b2SScott Wood 668*03051c3dSDave Liu /* The MPH must have the same clock ratio as DR, unless its clock disabled */ 669*03051c3dSDave Liu #define SCCR_USBMPHCM 0x00c00000 670*03051c3dSDave Liu #define SCCR_USBMPHCM_SHIFT 22 671*03051c3dSDave Liu #define SCCR_USBDRCM 0x00300000 672*03051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 20 673*03051c3dSDave Liu #define SCCR_USBCM 0x00f00000 674*03051c3dSDave Liu #define SCCR_USBCM_SHIFT 20 675*03051c3dSDave Liu #define SCCR_USBCM_0 0x00000000 676*03051c3dSDave Liu #define SCCR_USBCM_1 0x00500000 677*03051c3dSDave Liu #define SCCR_USBCM_2 0x00A00000 678*03051c3dSDave Liu #define SCCR_USBCM_3 0x00F00000 679*03051c3dSDave Liu 680d87c57b2SScott Wood #elif defined(CONFIG_MPC831X) 681d87c57b2SScott Wood /* TSEC1 bits are for TSEC2 as well */ 682d87c57b2SScott Wood #define SCCR_TSEC1CM 0xc0000000 683d87c57b2SScott Wood #define SCCR_TSEC1CM_SHIFT 30 684d87c57b2SScott Wood #define SCCR_TSEC1CM_1 0x40000000 685d87c57b2SScott Wood #define SCCR_TSEC1CM_2 0x80000000 686d87c57b2SScott Wood #define SCCR_TSEC1CM_3 0xC0000000 687d87c57b2SScott Wood 688d87c57b2SScott Wood #define SCCR_TSEC1ON 0x20000000 689df33f6b4STimur Tabi #define SCCR_TSEC1ON_SHIFT 29 690d87c57b2SScott Wood #define SCCR_TSEC2ON 0x10000000 691df33f6b4STimur Tabi #define SCCR_TSEC2ON_SHIFT 28 692d87c57b2SScott Wood 693e080313cSDave Liu #define SCCR_USBDRCM 0x00300000 694e080313cSDave Liu #define SCCR_USBDRCM_SHIFT 20 695*03051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 696*03051c3dSDave Liu #define SCCR_USBDRCM_1 0x00100000 697*03051c3dSDave Liu #define SCCR_USBDRCM_2 0x00200000 698*03051c3dSDave Liu #define SCCR_USBDRCM_3 0x00300000 699e080313cSDave Liu 700*03051c3dSDave Liu #elif defined(CONFIG_MPC837X) 701*03051c3dSDave Liu /* SCCR bits - MPC837x specific */ 702*03051c3dSDave Liu #define SCCR_TSEC1CM 0xc0000000 703*03051c3dSDave Liu #define SCCR_TSEC1CM_SHIFT 30 704*03051c3dSDave Liu #define SCCR_TSEC1CM_0 0x00000000 705*03051c3dSDave Liu #define SCCR_TSEC1CM_1 0x40000000 706*03051c3dSDave Liu #define SCCR_TSEC1CM_2 0x80000000 707*03051c3dSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 708*03051c3dSDave Liu 709*03051c3dSDave Liu #define SCCR_TSEC2CM 0x30000000 710*03051c3dSDave Liu #define SCCR_TSEC2CM_SHIFT 28 711*03051c3dSDave Liu #define SCCR_TSEC2CM_0 0x00000000 712*03051c3dSDave Liu #define SCCR_TSEC2CM_1 0x10000000 713*03051c3dSDave Liu #define SCCR_TSEC2CM_2 0x20000000 714*03051c3dSDave Liu #define SCCR_TSEC2CM_3 0x30000000 715*03051c3dSDave Liu 716*03051c3dSDave Liu #define SCCR_SDHCCM 0x0c000000 717*03051c3dSDave Liu #define SCCR_SDHCCM_SHIFT 26 718*03051c3dSDave Liu #define SCCR_SDHCCM_0 0x00000000 719*03051c3dSDave Liu #define SCCR_SDHCCM_1 0x04000000 720*03051c3dSDave Liu #define SCCR_SDHCCM_2 0x08000000 721*03051c3dSDave Liu #define SCCR_SDHCCM_3 0x0c000000 722*03051c3dSDave Liu 723*03051c3dSDave Liu #define SCCR_USBDRCM 0x00c00000 724*03051c3dSDave Liu #define SCCR_USBDRCM_SHIFT 22 725*03051c3dSDave Liu #define SCCR_USBDRCM_0 0x00000000 726*03051c3dSDave Liu #define SCCR_USBDRCM_1 0x00400000 727*03051c3dSDave Liu #define SCCR_USBDRCM_2 0x00800000 728*03051c3dSDave Liu #define SCCR_USBDRCM_3 0x00c00000 729*03051c3dSDave Liu 730*03051c3dSDave Liu #define SCCR_PCIEXP1CM 0x00300000 731*03051c3dSDave Liu #define SCCR_PCIEXP1CM_SHIFT 20 732*03051c3dSDave Liu #define SCCR_PCIEXP1CM_0 0x00000000 733*03051c3dSDave Liu #define SCCR_PCIEXP1CM_1 0x00100000 734*03051c3dSDave Liu #define SCCR_PCIEXP1CM_2 0x00200000 735*03051c3dSDave Liu #define SCCR_PCIEXP1CM_3 0x00300000 736*03051c3dSDave Liu 737*03051c3dSDave Liu #define SCCR_PCIEXP2CM 0x000c0000 738*03051c3dSDave Liu #define SCCR_PCIEXP2CM_SHIFT 18 739*03051c3dSDave Liu #define SCCR_PCIEXP2CM_0 0x00000000 740*03051c3dSDave Liu #define SCCR_PCIEXP2CM_1 0x00040000 741*03051c3dSDave Liu #define SCCR_PCIEXP2CM_2 0x00080000 742*03051c3dSDave Liu #define SCCR_PCIEXP2CM_3 0x000c0000 743*03051c3dSDave Liu 744*03051c3dSDave Liu /* All of the four SATA controllers must have the same clock ratio */ 745*03051c3dSDave Liu #define SCCR_SATA1CM 0x000000c0 746*03051c3dSDave Liu #define SCCR_SATA1CM_SHIFT 6 747*03051c3dSDave Liu #define SCCR_SATACM 0x000000ff 748*03051c3dSDave Liu #define SCCR_SATACM_SHIFT 0 749*03051c3dSDave Liu #define SCCR_SATACM_0 0x00000000 750*03051c3dSDave Liu #define SCCR_SATACM_1 0x00000055 751*03051c3dSDave Liu #define SCCR_SATACM_2 0x000000aa 752*03051c3dSDave Liu #define SCCR_SATACM_3 0x000000ff 753*03051c3dSDave Liu #endif 754e080313cSDave Liu 755e080313cSDave Liu /* CSn_BDNS - Chip Select memory Bounds Register 756e080313cSDave Liu */ 757e080313cSDave Liu #define CSBNDS_SA 0x00FF0000 758e080313cSDave Liu #define CSBNDS_SA_SHIFT 8 759e080313cSDave Liu #define CSBNDS_EA 0x000000FF 760e080313cSDave Liu #define CSBNDS_EA_SHIFT 24 761e080313cSDave Liu 762e080313cSDave Liu /* CSn_CONFIG - Chip Select Configuration Register 763e080313cSDave Liu */ 764e080313cSDave Liu #define CSCONFIG_EN 0x80000000 765e080313cSDave Liu #define CSCONFIG_AP 0x00800000 766e080313cSDave Liu #define CSCONFIG_ROW_BIT 0x00000700 767e080313cSDave Liu #define CSCONFIG_ROW_BIT_12 0x00000000 768e080313cSDave Liu #define CSCONFIG_ROW_BIT_13 0x00000100 769e080313cSDave Liu #define CSCONFIG_ROW_BIT_14 0x00000200 770e080313cSDave Liu #define CSCONFIG_COL_BIT 0x00000007 771e080313cSDave Liu #define CSCONFIG_COL_BIT_8 0x00000000 772e080313cSDave Liu #define CSCONFIG_COL_BIT_9 0x00000001 773e080313cSDave Liu #define CSCONFIG_COL_BIT_10 0x00000002 774e080313cSDave Liu #define CSCONFIG_COL_BIT_11 0x00000003 775e080313cSDave Liu 776d87c57b2SScott Wood /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 777d87c57b2SScott Wood */ 778d87c57b2SScott Wood #define TIMING_CFG0_RWT 0xC0000000 779d87c57b2SScott Wood #define TIMING_CFG0_RWT_SHIFT 30 780d87c57b2SScott Wood #define TIMING_CFG0_WRT 0x30000000 781d87c57b2SScott Wood #define TIMING_CFG0_WRT_SHIFT 28 782d87c57b2SScott Wood #define TIMING_CFG0_RRT 0x0C000000 783d87c57b2SScott Wood #define TIMING_CFG0_RRT_SHIFT 26 784d87c57b2SScott Wood #define TIMING_CFG0_WWT 0x03000000 785d87c57b2SScott Wood #define TIMING_CFG0_WWT_SHIFT 24 786d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 787d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 788d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 789d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 790d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 791d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 792d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC 0x00000F00 793d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC_SHIFT 0 794d87c57b2SScott Wood 795e080313cSDave Liu /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 796e080313cSDave Liu */ 797e080313cSDave Liu #define TIMING_CFG1_PRETOACT 0x70000000 798e080313cSDave Liu #define TIMING_CFG1_PRETOACT_SHIFT 28 799e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE 0x0F000000 800e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE_SHIFT 24 801e080313cSDave Liu #define TIMING_CFG1_ACTTORW 0x00700000 802e080313cSDave Liu #define TIMING_CFG1_ACTTORW_SHIFT 20 803e080313cSDave Liu #define TIMING_CFG1_CASLAT 0x00070000 804e080313cSDave Liu #define TIMING_CFG1_CASLAT_SHIFT 16 805e080313cSDave Liu #define TIMING_CFG1_REFREC 0x0000F000 806e080313cSDave Liu #define TIMING_CFG1_REFREC_SHIFT 12 807e080313cSDave Liu #define TIMING_CFG1_WRREC 0x00000700 808e080313cSDave Liu #define TIMING_CFG1_WRREC_SHIFT 8 809e080313cSDave Liu #define TIMING_CFG1_ACTTOACT 0x00000070 810e080313cSDave Liu #define TIMING_CFG1_ACTTOACT_SHIFT 4 811e080313cSDave Liu #define TIMING_CFG1_WRTORD 0x00000007 812e080313cSDave Liu #define TIMING_CFG1_WRTORD_SHIFT 0 813e080313cSDave Liu #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 814e080313cSDave Liu #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 815e080313cSDave Liu 816e080313cSDave Liu /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 817e080313cSDave Liu */ 8188d172c0fSXie Xiaobo #define TIMING_CFG2_CPO 0x0F800000 8198d172c0fSXie Xiaobo #define TIMING_CFG2_CPO_SHIFT 23 820e080313cSDave Liu #define TIMING_CFG2_ACSM 0x00080000 821e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 822e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 823e080313cSDave Liu #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 824e080313cSDave Liu 825d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT 0x70000000 826d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT_SHIFT 28 827d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 828d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 829d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE 0x0000E000 830d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 831d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS 0x000001C0 832d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS_SHIFT 6 833d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT 0x0000003F 834d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT_SHIFT 0 835d87c57b2SScott Wood 836e080313cSDave Liu /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 837e080313cSDave Liu */ 838e080313cSDave Liu #define SDRAM_CFG_MEM_EN 0x80000000 839e080313cSDave Liu #define SDRAM_CFG_SREN 0x40000000 840e080313cSDave Liu #define SDRAM_CFG_ECC_EN 0x20000000 841e080313cSDave Liu #define SDRAM_CFG_RD_EN 0x10000000 842bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 843bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 844bbea46f7SKim Phillips #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 845e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 846e080313cSDave Liu #define SDRAM_CFG_DYN_PWR 0x00200000 847e080313cSDave Liu #define SDRAM_CFG_32_BE 0x00080000 848e080313cSDave Liu #define SDRAM_CFG_8_BE 0x00040000 849e080313cSDave Liu #define SDRAM_CFG_NCAP 0x00020000 850e080313cSDave Liu #define SDRAM_CFG_2T_EN 0x00008000 851d87c57b2SScott Wood #define SDRAM_CFG_BI 0x00000001 852e080313cSDave Liu 853e080313cSDave Liu /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 854e080313cSDave Liu */ 855e080313cSDave Liu #define SDRAM_MODE_ESD 0xFFFF0000 856e080313cSDave Liu #define SDRAM_MODE_ESD_SHIFT 16 857e080313cSDave Liu #define SDRAM_MODE_SD 0x0000FFFF 858e080313cSDave Liu #define SDRAM_MODE_SD_SHIFT 0 859e080313cSDave Liu #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 860e080313cSDave Liu #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 861e080313cSDave Liu #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 862e080313cSDave Liu #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 863e080313cSDave Liu #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 864e080313cSDave Liu #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 865e080313cSDave Liu #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 866e080313cSDave Liu #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 867e080313cSDave Liu #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 868e080313cSDave Liu #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 869e080313cSDave Liu #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 870e080313cSDave Liu #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 871e080313cSDave Liu #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 872e080313cSDave Liu #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 873e080313cSDave Liu #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 874e080313cSDave Liu #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 875e080313cSDave Liu #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 876e080313cSDave Liu #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 877e080313cSDave Liu #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 878e080313cSDave Liu 879e080313cSDave Liu /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 880e080313cSDave Liu */ 881e080313cSDave Liu #define SDRAM_INTERVAL_REFINT 0x3FFF0000 882e080313cSDave Liu #define SDRAM_INTERVAL_REFINT_SHIFT 16 883e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 884e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 885e080313cSDave Liu 886e080313cSDave Liu /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 887e080313cSDave Liu */ 888e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 889e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 890e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 891e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 892e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 893e080313cSDave Liu 894e080313cSDave Liu /* ECC_ERR_INJECT - Memory data path error injection mask ECC 895e080313cSDave Liu */ 896e080313cSDave Liu #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 897e080313cSDave Liu #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 898e080313cSDave Liu #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 899e080313cSDave Liu #define ECC_ERR_INJECT_EEIM_SHIFT 0 900e080313cSDave Liu 901e080313cSDave Liu /* CAPTURE_ECC - Memory data path read capture ECC 902e080313cSDave Liu */ 903e080313cSDave Liu #define CAPTURE_ECC_ECE (0xff000000>>24) 904e080313cSDave Liu #define CAPTURE_ECC_ECE_SHIFT 0 905e080313cSDave Liu 906e080313cSDave Liu /* ERR_DETECT - Memory error detect 907e080313cSDave Liu */ 908e080313cSDave Liu #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 909e080313cSDave Liu #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 910e080313cSDave Liu #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 911e080313cSDave Liu #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 912e080313cSDave Liu 913e080313cSDave Liu /* ERR_DISABLE - Memory error disable 914e080313cSDave Liu */ 915e080313cSDave Liu #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 916e080313cSDave Liu #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 917e080313cSDave Liu #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 918e080313cSDave Liu #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 919e080313cSDave Liu ECC_ERROR_DISABLE_MBED) 920e080313cSDave Liu /* ERR_INT_EN - Memory error interrupt enable 921e080313cSDave Liu */ 922e080313cSDave Liu #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 923e080313cSDave Liu #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 924e080313cSDave Liu #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 925e080313cSDave Liu #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 926e080313cSDave Liu ECC_ERR_INT_EN_MSEE) 927e080313cSDave Liu /* CAPTURE_ATTRIBUTES - Memory error attributes capture 928e080313cSDave Liu */ 929e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 930e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM_SHIFT 28 931e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 932e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 933e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 934e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 935e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 936e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 937e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 938e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 939e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 940e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 941e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 942e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 943e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 944e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_I2C 0x9 945e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 946e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 947e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 948e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_DMA 0xF 949e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_SHIFT 16 950e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 951e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 952e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_READ 0x2 953e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 954e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_SHIFT 12 955e080313cSDave Liu #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 956e080313cSDave Liu 957e080313cSDave Liu /* ERR_SBE - Single bit ECC memory error management 958e080313cSDave Liu */ 959e080313cSDave Liu #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 960e080313cSDave Liu #define ECC_ERROR_MAN_SBET_SHIFT 16 961e080313cSDave Liu #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 962e080313cSDave Liu #define ECC_ERROR_MAN_SBEC_SHIFT 0 963e080313cSDave Liu 964e080313cSDave Liu /* BR - Base Registers 965e080313cSDave Liu */ 966e080313cSDave Liu #define BR0 0x5000 /* Register offset to immr */ 967f046ccd1SEran Liberty #define BR1 0x5008 968f046ccd1SEran Liberty #define BR2 0x5010 969f046ccd1SEran Liberty #define BR3 0x5018 970f046ccd1SEran Liberty #define BR4 0x5020 971f046ccd1SEran Liberty #define BR5 0x5028 972f046ccd1SEran Liberty #define BR6 0x5030 973f046ccd1SEran Liberty #define BR7 0x5038 974f046ccd1SEran Liberty 975f046ccd1SEran Liberty #define BR_BA 0xFFFF8000 976f046ccd1SEran Liberty #define BR_BA_SHIFT 15 977f046ccd1SEran Liberty #define BR_PS 0x00001800 978f046ccd1SEran Liberty #define BR_PS_SHIFT 11 979e6f2e902SMarian Balakowicz #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 980e6f2e902SMarian Balakowicz #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 981e6f2e902SMarian Balakowicz #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 982f046ccd1SEran Liberty #define BR_DECC 0x00000600 983f046ccd1SEran Liberty #define BR_DECC_SHIFT 9 984d87c57b2SScott Wood #define BR_DECC_OFF 0x00000000 985d87c57b2SScott Wood #define BR_DECC_CHK 0x00000200 986d87c57b2SScott Wood #define BR_DECC_CHK_GEN 0x00000400 987f046ccd1SEran Liberty #define BR_WP 0x00000100 988f046ccd1SEran Liberty #define BR_WP_SHIFT 8 989f046ccd1SEran Liberty #define BR_MSEL 0x000000E0 990f046ccd1SEran Liberty #define BR_MSEL_SHIFT 5 991e6f2e902SMarian Balakowicz #define BR_MS_GPCM 0x00000000 /* GPCM */ 992d87c57b2SScott Wood #define BR_MS_FCM 0x00000020 /* FCM */ 993e6f2e902SMarian Balakowicz #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 994e6f2e902SMarian Balakowicz #define BR_MS_UPMA 0x00000080 /* UPMA */ 995e6f2e902SMarian Balakowicz #define BR_MS_UPMB 0x000000A0 /* UPMB */ 996e6f2e902SMarian Balakowicz #define BR_MS_UPMC 0x000000C0 /* UPMC */ 997*03051c3dSDave Liu #if !defined(CONFIG_MPC834X) 9985f820439SDave Liu #define BR_ATOM 0x0000000C 9995f820439SDave Liu #define BR_ATOM_SHIFT 2 10005f820439SDave Liu #endif 1001f046ccd1SEran Liberty #define BR_V 0x00000001 1002f046ccd1SEran Liberty #define BR_V_SHIFT 0 1003e080313cSDave Liu 10043e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 1005f046ccd1SEran Liberty #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) 1006*03051c3dSDave Liu #else 10075f820439SDave Liu #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) 10085f820439SDave Liu #endif 1009f046ccd1SEran Liberty 1010e080313cSDave Liu /* OR - Option Registers 1011e080313cSDave Liu */ 1012e080313cSDave Liu #define OR0 0x5004 /* Register offset to immr */ 1013f046ccd1SEran Liberty #define OR1 0x500C 1014f046ccd1SEran Liberty #define OR2 0x5014 1015f046ccd1SEran Liberty #define OR3 0x501C 1016f046ccd1SEran Liberty #define OR4 0x5024 1017f046ccd1SEran Liberty #define OR5 0x502C 1018f046ccd1SEran Liberty #define OR6 0x5034 1019f046ccd1SEran Liberty #define OR7 0x503C 1020f046ccd1SEran Liberty 1021f046ccd1SEran Liberty #define OR_GPCM_AM 0xFFFF8000 1022f046ccd1SEran Liberty #define OR_GPCM_AM_SHIFT 15 1023f046ccd1SEran Liberty #define OR_GPCM_BCTLD 0x00001000 1024f046ccd1SEran Liberty #define OR_GPCM_BCTLD_SHIFT 12 1025f046ccd1SEran Liberty #define OR_GPCM_CSNT 0x00000800 1026f046ccd1SEran Liberty #define OR_GPCM_CSNT_SHIFT 11 1027f046ccd1SEran Liberty #define OR_GPCM_ACS 0x00000600 1028f046ccd1SEran Liberty #define OR_GPCM_ACS_SHIFT 9 1029e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b10 0x00000400 1030e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b11 0x00000600 1031f046ccd1SEran Liberty #define OR_GPCM_XACS 0x00000100 1032f046ccd1SEran Liberty #define OR_GPCM_XACS_SHIFT 8 1033f046ccd1SEran Liberty #define OR_GPCM_SCY 0x000000F0 1034f046ccd1SEran Liberty #define OR_GPCM_SCY_SHIFT 4 1035e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_1 0x00000010 1036e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_2 0x00000020 1037e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_3 0x00000030 1038e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_4 0x00000040 1039e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_5 0x00000050 1040e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_6 0x00000060 1041e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_7 0x00000070 1042e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_8 0x00000080 1043e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_9 0x00000090 1044e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_10 0x000000a0 1045e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_11 0x000000b0 1046e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_12 0x000000c0 1047e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_13 0x000000d0 1048e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_14 0x000000e0 1049e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_15 0x000000f0 1050f046ccd1SEran Liberty #define OR_GPCM_SETA 0x00000008 1051f046ccd1SEran Liberty #define OR_GPCM_SETA_SHIFT 3 1052f046ccd1SEran Liberty #define OR_GPCM_TRLX 0x00000004 1053f046ccd1SEran Liberty #define OR_GPCM_TRLX_SHIFT 2 1054f046ccd1SEran Liberty #define OR_GPCM_EHTR 0x00000002 1055f046ccd1SEran Liberty #define OR_GPCM_EHTR_SHIFT 1 1056f046ccd1SEran Liberty #define OR_GPCM_EAD 0x00000001 1057f046ccd1SEran Liberty #define OR_GPCM_EAD_SHIFT 0 1058f046ccd1SEran Liberty 1059d87c57b2SScott Wood #define OR_FCM_AM 0xFFFF8000 1060d87c57b2SScott Wood #define OR_FCM_AM_SHIFT 15 1061d87c57b2SScott Wood #define OR_FCM_BCTLD 0x00001000 1062d87c57b2SScott Wood #define OR_FCM_BCTLD_SHIFT 12 1063d87c57b2SScott Wood #define OR_FCM_PGS 0x00000400 1064d87c57b2SScott Wood #define OR_FCM_PGS_SHIFT 10 1065d87c57b2SScott Wood #define OR_FCM_CSCT 0x00000200 1066d87c57b2SScott Wood #define OR_FCM_CSCT_SHIFT 9 1067d87c57b2SScott Wood #define OR_FCM_CST 0x00000100 1068d87c57b2SScott Wood #define OR_FCM_CST_SHIFT 8 1069d87c57b2SScott Wood #define OR_FCM_CHT 0x00000080 1070d87c57b2SScott Wood #define OR_FCM_CHT_SHIFT 7 1071d87c57b2SScott Wood #define OR_FCM_SCY 0x00000070 1072d87c57b2SScott Wood #define OR_FCM_SCY_SHIFT 4 1073d87c57b2SScott Wood #define OR_FCM_SCY_1 0x00000010 1074d87c57b2SScott Wood #define OR_FCM_SCY_2 0x00000020 1075d87c57b2SScott Wood #define OR_FCM_SCY_3 0x00000030 1076d87c57b2SScott Wood #define OR_FCM_SCY_4 0x00000040 1077d87c57b2SScott Wood #define OR_FCM_SCY_5 0x00000050 1078d87c57b2SScott Wood #define OR_FCM_SCY_6 0x00000060 1079d87c57b2SScott Wood #define OR_FCM_SCY_7 0x00000070 1080d87c57b2SScott Wood #define OR_FCM_RST 0x00000008 1081d87c57b2SScott Wood #define OR_FCM_RST_SHIFT 3 1082d87c57b2SScott Wood #define OR_FCM_TRLX 0x00000004 1083d87c57b2SScott Wood #define OR_FCM_TRLX_SHIFT 2 1084d87c57b2SScott Wood #define OR_FCM_EHTR 0x00000002 1085d87c57b2SScott Wood #define OR_FCM_EHTR_SHIFT 1 1086d87c57b2SScott Wood 1087f046ccd1SEran Liberty #define OR_UPM_AM 0xFFFF8000 1088f046ccd1SEran Liberty #define OR_UPM_AM_SHIFT 15 1089f046ccd1SEran Liberty #define OR_UPM_XAM 0x00006000 1090f046ccd1SEran Liberty #define OR_UPM_XAM_SHIFT 13 1091f046ccd1SEran Liberty #define OR_UPM_BCTLD 0x00001000 1092f046ccd1SEran Liberty #define OR_UPM_BCTLD_SHIFT 12 1093f046ccd1SEran Liberty #define OR_UPM_BI 0x00000100 1094f046ccd1SEran Liberty #define OR_UPM_BI_SHIFT 8 1095f046ccd1SEran Liberty #define OR_UPM_TRLX 0x00000004 1096f046ccd1SEran Liberty #define OR_UPM_TRLX_SHIFT 2 1097f046ccd1SEran Liberty #define OR_UPM_EHTR 0x00000002 1098f046ccd1SEran Liberty #define OR_UPM_EHTR_SHIFT 1 1099f046ccd1SEran Liberty #define OR_UPM_EAD 0x00000001 1100f046ccd1SEran Liberty #define OR_UPM_EAD_SHIFT 0 1101f046ccd1SEran Liberty 1102f046ccd1SEran Liberty #define OR_SDRAM_AM 0xFFFF8000 1103f046ccd1SEran Liberty #define OR_SDRAM_AM_SHIFT 15 1104f046ccd1SEran Liberty #define OR_SDRAM_XAM 0x00006000 1105f046ccd1SEran Liberty #define OR_SDRAM_XAM_SHIFT 13 1106f046ccd1SEran Liberty #define OR_SDRAM_COLS 0x00001C00 1107f046ccd1SEran Liberty #define OR_SDRAM_COLS_SHIFT 10 1108f046ccd1SEran Liberty #define OR_SDRAM_ROWS 0x000001C0 1109f046ccd1SEran Liberty #define OR_SDRAM_ROWS_SHIFT 6 1110f046ccd1SEran Liberty #define OR_SDRAM_PMSEL 0x00000020 1111f046ccd1SEran Liberty #define OR_SDRAM_PMSEL_SHIFT 5 1112f046ccd1SEran Liberty #define OR_SDRAM_EAD 0x00000001 1113f046ccd1SEran Liberty #define OR_SDRAM_EAD_SHIFT 0 1114f046ccd1SEran Liberty 11157a78f148STimur Tabi #define OR_AM_32KB 0xFFFF8000 11167a78f148STimur Tabi #define OR_AM_64KB 0xFFFF0000 11177a78f148STimur Tabi #define OR_AM_128KB 0xFFFE0000 11187a78f148STimur Tabi #define OR_AM_256KB 0xFFFC0000 11197a78f148STimur Tabi #define OR_AM_512KB 0xFFF80000 11207a78f148STimur Tabi #define OR_AM_1MB 0xFFF00000 11217a78f148STimur Tabi #define OR_AM_2MB 0xFFE00000 11227a78f148STimur Tabi #define OR_AM_4MB 0xFFC00000 11237a78f148STimur Tabi #define OR_AM_8MB 0xFF800000 11247a78f148STimur Tabi #define OR_AM_16MB 0xFF000000 11257a78f148STimur Tabi #define OR_AM_32MB 0xFE000000 11267a78f148STimur Tabi #define OR_AM_64MB 0xFC000000 11277a78f148STimur Tabi #define OR_AM_128MB 0xF8000000 11287a78f148STimur Tabi #define OR_AM_256MB 0xF0000000 11297a78f148STimur Tabi #define OR_AM_512MB 0xE0000000 11307a78f148STimur Tabi #define OR_AM_1GB 0xC0000000 11317a78f148STimur Tabi #define OR_AM_2GB 0x80000000 11327a78f148STimur Tabi #define OR_AM_4GB 0x00000000 11337a78f148STimur Tabi 11347a78f148STimur Tabi #define LBLAWAR_EN 0x80000000 11357a78f148STimur Tabi #define LBLAWAR_4KB 0x0000000B 11367a78f148STimur Tabi #define LBLAWAR_8KB 0x0000000C 11377a78f148STimur Tabi #define LBLAWAR_16KB 0x0000000D 11387a78f148STimur Tabi #define LBLAWAR_32KB 0x0000000E 11397a78f148STimur Tabi #define LBLAWAR_64KB 0x0000000F 11407a78f148STimur Tabi #define LBLAWAR_128KB 0x00000010 11417a78f148STimur Tabi #define LBLAWAR_256KB 0x00000011 11427a78f148STimur Tabi #define LBLAWAR_512KB 0x00000012 11437a78f148STimur Tabi #define LBLAWAR_1MB 0x00000013 11447a78f148STimur Tabi #define LBLAWAR_2MB 0x00000014 11457a78f148STimur Tabi #define LBLAWAR_4MB 0x00000015 11467a78f148STimur Tabi #define LBLAWAR_8MB 0x00000016 11477a78f148STimur Tabi #define LBLAWAR_16MB 0x00000017 11487a78f148STimur Tabi #define LBLAWAR_32MB 0x00000018 11497a78f148STimur Tabi #define LBLAWAR_64MB 0x00000019 11507a78f148STimur Tabi #define LBLAWAR_128MB 0x0000001A 11517a78f148STimur Tabi #define LBLAWAR_256MB 0x0000001B 11527a78f148STimur Tabi #define LBLAWAR_512MB 0x0000001C 11537a78f148STimur Tabi #define LBLAWAR_1GB 0x0000001D 11547a78f148STimur Tabi #define LBLAWAR_2GB 0x0000001E 11557a78f148STimur Tabi 1156e080313cSDave Liu /* LBCR - Local Bus Configuration Register 1157f046ccd1SEran Liberty */ 1158e080313cSDave Liu #define LBCR_LDIS 0x80000000 1159e080313cSDave Liu #define LBCR_LDIS_SHIFT 31 1160e080313cSDave Liu #define LBCR_BCTLC 0x00C00000 1161e080313cSDave Liu #define LBCR_BCTLC_SHIFT 22 1162e080313cSDave Liu #define LBCR_LPBSE 0x00020000 1163e080313cSDave Liu #define LBCR_LPBSE_SHIFT 17 1164e080313cSDave Liu #define LBCR_EPAR 0x00010000 1165e080313cSDave Liu #define LBCR_EPAR_SHIFT 16 1166e080313cSDave Liu #define LBCR_BMT 0x0000FF00 1167e080313cSDave Liu #define LBCR_BMT_SHIFT 8 1168f046ccd1SEran Liberty 1169e080313cSDave Liu /* LCRR - Clock Ratio Register 1170f046ccd1SEran Liberty */ 1171f046ccd1SEran Liberty #define LCRR_DBYP 0x80000000 1172f046ccd1SEran Liberty #define LCRR_DBYP_SHIFT 31 1173f046ccd1SEran Liberty #define LCRR_BUFCMDC 0x30000000 1174e080313cSDave Liu #define LCRR_BUFCMDC_SHIFT 28 1175f046ccd1SEran Liberty #define LCRR_BUFCMDC_1 0x10000000 1176f046ccd1SEran Liberty #define LCRR_BUFCMDC_2 0x20000000 1177f046ccd1SEran Liberty #define LCRR_BUFCMDC_3 0x30000000 1178f046ccd1SEran Liberty #define LCRR_BUFCMDC_4 0x00000000 1179f046ccd1SEran Liberty #define LCRR_ECL 0x03000000 1180e080313cSDave Liu #define LCRR_ECL_SHIFT 24 1181f046ccd1SEran Liberty #define LCRR_ECL_4 0x00000000 1182f046ccd1SEran Liberty #define LCRR_ECL_5 0x01000000 1183f046ccd1SEran Liberty #define LCRR_ECL_6 0x02000000 1184f046ccd1SEran Liberty #define LCRR_ECL_7 0x03000000 1185f046ccd1SEran Liberty #define LCRR_EADC 0x00030000 1186e080313cSDave Liu #define LCRR_EADC_SHIFT 16 1187f046ccd1SEran Liberty #define LCRR_EADC_1 0x00010000 1188f046ccd1SEran Liberty #define LCRR_EADC_2 0x00020000 1189f046ccd1SEran Liberty #define LCRR_EADC_3 0x00030000 1190f046ccd1SEran Liberty #define LCRR_EADC_4 0x00000000 1191f046ccd1SEran Liberty #define LCRR_CLKDIV 0x0000000F 1192e080313cSDave Liu #define LCRR_CLKDIV_SHIFT 0 1193f046ccd1SEran Liberty #define LCRR_CLKDIV_2 0x00000002 1194f046ccd1SEran Liberty #define LCRR_CLKDIV_4 0x00000004 1195f046ccd1SEran Liberty #define LCRR_CLKDIV_8 0x00000008 1196f046ccd1SEran Liberty 1197e080313cSDave Liu /* DMAMR - DMA Mode Register 1198f6eda7f8SDave Liu */ 1199e080313cSDave Liu #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 1200e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 1201e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 1202e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 1203e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 1204e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 1205e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 1206e080313cSDave Liu #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 1207f6eda7f8SDave Liu 1208e080313cSDave Liu /* DMASR - DMA Status Register 1209e080313cSDave Liu */ 1210e080313cSDave Liu #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 1211e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 12125f820439SDave Liu 1213e080313cSDave Liu /* CONFIG_ADDRESS - PCI Config Address Register 1214e080313cSDave Liu */ 1215e080313cSDave Liu #define PCI_CONFIG_ADDRESS_EN 0x80000000 1216e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1217e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1218e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1219e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1220e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1221e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1222e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1223e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1224e080313cSDave Liu 1225e080313cSDave Liu /* POTAR - PCI Outbound Translation Address Register 1226e080313cSDave Liu */ 1227e080313cSDave Liu #define POTAR_TA_MASK 0x000fffff 1228e080313cSDave Liu 1229e080313cSDave Liu /* POBAR - PCI Outbound Base Address Register 1230e080313cSDave Liu */ 1231e080313cSDave Liu #define POBAR_BA_MASK 0x000fffff 1232e080313cSDave Liu 1233e080313cSDave Liu /* POCMR - PCI Outbound Comparision Mask Register 1234e080313cSDave Liu */ 1235e080313cSDave Liu #define POCMR_EN 0x80000000 1236e080313cSDave Liu #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1237e080313cSDave Liu #define POCMR_SE 0x20000000 /* streaming enable */ 1238e080313cSDave Liu #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1239e080313cSDave Liu #define POCMR_CM_MASK 0x000fffff 1240e080313cSDave Liu #define POCMR_CM_4G 0x00000000 1241e080313cSDave Liu #define POCMR_CM_2G 0x00080000 1242e080313cSDave Liu #define POCMR_CM_1G 0x000C0000 1243e080313cSDave Liu #define POCMR_CM_512M 0x000E0000 1244e080313cSDave Liu #define POCMR_CM_256M 0x000F0000 1245e080313cSDave Liu #define POCMR_CM_128M 0x000F8000 1246e080313cSDave Liu #define POCMR_CM_64M 0x000FC000 1247e080313cSDave Liu #define POCMR_CM_32M 0x000FE000 1248e080313cSDave Liu #define POCMR_CM_16M 0x000FF000 1249e080313cSDave Liu #define POCMR_CM_8M 0x000FF800 1250e080313cSDave Liu #define POCMR_CM_4M 0x000FFC00 1251e080313cSDave Liu #define POCMR_CM_2M 0x000FFE00 1252e080313cSDave Liu #define POCMR_CM_1M 0x000FFF00 1253e080313cSDave Liu #define POCMR_CM_512K 0x000FFF80 1254e080313cSDave Liu #define POCMR_CM_256K 0x000FFFC0 1255e080313cSDave Liu #define POCMR_CM_128K 0x000FFFE0 1256e080313cSDave Liu #define POCMR_CM_64K 0x000FFFF0 1257e080313cSDave Liu #define POCMR_CM_32K 0x000FFFF8 1258e080313cSDave Liu #define POCMR_CM_16K 0x000FFFFC 1259e080313cSDave Liu #define POCMR_CM_8K 0x000FFFFE 1260e080313cSDave Liu #define POCMR_CM_4K 0x000FFFFF 1261e080313cSDave Liu 1262e080313cSDave Liu /* PITAR - PCI Inbound Translation Address Register 1263e080313cSDave Liu */ 1264e080313cSDave Liu #define PITAR_TA_MASK 0x000fffff 1265e080313cSDave Liu 1266e080313cSDave Liu /* PIBAR - PCI Inbound Base/Extended Address Register 1267e080313cSDave Liu */ 1268e080313cSDave Liu #define PIBAR_MASK 0xffffffff 1269e080313cSDave Liu #define PIEBAR_EBA_MASK 0x000fffff 1270e080313cSDave Liu 1271e080313cSDave Liu /* PIWAR - PCI Inbound Windows Attributes Register 1272e080313cSDave Liu */ 1273e080313cSDave Liu #define PIWAR_EN 0x80000000 1274e080313cSDave Liu #define PIWAR_PF 0x20000000 1275e080313cSDave Liu #define PIWAR_RTT_MASK 0x000f0000 1276e080313cSDave Liu #define PIWAR_RTT_NO_SNOOP 0x00040000 1277e080313cSDave Liu #define PIWAR_RTT_SNOOP 0x00050000 1278e080313cSDave Liu #define PIWAR_WTT_MASK 0x0000f000 1279e080313cSDave Liu #define PIWAR_WTT_NO_SNOOP 0x00004000 1280e080313cSDave Liu #define PIWAR_WTT_SNOOP 0x00005000 1281e080313cSDave Liu #define PIWAR_IWS_MASK 0x0000003F 1282e080313cSDave Liu #define PIWAR_IWS_4K 0x0000000B 1283e080313cSDave Liu #define PIWAR_IWS_8K 0x0000000C 1284e080313cSDave Liu #define PIWAR_IWS_16K 0x0000000D 1285e080313cSDave Liu #define PIWAR_IWS_32K 0x0000000E 1286e080313cSDave Liu #define PIWAR_IWS_64K 0x0000000F 1287e080313cSDave Liu #define PIWAR_IWS_128K 0x00000010 1288e080313cSDave Liu #define PIWAR_IWS_256K 0x00000011 1289e080313cSDave Liu #define PIWAR_IWS_512K 0x00000012 1290e080313cSDave Liu #define PIWAR_IWS_1M 0x00000013 1291e080313cSDave Liu #define PIWAR_IWS_2M 0x00000014 1292e080313cSDave Liu #define PIWAR_IWS_4M 0x00000015 1293e080313cSDave Liu #define PIWAR_IWS_8M 0x00000016 1294e080313cSDave Liu #define PIWAR_IWS_16M 0x00000017 1295e080313cSDave Liu #define PIWAR_IWS_32M 0x00000018 1296e080313cSDave Liu #define PIWAR_IWS_64M 0x00000019 1297e080313cSDave Liu #define PIWAR_IWS_128M 0x0000001A 1298e080313cSDave Liu #define PIWAR_IWS_256M 0x0000001B 1299e080313cSDave Liu #define PIWAR_IWS_512M 0x0000001C 1300e080313cSDave Liu #define PIWAR_IWS_1G 0x0000001D 1301e080313cSDave Liu #define PIWAR_IWS_2G 0x0000001E 1302f6eda7f8SDave Liu 1303d87c57b2SScott Wood /* PMCCR1 - PCI Configuration Register 1 1304d87c57b2SScott Wood */ 1305d87c57b2SScott Wood #define PMCCR1_POWER_OFF 0x00000020 1306d87c57b2SScott Wood 1307d87c57b2SScott Wood /* FMR - Flash Mode Register 1308d87c57b2SScott Wood */ 1309d87c57b2SScott Wood #define FMR_CWTO 0x0000F000 1310d87c57b2SScott Wood #define FMR_CWTO_SHIFT 12 1311d87c57b2SScott Wood #define FMR_BOOT 0x00000800 1312d87c57b2SScott Wood #define FMR_ECCM 0x00000100 1313d87c57b2SScott Wood #define FMR_AL 0x00000030 1314d87c57b2SScott Wood #define FMR_AL_SHIFT 4 1315d87c57b2SScott Wood #define FMR_OP 0x00000003 1316d87c57b2SScott Wood #define FMR_OP_SHIFT 0 1317d87c57b2SScott Wood 1318d87c57b2SScott Wood /* FIR - Flash Instruction Register 1319d87c57b2SScott Wood */ 1320d87c57b2SScott Wood #define FIR_OP0 0xF0000000 1321d87c57b2SScott Wood #define FIR_OP0_SHIFT 28 1322d87c57b2SScott Wood #define FIR_OP1 0x0F000000 1323d87c57b2SScott Wood #define FIR_OP1_SHIFT 24 1324d87c57b2SScott Wood #define FIR_OP2 0x00F00000 1325d87c57b2SScott Wood #define FIR_OP2_SHIFT 20 1326d87c57b2SScott Wood #define FIR_OP3 0x000F0000 1327d87c57b2SScott Wood #define FIR_OP3_SHIFT 16 1328d87c57b2SScott Wood #define FIR_OP4 0x0000F000 1329d87c57b2SScott Wood #define FIR_OP4_SHIFT 12 1330d87c57b2SScott Wood #define FIR_OP5 0x00000F00 1331d87c57b2SScott Wood #define FIR_OP5_SHIFT 8 1332d87c57b2SScott Wood #define FIR_OP6 0x000000F0 1333d87c57b2SScott Wood #define FIR_OP6_SHIFT 4 1334d87c57b2SScott Wood #define FIR_OP7 0x0000000F 1335d87c57b2SScott Wood #define FIR_OP7_SHIFT 0 1336d87c57b2SScott Wood #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 1337d87c57b2SScott Wood #define FIR_OP_CA 0x1 /* Issue current column address */ 1338d87c57b2SScott Wood #define FIR_OP_PA 0x2 /* Issue current block+page address */ 1339d87c57b2SScott Wood #define FIR_OP_UA 0x3 /* Issue user defined address */ 1340d87c57b2SScott Wood #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 1341d87c57b2SScott Wood #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 1342d87c57b2SScott Wood #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 1343d87c57b2SScott Wood #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 1344d87c57b2SScott Wood #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 1345d87c57b2SScott Wood #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 1346d87c57b2SScott Wood #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 1347d87c57b2SScott Wood #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 1348d87c57b2SScott Wood #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 1349d87c57b2SScott Wood #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 1350d87c57b2SScott Wood #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 1351d87c57b2SScott Wood #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 1352d87c57b2SScott Wood 1353d87c57b2SScott Wood /* FCR - Flash Command Register 1354d87c57b2SScott Wood */ 1355d87c57b2SScott Wood #define FCR_CMD0 0xFF000000 1356d87c57b2SScott Wood #define FCR_CMD0_SHIFT 24 1357d87c57b2SScott Wood #define FCR_CMD1 0x00FF0000 1358d87c57b2SScott Wood #define FCR_CMD1_SHIFT 16 1359d87c57b2SScott Wood #define FCR_CMD2 0x0000FF00 1360d87c57b2SScott Wood #define FCR_CMD2_SHIFT 8 1361d87c57b2SScott Wood #define FCR_CMD3 0x000000FF 1362d87c57b2SScott Wood #define FCR_CMD3_SHIFT 0 1363d87c57b2SScott Wood 1364d87c57b2SScott Wood /* FBAR - Flash Block Address Register 1365d87c57b2SScott Wood */ 1366d87c57b2SScott Wood #define FBAR_BLK 0x00FFFFFF 1367d87c57b2SScott Wood 1368d87c57b2SScott Wood /* FPAR - Flash Page Address Register 1369d87c57b2SScott Wood */ 1370d87c57b2SScott Wood #define FPAR_SP_PI 0x00007C00 1371d87c57b2SScott Wood #define FPAR_SP_PI_SHIFT 10 1372d87c57b2SScott Wood #define FPAR_SP_MS 0x00000200 1373d87c57b2SScott Wood #define FPAR_SP_CI 0x000001FF 1374d87c57b2SScott Wood #define FPAR_SP_CI_SHIFT 0 1375d87c57b2SScott Wood #define FPAR_LP_PI 0x0003F000 1376d87c57b2SScott Wood #define FPAR_LP_PI_SHIFT 12 1377d87c57b2SScott Wood #define FPAR_LP_MS 0x00000800 1378d87c57b2SScott Wood #define FPAR_LP_CI 0x000007FF 1379d87c57b2SScott Wood #define FPAR_LP_CI_SHIFT 0 1380d87c57b2SScott Wood 1381d87c57b2SScott Wood /* LTESR - Transfer Error Status Register 1382d87c57b2SScott Wood */ 1383d87c57b2SScott Wood #define LTESR_BM 0x80000000 1384d87c57b2SScott Wood #define LTESR_FCT 0x40000000 1385d87c57b2SScott Wood #define LTESR_PAR 0x20000000 1386d87c57b2SScott Wood #define LTESR_WP 0x04000000 1387d87c57b2SScott Wood #define LTESR_ATMW 0x00800000 1388d87c57b2SScott Wood #define LTESR_ATMR 0x00400000 1389d87c57b2SScott Wood #define LTESR_CS 0x00080000 1390d87c57b2SScott Wood #define LTESR_CC 0x00000001 1391d87c57b2SScott Wood 1392*03051c3dSDave Liu /* DDRCDR - DDR Control Driver Register 1393d87c57b2SScott Wood */ 1394d87c57b2SScott Wood #define DDRCDR_EN 0x40000000 1395d87c57b2SScott Wood #define DDRCDR_PZ 0x3C000000 1396d87c57b2SScott Wood #define DDRCDR_PZ_MAXZ 0x00000000 1397d87c57b2SScott Wood #define DDRCDR_PZ_HIZ 0x20000000 1398d87c57b2SScott Wood #define DDRCDR_PZ_NOMZ 0x30000000 1399d87c57b2SScott Wood #define DDRCDR_PZ_LOZ 0x38000000 1400d87c57b2SScott Wood #define DDRCDR_PZ_MINZ 0x3C000000 1401d87c57b2SScott Wood #define DDRCDR_NZ 0x3C000000 1402d87c57b2SScott Wood #define DDRCDR_NZ_MAXZ 0x00000000 1403d87c57b2SScott Wood #define DDRCDR_NZ_HIZ 0x02000000 1404d87c57b2SScott Wood #define DDRCDR_NZ_NOMZ 0x03000000 1405d87c57b2SScott Wood #define DDRCDR_NZ_LOZ 0x03800000 1406d87c57b2SScott Wood #define DDRCDR_NZ_MINZ 0x03C00000 1407d87c57b2SScott Wood #define DDRCDR_ODT 0x00080000 1408d87c57b2SScott Wood #define DDRCDR_DDR_CFG 0x00040000 1409d87c57b2SScott Wood #define DDRCDR_M_ODR 0x00000002 1410d87c57b2SScott Wood #define DDRCDR_Q_DRN 0x00000001 1411d87c57b2SScott Wood 141249ea3b6eSScott Wood #ifndef __ASSEMBLY__ 141349ea3b6eSScott Wood struct pci_region; 141449ea3b6eSScott Wood void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 141549ea3b6eSScott Wood #endif 141649ea3b6eSScott Wood 1417f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 1418