1f046ccd1SEran Liberty /* 2f6eda7f8SDave Liu * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 3f046ccd1SEran Liberty * 4f046ccd1SEran Liberty * See file CREDITS for list of people who contributed to this 5f046ccd1SEran Liberty * project. 6f046ccd1SEran Liberty * 7f046ccd1SEran Liberty * This program is free software; you can redistribute it and/or 8f046ccd1SEran Liberty * modify it under the terms of the GNU General Public License as 9f046ccd1SEran Liberty * published by the Free Software Foundation; either version 2 of 10f046ccd1SEran Liberty * the License, or (at your option) any later version. 11f046ccd1SEran Liberty */ 12f046ccd1SEran Liberty 13f046ccd1SEran Liberty #ifndef __MPC83XX_H__ 14f046ccd1SEran Liberty #define __MPC83XX_H__ 15f046ccd1SEran Liberty 16f6eda7f8SDave Liu #include <config.h> 17f046ccd1SEran Liberty #if defined(CONFIG_E300) 18f046ccd1SEran Liberty #include <asm/e300.h> 19f046ccd1SEran Liberty #endif 20f046ccd1SEran Liberty 21e080313cSDave Liu /* MPC83xx cpu provide RCR register to do reset thing specially 22f046ccd1SEran Liberty */ 23f046ccd1SEran Liberty #define MPC83xx_RESET 24f046ccd1SEran Liberty 25e080313cSDave Liu /* System reset offset (PowerPC standard) 26f046ccd1SEran Liberty */ 27f046ccd1SEran Liberty #define EXC_OFF_SYS_RESET 0x0100 28*02032e8fSRafal Jaworowski #define _START_OFFSET EXC_OFF_SYS_RESET 29f046ccd1SEran Liberty 30e080313cSDave Liu /* IMMRBAR - Internal Memory Register Base Address 31f046ccd1SEran Liberty */ 32e080313cSDave Liu #define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ 33e080313cSDave Liu #define IMMRBAR 0x0000 /* Register offset to immr */ 34e080313cSDave Liu #define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ 35f046ccd1SEran Liberty #define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) 36f046ccd1SEran Liberty 37e080313cSDave Liu /* LAWBAR - Local Access Window Base Address Register 38f046ccd1SEran Liberty */ 39e080313cSDave Liu #define LBLAWBAR0 0x0020 /* Register offset to immr */ 40f046ccd1SEran Liberty #define LBLAWAR0 0x0024 41f046ccd1SEran Liberty #define LBLAWBAR1 0x0028 42f046ccd1SEran Liberty #define LBLAWAR1 0x002C 43f046ccd1SEran Liberty #define LBLAWBAR2 0x0030 44f046ccd1SEran Liberty #define LBLAWAR2 0x0034 45f046ccd1SEran Liberty #define LBLAWBAR3 0x0038 46f046ccd1SEran Liberty #define LBLAWAR3 0x003C 47e080313cSDave Liu #define LAWBAR_BAR 0xFFFFF000 /* Base address mask */ 48f046ccd1SEran Liberty 49e080313cSDave Liu /* SPRIDR - System Part and Revision ID Register 50f6eda7f8SDave Liu */ 51e080313cSDave Liu #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ 52e080313cSDave Liu #define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ 53e080313cSDave Liu 54f6eda7f8SDave Liu #define SPR_8349E_REV10 0x80300100 555f820439SDave Liu #define SPR_8349_REV10 0x80310100 565f820439SDave Liu #define SPR_8347E_REV10_TBGA 0x80320100 575f820439SDave Liu #define SPR_8347_REV10_TBGA 0x80330100 585f820439SDave Liu #define SPR_8347E_REV10_PBGA 0x80340100 595f820439SDave Liu #define SPR_8347_REV10_PBGA 0x80350100 605f820439SDave Liu #define SPR_8343E_REV10 0x80360100 615f820439SDave Liu #define SPR_8343_REV10 0x80370100 625f820439SDave Liu 63f6eda7f8SDave Liu #define SPR_8349E_REV11 0x80300101 645f820439SDave Liu #define SPR_8349_REV11 0x80310101 655f820439SDave Liu #define SPR_8347E_REV11_TBGA 0x80320101 665f820439SDave Liu #define SPR_8347_REV11_TBGA 0x80330101 675f820439SDave Liu #define SPR_8347E_REV11_PBGA 0x80340101 685f820439SDave Liu #define SPR_8347_REV11_PBGA 0x80350101 695f820439SDave Liu #define SPR_8343E_REV11 0x80360101 705f820439SDave Liu #define SPR_8343_REV11 0x80370101 715f820439SDave Liu 728d172c0fSXie Xiaobo #define SPR_8349E_REV31 0x80300300 738d172c0fSXie Xiaobo #define SPR_8349_REV31 0x80310300 748d172c0fSXie Xiaobo #define SPR_8347E_REV31_TBGA 0x80320300 758d172c0fSXie Xiaobo #define SPR_8347_REV31_TBGA 0x80330300 768d172c0fSXie Xiaobo #define SPR_8347E_REV31_PBGA 0x80340300 778d172c0fSXie Xiaobo #define SPR_8347_REV31_PBGA 0x80350300 788d172c0fSXie Xiaobo #define SPR_8343E_REV31 0x80360300 798d172c0fSXie Xiaobo #define SPR_8343_REV31 0x80370300 808d172c0fSXie Xiaobo 815f820439SDave Liu #define SPR_8360E_REV10 0x80480010 825f820439SDave Liu #define SPR_8360_REV10 0x80490010 835f820439SDave Liu #define SPR_8360E_REV11 0x80480011 845f820439SDave Liu #define SPR_8360_REV11 0x80490011 855f820439SDave Liu #define SPR_8360E_REV12 0x80480012 865f820439SDave Liu #define SPR_8360_REV12 0x80490012 87b110f40bSXie Xiaobo #define SPR_8360E_REV20 0x80480020 88b110f40bSXie Xiaobo #define SPR_8360_REV20 0x80490020 89f046ccd1SEran Liberty 9024c3aca3SDave Liu #define SPR_8323E_REV10 0x80620010 9124c3aca3SDave Liu #define SPR_8323_REV10 0x80630010 9224c3aca3SDave Liu #define SPR_8321E_REV10 0x80660010 9324c3aca3SDave Liu #define SPR_8321_REV10 0x80670010 9424c3aca3SDave Liu #define SPR_8323E_REV11 0x80620011 9524c3aca3SDave Liu #define SPR_8323_REV11 0x80630011 9624c3aca3SDave Liu #define SPR_8321E_REV11 0x80660011 9724c3aca3SDave Liu #define SPR_8321_REV11 0x80670011 9824c3aca3SDave Liu 99d87c57b2SScott Wood #define SPR_8311_REV10 0x80B30010 100d87c57b2SScott Wood #define SPR_8311E_REV10 0x80B20010 101d87c57b2SScott Wood #define SPR_8313_REV10 0x80B10010 102d87c57b2SScott Wood #define SPR_8313E_REV10 0x80B00010 103d87c57b2SScott Wood 104e080313cSDave Liu /* SPCR - System Priority Configuration Register 105f046ccd1SEran Liberty */ 106e080313cSDave Liu #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ 107e080313cSDave Liu #define SPCR_PCIHPE_SHIFT (31-3) 108e080313cSDave Liu #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ 109e080313cSDave Liu #define SPCR_PCIPR_SHIFT (31-7) 110e080313cSDave Liu #define SPCR_OPT 0x00800000 /* Optimize */ 111e080313cSDave Liu #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ 112e080313cSDave Liu #define SPCR_TBEN_SHIFT (31-9) 113e080313cSDave Liu #define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ 114e080313cSDave Liu #define SPCR_COREPR_SHIFT (31-11) 115e080313cSDave Liu 1163e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 117e080313cSDave Liu /* SPCR bits - MPC8349 specific */ 118e080313cSDave Liu #define SPCR_TSEC1DP 0x00003000 /* TSEC1 data priority */ 119e080313cSDave Liu #define SPCR_TSEC1DP_SHIFT (31-19) 120e080313cSDave Liu #define SPCR_TSEC1BDP 0x00000C00 /* TSEC1 buffer descriptor priority */ 121e080313cSDave Liu #define SPCR_TSEC1BDP_SHIFT (31-21) 122e080313cSDave Liu #define SPCR_TSEC1EP 0x00000300 /* TSEC1 emergency priority */ 123e080313cSDave Liu #define SPCR_TSEC1EP_SHIFT (31-23) 124e080313cSDave Liu #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority */ 125e080313cSDave Liu #define SPCR_TSEC2DP_SHIFT (31-27) 126e080313cSDave Liu #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority */ 127e080313cSDave Liu #define SPCR_TSEC2BDP_SHIFT (31-29) 128e080313cSDave Liu #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority */ 129e080313cSDave Liu #define SPCR_TSEC2EP_SHIFT (31-31) 130d87c57b2SScott Wood 131d87c57b2SScott Wood #elif defined(CONFIG_MPC831X) 132d87c57b2SScott Wood /* SPCR bits - MPC831x specific */ 133d87c57b2SScott Wood #define SPCR_TSECDP 0x00003000 /* TSEC data priority */ 134d87c57b2SScott Wood #define SPCR_TSECDP_SHIFT (31-19) 135d87c57b2SScott Wood #define SPCR_TSECEP 0x00000C00 /* TSEC emergency priority */ 136d87c57b2SScott Wood #define SPCR_TSECEP_SHIFT (31-21) 137d87c57b2SScott Wood #define SPCR_TSECBDP 0x00000300 /* TSEC buffer descriptor priority */ 138d87c57b2SScott Wood #define SPCR_TSECBDP_SHIFT (31-23) 139e080313cSDave Liu #endif 140e080313cSDave Liu 141e080313cSDave Liu /* SICRL/H - System I/O Configuration Register Low/High 142e080313cSDave Liu */ 1433e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 144e080313cSDave Liu /* SICRL bits - MPC8349 specific */ 145e080313cSDave Liu #define SICRL_LDP_A 0x80000000 146e080313cSDave Liu #define SICRL_USB1 0x40000000 147e080313cSDave Liu #define SICRL_USB0 0x20000000 148e080313cSDave Liu #define SICRL_UART 0x0C000000 149e080313cSDave Liu #define SICRL_GPIO1_A 0x02000000 150e080313cSDave Liu #define SICRL_GPIO1_B 0x01000000 151e080313cSDave Liu #define SICRL_GPIO1_C 0x00800000 152e080313cSDave Liu #define SICRL_GPIO1_D 0x00400000 153e080313cSDave Liu #define SICRL_GPIO1_E 0x00200000 154e080313cSDave Liu #define SICRL_GPIO1_F 0x00180000 155e080313cSDave Liu #define SICRL_GPIO1_G 0x00040000 156e080313cSDave Liu #define SICRL_GPIO1_H 0x00020000 157e080313cSDave Liu #define SICRL_GPIO1_I 0x00010000 158e080313cSDave Liu #define SICRL_GPIO1_J 0x00008000 159e080313cSDave Liu #define SICRL_GPIO1_K 0x00004000 160e080313cSDave Liu #define SICRL_GPIO1_L 0x00003000 161e080313cSDave Liu 162e080313cSDave Liu /* SICRH bits - MPC8349 specific */ 163e080313cSDave Liu #define SICRH_DDR 0x80000000 164e080313cSDave Liu #define SICRH_TSEC1_A 0x10000000 165e080313cSDave Liu #define SICRH_TSEC1_B 0x08000000 166e080313cSDave Liu #define SICRH_TSEC1_C 0x04000000 167e080313cSDave Liu #define SICRH_TSEC1_D 0x02000000 168e080313cSDave Liu #define SICRH_TSEC1_E 0x01000000 169e080313cSDave Liu #define SICRH_TSEC1_F 0x00800000 170e080313cSDave Liu #define SICRH_TSEC2_A 0x00400000 171e080313cSDave Liu #define SICRH_TSEC2_B 0x00200000 172e080313cSDave Liu #define SICRH_TSEC2_C 0x00100000 173e080313cSDave Liu #define SICRH_TSEC2_D 0x00080000 174e080313cSDave Liu #define SICRH_TSEC2_E 0x00040000 175e080313cSDave Liu #define SICRH_TSEC2_F 0x00020000 176e080313cSDave Liu #define SICRH_TSEC2_G 0x00010000 177e080313cSDave Liu #define SICRH_TSEC2_H 0x00008000 178e080313cSDave Liu #define SICRH_GPIO2_A 0x00004000 179e080313cSDave Liu #define SICRH_GPIO2_B 0x00002000 180e080313cSDave Liu #define SICRH_GPIO2_C 0x00001000 181e080313cSDave Liu #define SICRH_GPIO2_D 0x00000800 182e080313cSDave Liu #define SICRH_GPIO2_E 0x00000400 183e080313cSDave Liu #define SICRH_GPIO2_F 0x00000200 184e080313cSDave Liu #define SICRH_GPIO2_G 0x00000180 185e080313cSDave Liu #define SICRH_GPIO2_H 0x00000060 186e080313cSDave Liu #define SICRH_TSOBI1 0x00000002 187e080313cSDave Liu #define SICRH_TSOBI2 0x00000001 188e080313cSDave Liu 189e080313cSDave Liu #elif defined(CONFIG_MPC8360) 190e080313cSDave Liu /* SICRL bits - MPC8360 specific */ 191e080313cSDave Liu #define SICRL_LDP_A 0xC0000000 192e080313cSDave Liu #define SICRL_LCLK_1 0x10000000 193e080313cSDave Liu #define SICRL_LCLK_2 0x08000000 194e080313cSDave Liu #define SICRL_SRCID_A 0x03000000 195e080313cSDave Liu #define SICRL_IRQ_CKSTP_A 0x00C00000 196e080313cSDave Liu 197e080313cSDave Liu /* SICRH bits - MPC8360 specific */ 198e080313cSDave Liu #define SICRH_DDR 0x80000000 199e080313cSDave Liu #define SICRH_SECONDARY_DDR 0x40000000 200e080313cSDave Liu #define SICRH_SDDROE 0x20000000 201e080313cSDave Liu #define SICRH_IRQ3 0x10000000 202e080313cSDave Liu #define SICRH_UC1EOBI 0x00000004 203e080313cSDave Liu #define SICRH_UC2E1OBI 0x00000002 204e080313cSDave Liu #define SICRH_UC2E2OBI 0x00000001 20524c3aca3SDave Liu 20624c3aca3SDave Liu #elif defined(CONFIG_MPC832X) 20724c3aca3SDave Liu /* SICRL bits - MPC832X specific */ 20824c3aca3SDave Liu #define SICRL_LDP_LCS_A 0x80000000 20924c3aca3SDave Liu #define SICRL_IRQ_CKS 0x20000000 21024c3aca3SDave Liu #define SICRL_PCI_MSRC 0x10000000 21124c3aca3SDave Liu #define SICRL_URT_CTPR 0x06000000 21224c3aca3SDave Liu #define SICRL_IRQ_CTPR 0x00C00000 213d87c57b2SScott Wood 214d87c57b2SScott Wood #elif defined(CONFIG_MPC831X) 215d87c57b2SScott Wood /* SICRL bits - MPC831x specific */ 216d87c57b2SScott Wood #define SICRL_LBC 0x30000000 217d87c57b2SScott Wood #define SICRL_UART 0x0C000000 218d87c57b2SScott Wood #define SICRL_SPI_A 0x03000000 219d87c57b2SScott Wood #define SICRL_SPI_B 0x00C00000 220d87c57b2SScott Wood #define SICRL_SPI_C 0x00300000 221d87c57b2SScott Wood #define SICRL_SPI_D 0x000C0000 222d87c57b2SScott Wood #define SICRL_USBDR 0x00000C00 223d87c57b2SScott Wood #define SICRL_ETSEC1_A 0x0000000C 224d87c57b2SScott Wood #define SICRL_ETSEC2_A 0x00000003 225d87c57b2SScott Wood 226d87c57b2SScott Wood /* SICRH bits - MPC831x specific */ 227d87c57b2SScott Wood #define SICRH_INTR_A 0x02000000 228d87c57b2SScott Wood #define SICRH_INTR_B 0x00C00000 229d87c57b2SScott Wood #define SICRH_IIC 0x00300000 230d87c57b2SScott Wood #define SICRH_ETSEC2_B 0x000C0000 231d87c57b2SScott Wood #define SICRH_ETSEC2_C 0x00030000 232d87c57b2SScott Wood #define SICRH_ETSEC2_D 0x0000C000 233d87c57b2SScott Wood #define SICRH_ETSEC2_E 0x00003000 234d87c57b2SScott Wood #define SICRH_ETSEC2_F 0x00000C00 235d87c57b2SScott Wood #define SICRH_ETSEC2_G 0x00000300 236d87c57b2SScott Wood #define SICRH_ETSEC1_B 0x00000080 237d87c57b2SScott Wood #define SICRH_ETSEC1_C 0x00000060 238d87c57b2SScott Wood #define SICRH_GTX1_DLY 0x00000008 239d87c57b2SScott Wood #define SICRH_GTX2_DLY 0x00000004 240d87c57b2SScott Wood #define SICRH_TSOBI1 0x00000002 241d87c57b2SScott Wood #define SICRH_TSOBI2 0x00000001 242d87c57b2SScott Wood 243e080313cSDave Liu #endif 244e080313cSDave Liu 245e080313cSDave Liu /* SWCRR - System Watchdog Control Register 246e080313cSDave Liu */ 247e080313cSDave Liu #define SWCRR 0x0204 /* Register offset to immr */ 248e080313cSDave Liu #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ 249e080313cSDave Liu #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ 250e080313cSDave Liu #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ 251e080313cSDave Liu #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ 252e080313cSDave Liu #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) 253e080313cSDave Liu 254e080313cSDave Liu /* SWCNR - System Watchdog Counter Register 255e080313cSDave Liu */ 256e080313cSDave Liu #define SWCNR 0x0208 /* Register offset to immr */ 257e080313cSDave Liu #define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ 258e080313cSDave Liu #define SWCNR_RES ~(SWCNR_SWCN) 259e080313cSDave Liu 260e080313cSDave Liu /* SWSRR - System Watchdog Service Register 261e080313cSDave Liu */ 262e080313cSDave Liu #define SWSRR 0x020E /* Register offset to immr */ 263e080313cSDave Liu 264e080313cSDave Liu /* ACR - Arbiter Configuration Register 265e080313cSDave Liu */ 266e080313cSDave Liu #define ACR_COREDIS 0x10000000 /* Core disable */ 267e080313cSDave Liu #define ACR_COREDIS_SHIFT (31-7) 268e080313cSDave Liu #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ 269e080313cSDave Liu #define ACR_PIPE_DEP_SHIFT (31-15) 270e080313cSDave Liu #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ 271e080313cSDave Liu #define ACR_PCI_RPTCNT_SHIFT (31-19) 272e080313cSDave Liu #define ACR_RPTCNT 0x00000700 /* Repeat count */ 273e080313cSDave Liu #define ACR_RPTCNT_SHIFT (31-23) 274e080313cSDave Liu #define ACR_APARK 0x00000030 /* Address parking */ 275e080313cSDave Liu #define ACR_APARK_SHIFT (31-27) 276e080313cSDave Liu #define ACR_PARKM 0x0000000F /* Parking master */ 277e080313cSDave Liu #define ACR_PARKM_SHIFT (31-31) 278e080313cSDave Liu 279e080313cSDave Liu /* ATR - Arbiter Timers Register 280e080313cSDave Liu */ 281e080313cSDave Liu #define ATR_DTO 0x00FF0000 /* Data time out */ 282e080313cSDave Liu #define ATR_ATO 0x000000FF /* Address time out */ 283e080313cSDave Liu 284e080313cSDave Liu /* AER - Arbiter Event Register 285e080313cSDave Liu */ 286e080313cSDave Liu #define AER_ETEA 0x00000020 /* Transfer error */ 287e080313cSDave Liu #define AER_RES 0x00000010 /* Reserved transfer type */ 288e080313cSDave Liu #define AER_ECW 0x00000008 /* External control word transfer type */ 289e080313cSDave Liu #define AER_AO 0x00000004 /* Address Only transfer type */ 290e080313cSDave Liu #define AER_DTO 0x00000002 /* Data time out */ 291e080313cSDave Liu #define AER_ATO 0x00000001 /* Address time out */ 292e080313cSDave Liu 293e080313cSDave Liu /* AEATR - Arbiter Event Address Register 294e080313cSDave Liu */ 295e080313cSDave Liu #define AEATR_EVENT 0x07000000 /* Event type */ 296e080313cSDave Liu #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ 297e080313cSDave Liu #define AEATR_TBST 0x00000800 /* Transfer burst */ 298e080313cSDave Liu #define AEATR_TSIZE 0x00000700 /* Transfer Size */ 299e080313cSDave Liu #define AEATR_TTYPE 0x0000001F /* Transfer Type */ 300e080313cSDave Liu 301e080313cSDave Liu /* HRCWL - Hard Reset Configuration Word Low 302e080313cSDave Liu */ 303e080313cSDave Liu #define HRCWL_LBIUCM 0x80000000 304e080313cSDave Liu #define HRCWL_LBIUCM_SHIFT 31 305e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 306e080313cSDave Liu #define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 307e080313cSDave Liu 308e080313cSDave Liu #define HRCWL_DDRCM 0x40000000 309e080313cSDave Liu #define HRCWL_DDRCM_SHIFT 30 310e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 311e080313cSDave Liu #define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 312e080313cSDave Liu 313e080313cSDave Liu #define HRCWL_SPMF 0x0f000000 314e080313cSDave Liu #define HRCWL_SPMF_SHIFT 24 315e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 316e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 317e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 318e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 319e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 320e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 321e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 322e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 323e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 324e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 325e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 326e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 327e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 328e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 329e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 330e080313cSDave Liu #define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 331e080313cSDave Liu 332e080313cSDave Liu #define HRCWL_VCO_BYPASS 0x00000000 333e080313cSDave Liu #define HRCWL_VCO_1X2 0x00000000 334e080313cSDave Liu #define HRCWL_VCO_1X4 0x00200000 335e080313cSDave Liu #define HRCWL_VCO_1X8 0x00400000 336e080313cSDave Liu 337e080313cSDave Liu #define HRCWL_COREPLL 0x007F0000 338e080313cSDave Liu #define HRCWL_COREPLL_SHIFT 16 339e080313cSDave Liu #define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 340e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1X1 0x00020000 341e080313cSDave Liu #define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 342e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2X1 0x00040000 343e080313cSDave Liu #define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 344e080313cSDave Liu #define HRCWL_CORE_TO_CSB_3X1 0x00060000 345e080313cSDave Liu 34624c3aca3SDave Liu #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 347e080313cSDave Liu #define HRCWL_CEVCOD 0x000000C0 348e080313cSDave Liu #define HRCWL_CEVCOD_SHIFT 6 349e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_4 0x00000000 350e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_8 0x00000040 351e080313cSDave Liu #define HRCWL_CE_PLL_VCO_DIV_2 0x00000080 352e080313cSDave Liu 353e080313cSDave Liu #define HRCWL_CEPDF 0x00000020 354e080313cSDave Liu #define HRCWL_CEPDF_SHIFT 5 355e080313cSDave Liu #define HRCWL_CE_PLL_DIV_1X1 0x00000000 356e080313cSDave Liu #define HRCWL_CE_PLL_DIV_2X1 0x00000020 357e080313cSDave Liu 358e080313cSDave Liu #define HRCWL_CEPMF 0x0000001F 359e080313cSDave Liu #define HRCWL_CEPMF_SHIFT 0 360e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16_ 0x00000000 361e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X2 0x00000002 362e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X3 0x00000003 363e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X4 0x00000004 364e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X5 0x00000005 365e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X6 0x00000006 366e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X7 0x00000007 367e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X8 0x00000008 368e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X9 0x00000009 369e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X10 0x0000000A 370e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X11 0x0000000B 371e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X12 0x0000000C 372e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X13 0x0000000D 373e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X14 0x0000000E 374e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X15 0x0000000F 375e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X16 0x00000010 376e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X17 0x00000011 377e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X18 0x00000012 378e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X19 0x00000013 379e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X20 0x00000014 380e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X21 0x00000015 381e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X22 0x00000016 382e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X23 0x00000017 383e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X24 0x00000018 384e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X25 0x00000019 385e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X26 0x0000001A 386e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X27 0x0000001B 387e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X28 0x0000001C 388e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X29 0x0000001D 389e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X30 0x0000001E 390e080313cSDave Liu #define HRCWL_CE_TO_PLL_1X31 0x0000001F 391e080313cSDave Liu #endif 392e080313cSDave Liu 393e080313cSDave Liu /* HRCWH - Hardware Reset Configuration Word High 394e080313cSDave Liu */ 395e080313cSDave Liu #define HRCWH_PCI_HOST 0x80000000 396e080313cSDave Liu #define HRCWH_PCI_HOST_SHIFT 31 397e080313cSDave Liu #define HRCWH_PCI_AGENT 0x00000000 398e080313cSDave Liu 3993e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 400e080313cSDave Liu #define HRCWH_32_BIT_PCI 0x00000000 401e080313cSDave Liu #define HRCWH_64_BIT_PCI 0x40000000 402e080313cSDave Liu #endif 403e080313cSDave Liu 404e080313cSDave Liu #define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 405e080313cSDave Liu #define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 406e080313cSDave Liu 407e080313cSDave Liu #define HRCWH_PCI_ARBITER_DISABLE 0x00000000 408e080313cSDave Liu #define HRCWH_PCI_ARBITER_ENABLE 0x20000000 409e080313cSDave Liu 4103e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 411e080313cSDave Liu #define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 412e080313cSDave Liu #define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 413e080313cSDave Liu 414e080313cSDave Liu #elif defined(CONFIG_MPC8360) 415e080313cSDave Liu #define HRCWH_PCICKDRV_DISABLE 0x00000000 416e080313cSDave Liu #define HRCWH_PCICKDRV_ENABLE 0x10000000 417e080313cSDave Liu #endif 418e080313cSDave Liu 419e080313cSDave Liu #define HRCWH_CORE_DISABLE 0x08000000 420e080313cSDave Liu #define HRCWH_CORE_ENABLE 0x00000000 421e080313cSDave Liu 422e080313cSDave Liu #define HRCWH_FROM_0X00000100 0x00000000 423e080313cSDave Liu #define HRCWH_FROM_0XFFF00100 0x04000000 424e080313cSDave Liu 425e080313cSDave Liu #define HRCWH_BOOTSEQ_DISABLE 0x00000000 426e080313cSDave Liu #define HRCWH_BOOTSEQ_NORMAL 0x01000000 427e080313cSDave Liu #define HRCWH_BOOTSEQ_EXTENDED 0x02000000 428e080313cSDave Liu 429e080313cSDave Liu #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 430e080313cSDave Liu #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 431e080313cSDave Liu 432e080313cSDave Liu #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 433e080313cSDave Liu #define HRCWH_ROM_LOC_PCI1 0x00100000 4343e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 435e080313cSDave Liu #define HRCWH_ROM_LOC_PCI2 0x00200000 436e080313cSDave Liu #endif 437e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 438e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 439e080313cSDave Liu #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 440e080313cSDave Liu 441d87c57b2SScott Wood #if defined(CONFIG_MPC831X) 442d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 443d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 444d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 445d87c57b2SScott Wood #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 446d87c57b2SScott Wood 447d87c57b2SScott Wood #define HRCWH_RL_EXT_LEGACY 0x00000000 448d87c57b2SScott Wood #define HRCWH_RL_EXT_NAND 0x00040000 449d87c57b2SScott Wood 450d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_MII 0x00000000 451d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RMII 0x00002000 452d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RGMII 0x00006000 453d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_RTBI 0x0000A000 454d87c57b2SScott Wood #define HRCWH_TSEC1M_IN_SGMII 0x0000C000 455d87c57b2SScott Wood 456d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_MII 0x00000000 457d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RMII 0x00000400 458d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RGMII 0x00000C00 459d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_RTBI 0x00001400 460d87c57b2SScott Wood #define HRCWH_TSEC2M_IN_SGMII 0x00001800 461d87c57b2SScott Wood #endif 462d87c57b2SScott Wood 4633e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 464e080313cSDave Liu #define HRCWH_TSEC1M_IN_RGMII 0x00000000 465e080313cSDave Liu #define HRCWH_TSEC1M_IN_RTBI 0x00004000 466e080313cSDave Liu #define HRCWH_TSEC1M_IN_GMII 0x00008000 467e080313cSDave Liu #define HRCWH_TSEC1M_IN_TBI 0x0000C000 468e080313cSDave Liu #define HRCWH_TSEC2M_IN_RGMII 0x00000000 469e080313cSDave Liu #define HRCWH_TSEC2M_IN_RTBI 0x00001000 470e080313cSDave Liu #define HRCWH_TSEC2M_IN_GMII 0x00002000 471e080313cSDave Liu #define HRCWH_TSEC2M_IN_TBI 0x00003000 472e080313cSDave Liu #endif 473e080313cSDave Liu 474e080313cSDave Liu #if defined(CONFIG_MPC8360) 475e080313cSDave Liu #define HRCWH_SECONDARY_DDR_DISABLE 0x00000000 476e080313cSDave Liu #define HRCWH_SECONDARY_DDR_ENABLE 0x00000010 477e080313cSDave Liu #endif 478e080313cSDave Liu 479e080313cSDave Liu #define HRCWH_BIG_ENDIAN 0x00000000 480e080313cSDave Liu #define HRCWH_LITTLE_ENDIAN 0x00000008 481e080313cSDave Liu 482e080313cSDave Liu #define HRCWH_LALE_NORMAL 0x00000000 483e080313cSDave Liu #define HRCWH_LALE_EARLY 0x00000004 484e080313cSDave Liu 485e080313cSDave Liu #define HRCWH_LDP_SET 0x00000000 486e080313cSDave Liu #define HRCWH_LDP_CLEAR 0x00000002 487e080313cSDave Liu 488e080313cSDave Liu /* RSR - Reset Status Register 489e080313cSDave Liu */ 490e080313cSDave Liu #define RSR_RSTSRC 0xE0000000 /* Reset source */ 491e080313cSDave Liu #define RSR_RSTSRC_SHIFT 29 492e080313cSDave Liu #define RSR_BSF 0x00010000 /* Boot seq. fail */ 493e080313cSDave Liu #define RSR_BSF_SHIFT 16 494e080313cSDave Liu #define RSR_SWSR 0x00002000 /* software soft reset */ 495e080313cSDave Liu #define RSR_SWSR_SHIFT 13 496e080313cSDave Liu #define RSR_SWHR 0x00001000 /* software hard reset */ 497e080313cSDave Liu #define RSR_SWHR_SHIFT 12 498e080313cSDave Liu #define RSR_JHRS 0x00000200 /* jtag hreset */ 499e080313cSDave Liu #define RSR_JHRS_SHIFT 9 500e080313cSDave Liu #define RSR_JSRS 0x00000100 /* jtag sreset status */ 501e080313cSDave Liu #define RSR_JSRS_SHIFT 8 502e080313cSDave Liu #define RSR_CSHR 0x00000010 /* checkstop reset status */ 503e080313cSDave Liu #define RSR_CSHR_SHIFT 4 504e080313cSDave Liu #define RSR_SWRS 0x00000008 /* software watchdog reset status */ 505e080313cSDave Liu #define RSR_SWRS_SHIFT 3 506e080313cSDave Liu #define RSR_BMRS 0x00000004 /* bus monitop reset status */ 507e080313cSDave Liu #define RSR_BMRS_SHIFT 2 508e080313cSDave Liu #define RSR_SRS 0x00000002 /* soft reset status */ 509e080313cSDave Liu #define RSR_SRS_SHIFT 1 510e080313cSDave Liu #define RSR_HRS 0x00000001 /* hard reset status */ 511e080313cSDave Liu #define RSR_HRS_SHIFT 0 512e080313cSDave Liu #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR |\ 513e080313cSDave Liu RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ 514e080313cSDave Liu RSR_BMRS | RSR_SRS | RSR_HRS) 515e080313cSDave Liu /* RMR - Reset Mode Register 516e080313cSDave Liu */ 517e080313cSDave Liu #define RMR_CSRE 0x00000001 /* checkstop reset enable */ 518e080313cSDave Liu #define RMR_CSRE_SHIFT 0 519e080313cSDave Liu #define RMR_RES ~(RMR_CSRE) 520e080313cSDave Liu 521e080313cSDave Liu /* RCR - Reset Control Register 522e080313cSDave Liu */ 523e080313cSDave Liu #define RCR_SWHR 0x00000002 /* software hard reset */ 524e080313cSDave Liu #define RCR_SWSR 0x00000001 /* software soft reset */ 525e080313cSDave Liu #define RCR_RES ~(RCR_SWHR | RCR_SWSR) 526e080313cSDave Liu 527e080313cSDave Liu /* RCER - Reset Control Enable Register 528e080313cSDave Liu */ 529e080313cSDave Liu #define RCER_CRE 0x00000001 /* software hard reset */ 530e080313cSDave Liu #define RCER_RES ~(RCER_CRE) 531e080313cSDave Liu 532e080313cSDave Liu /* SPMR - System PLL Mode Register 533e080313cSDave Liu */ 534e080313cSDave Liu #define SPMR_LBIUCM 0x80000000 535e080313cSDave Liu #define SPMR_DDRCM 0x40000000 536e080313cSDave Liu #define SPMR_SPMF 0x0F000000 537e080313cSDave Liu #define SPMR_CKID 0x00800000 538e080313cSDave Liu #define SPMR_CKID_SHIFT 23 539e080313cSDave Liu #define SPMR_COREPLL 0x007F0000 540e080313cSDave Liu #define SPMR_CEVCOD 0x000000C0 541e080313cSDave Liu #define SPMR_CEPDF 0x00000020 542e080313cSDave Liu #define SPMR_CEPMF 0x0000001F 543e080313cSDave Liu 544e080313cSDave Liu /* OCCR - Output Clock Control Register 545e080313cSDave Liu */ 546e080313cSDave Liu #define OCCR_PCICOE0 0x80000000 547e080313cSDave Liu #define OCCR_PCICOE1 0x40000000 548e080313cSDave Liu #define OCCR_PCICOE2 0x20000000 549e080313cSDave Liu #define OCCR_PCICOE3 0x10000000 550e080313cSDave Liu #define OCCR_PCICOE4 0x08000000 551e080313cSDave Liu #define OCCR_PCICOE5 0x04000000 552e080313cSDave Liu #define OCCR_PCICOE6 0x02000000 553e080313cSDave Liu #define OCCR_PCICOE7 0x01000000 554e080313cSDave Liu #define OCCR_PCICD0 0x00800000 555e080313cSDave Liu #define OCCR_PCICD1 0x00400000 556e080313cSDave Liu #define OCCR_PCICD2 0x00200000 557e080313cSDave Liu #define OCCR_PCICD3 0x00100000 558e080313cSDave Liu #define OCCR_PCICD4 0x00080000 559e080313cSDave Liu #define OCCR_PCICD5 0x00040000 560e080313cSDave Liu #define OCCR_PCICD6 0x00020000 561e080313cSDave Liu #define OCCR_PCICD7 0x00010000 562e080313cSDave Liu #define OCCR_PCI1CR 0x00000002 563e080313cSDave Liu #define OCCR_PCI2CR 0x00000001 564e080313cSDave Liu #define OCCR_PCICR OCCR_PCI1CR 565e080313cSDave Liu 566e080313cSDave Liu /* SCCR - System Clock Control Register 567e080313cSDave Liu */ 568e080313cSDave Liu #define SCCR_ENCCM 0x03000000 569e080313cSDave Liu #define SCCR_ENCCM_SHIFT 24 570e080313cSDave Liu #define SCCR_ENCCM_0 0x00000000 571e080313cSDave Liu #define SCCR_ENCCM_1 0x01000000 572e080313cSDave Liu #define SCCR_ENCCM_2 0x02000000 573e080313cSDave Liu #define SCCR_ENCCM_3 0x03000000 574e080313cSDave Liu 575e080313cSDave Liu #define SCCR_PCICM 0x00010000 576e080313cSDave Liu #define SCCR_PCICM_SHIFT 16 577e080313cSDave Liu 578e080313cSDave Liu /* SCCR bits - MPC8349 specific */ 5794feab4deSKumar Gala #ifdef CONFIG_MPC834X 580e080313cSDave Liu #define SCCR_TSEC1CM 0xc0000000 581e080313cSDave Liu #define SCCR_TSEC1CM_SHIFT 30 582e080313cSDave Liu #define SCCR_TSEC1CM_0 0x00000000 583e080313cSDave Liu #define SCCR_TSEC1CM_1 0x40000000 584e080313cSDave Liu #define SCCR_TSEC1CM_2 0x80000000 585e080313cSDave Liu #define SCCR_TSEC1CM_3 0xC0000000 586e080313cSDave Liu 587e080313cSDave Liu #define SCCR_TSEC2CM 0x30000000 588e080313cSDave Liu #define SCCR_TSEC2CM_SHIFT 28 589e080313cSDave Liu #define SCCR_TSEC2CM_0 0x00000000 590e080313cSDave Liu #define SCCR_TSEC2CM_1 0x10000000 591e080313cSDave Liu #define SCCR_TSEC2CM_2 0x20000000 592e080313cSDave Liu #define SCCR_TSEC2CM_3 0x30000000 593d87c57b2SScott Wood 594d87c57b2SScott Wood #elif defined(CONFIG_MPC831X) 595d87c57b2SScott Wood /* TSEC1 bits are for TSEC2 as well */ 596d87c57b2SScott Wood #define SCCR_TSEC1CM 0xc0000000 597d87c57b2SScott Wood #define SCCR_TSEC1CM_SHIFT 30 598d87c57b2SScott Wood #define SCCR_TSEC1CM_1 0x40000000 599d87c57b2SScott Wood #define SCCR_TSEC1CM_2 0x80000000 600d87c57b2SScott Wood #define SCCR_TSEC1CM_3 0xC0000000 601d87c57b2SScott Wood 602d87c57b2SScott Wood #define SCCR_TSEC1ON 0x20000000 603d87c57b2SScott Wood #define SCCR_TSEC2ON 0x10000000 604d87c57b2SScott Wood 6054feab4deSKumar Gala #endif 606e080313cSDave Liu 607e080313cSDave Liu #define SCCR_USBMPHCM 0x00c00000 608e080313cSDave Liu #define SCCR_USBMPHCM_SHIFT 22 609e080313cSDave Liu #define SCCR_USBDRCM 0x00300000 610e080313cSDave Liu #define SCCR_USBDRCM_SHIFT 20 611e080313cSDave Liu 612e080313cSDave Liu #define SCCR_USBCM_0 0x00000000 613e080313cSDave Liu #define SCCR_USBCM_1 0x00500000 614e080313cSDave Liu #define SCCR_USBCM_2 0x00A00000 615e080313cSDave Liu #define SCCR_USBCM_3 0x00F00000 616e080313cSDave Liu 617e080313cSDave Liu /* CSn_BDNS - Chip Select memory Bounds Register 618e080313cSDave Liu */ 619e080313cSDave Liu #define CSBNDS_SA 0x00FF0000 620e080313cSDave Liu #define CSBNDS_SA_SHIFT 8 621e080313cSDave Liu #define CSBNDS_EA 0x000000FF 622e080313cSDave Liu #define CSBNDS_EA_SHIFT 24 623e080313cSDave Liu 624e080313cSDave Liu /* CSn_CONFIG - Chip Select Configuration Register 625e080313cSDave Liu */ 626e080313cSDave Liu #define CSCONFIG_EN 0x80000000 627e080313cSDave Liu #define CSCONFIG_AP 0x00800000 628e080313cSDave Liu #define CSCONFIG_ROW_BIT 0x00000700 629e080313cSDave Liu #define CSCONFIG_ROW_BIT_12 0x00000000 630e080313cSDave Liu #define CSCONFIG_ROW_BIT_13 0x00000100 631e080313cSDave Liu #define CSCONFIG_ROW_BIT_14 0x00000200 632e080313cSDave Liu #define CSCONFIG_COL_BIT 0x00000007 633e080313cSDave Liu #define CSCONFIG_COL_BIT_8 0x00000000 634e080313cSDave Liu #define CSCONFIG_COL_BIT_9 0x00000001 635e080313cSDave Liu #define CSCONFIG_COL_BIT_10 0x00000002 636e080313cSDave Liu #define CSCONFIG_COL_BIT_11 0x00000003 637e080313cSDave Liu 638d87c57b2SScott Wood /* TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 639d87c57b2SScott Wood */ 640d87c57b2SScott Wood #define TIMING_CFG0_RWT 0xC0000000 641d87c57b2SScott Wood #define TIMING_CFG0_RWT_SHIFT 30 642d87c57b2SScott Wood #define TIMING_CFG0_WRT 0x30000000 643d87c57b2SScott Wood #define TIMING_CFG0_WRT_SHIFT 28 644d87c57b2SScott Wood #define TIMING_CFG0_RRT 0x0C000000 645d87c57b2SScott Wood #define TIMING_CFG0_RRT_SHIFT 26 646d87c57b2SScott Wood #define TIMING_CFG0_WWT 0x03000000 647d87c57b2SScott Wood #define TIMING_CFG0_WWT_SHIFT 24 648d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT 0x00700000 649d87c57b2SScott Wood #define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20 650d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT 0x00070000 651d87c57b2SScott Wood #define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16 652d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT 0x00000F00 653d87c57b2SScott Wood #define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8 654d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC 0x00000F00 655d87c57b2SScott Wood #define TIMING_CFG0_MRS_CYC_SHIFT 0 656d87c57b2SScott Wood 657e080313cSDave Liu /* TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 658e080313cSDave Liu */ 659e080313cSDave Liu #define TIMING_CFG1_PRETOACT 0x70000000 660e080313cSDave Liu #define TIMING_CFG1_PRETOACT_SHIFT 28 661e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE 0x0F000000 662e080313cSDave Liu #define TIMING_CFG1_ACTTOPRE_SHIFT 24 663e080313cSDave Liu #define TIMING_CFG1_ACTTORW 0x00700000 664e080313cSDave Liu #define TIMING_CFG1_ACTTORW_SHIFT 20 665e080313cSDave Liu #define TIMING_CFG1_CASLAT 0x00070000 666e080313cSDave Liu #define TIMING_CFG1_CASLAT_SHIFT 16 667e080313cSDave Liu #define TIMING_CFG1_REFREC 0x0000F000 668e080313cSDave Liu #define TIMING_CFG1_REFREC_SHIFT 12 669e080313cSDave Liu #define TIMING_CFG1_WRREC 0x00000700 670e080313cSDave Liu #define TIMING_CFG1_WRREC_SHIFT 8 671e080313cSDave Liu #define TIMING_CFG1_ACTTOACT 0x00000070 672e080313cSDave Liu #define TIMING_CFG1_ACTTOACT_SHIFT 4 673e080313cSDave Liu #define TIMING_CFG1_WRTORD 0x00000007 674e080313cSDave Liu #define TIMING_CFG1_WRTORD_SHIFT 0 675e080313cSDave Liu #define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */ 676e080313cSDave Liu #define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */ 677e080313cSDave Liu 678e080313cSDave Liu /* TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 679e080313cSDave Liu */ 6808d172c0fSXie Xiaobo #define TIMING_CFG2_CPO 0x0F800000 6818d172c0fSXie Xiaobo #define TIMING_CFG2_CPO_SHIFT 23 682e080313cSDave Liu #define TIMING_CFG2_ACSM 0x00080000 683e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 684e080313cSDave Liu #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 685e080313cSDave Liu #define TIMING_CFG2_CPO_DEF 0x00000000 /* default (= CASLAT + 1) */ 686e080313cSDave Liu 687d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT 0x70000000 688d87c57b2SScott Wood #define TIMING_CFG2_ADD_LAT_SHIFT 28 689d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY 0x00380000 690d87c57b2SScott Wood #define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19 691d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE 0x0000E000 692d87c57b2SScott Wood #define TIMING_CFG2_RD_TO_PRE_SHIFT 13 693d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS 0x000001C0 694d87c57b2SScott Wood #define TIMING_CFG2_CKE_PLS_SHIFT 6 695d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT 0x0000003F 696d87c57b2SScott Wood #define TIMING_CFG2_FOUR_ACT_SHIFT 0 697d87c57b2SScott Wood 698e080313cSDave Liu /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration 699e080313cSDave Liu */ 700e080313cSDave Liu #define SDRAM_CFG_MEM_EN 0x80000000 701e080313cSDave Liu #define SDRAM_CFG_SREN 0x40000000 702e080313cSDave Liu #define SDRAM_CFG_ECC_EN 0x20000000 703e080313cSDave Liu #define SDRAM_CFG_RD_EN 0x10000000 704e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE 0x03000000 705d87c57b2SScott Wood #define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000 706e080313cSDave Liu #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 707e080313cSDave Liu #define SDRAM_CFG_DYN_PWR 0x00200000 708e080313cSDave Liu #define SDRAM_CFG_32_BE 0x00080000 709e080313cSDave Liu #define SDRAM_CFG_8_BE 0x00040000 710e080313cSDave Liu #define SDRAM_CFG_NCAP 0x00020000 711e080313cSDave Liu #define SDRAM_CFG_2T_EN 0x00008000 712d87c57b2SScott Wood #define SDRAM_CFG_BI 0x00000001 713e080313cSDave Liu 714e080313cSDave Liu /* DDR_SDRAM_MODE - DDR SDRAM Mode Register 715e080313cSDave Liu */ 716e080313cSDave Liu #define SDRAM_MODE_ESD 0xFFFF0000 717e080313cSDave Liu #define SDRAM_MODE_ESD_SHIFT 16 718e080313cSDave Liu #define SDRAM_MODE_SD 0x0000FFFF 719e080313cSDave Liu #define SDRAM_MODE_SD_SHIFT 0 720e080313cSDave Liu #define DDR_MODE_EXT_MODEREG 0x4000 /* select extended mode reg */ 721e080313cSDave Liu #define DDR_MODE_EXT_OPMODE 0x3FF8 /* operating mode, mask */ 722e080313cSDave Liu #define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */ 723e080313cSDave Liu #define DDR_MODE_QFC 0x0004 /* QFC / compatibility, mask */ 724e080313cSDave Liu #define DDR_MODE_QFC_COMP 0x0000 /* compatible to older SDRAMs */ 725e080313cSDave Liu #define DDR_MODE_WEAK 0x0002 /* weak drivers */ 726e080313cSDave Liu #define DDR_MODE_DLL_DIS 0x0001 /* disable DLL */ 727e080313cSDave Liu #define DDR_MODE_CASLAT 0x0070 /* CAS latency, mask */ 728e080313cSDave Liu #define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */ 729e080313cSDave Liu #define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */ 730e080313cSDave Liu #define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */ 731e080313cSDave Liu #define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */ 732e080313cSDave Liu #define DDR_MODE_BTYPE_SEQ 0x0000 /* sequential burst */ 733e080313cSDave Liu #define DDR_MODE_BTYPE_ILVD 0x0008 /* interleaved burst */ 734e080313cSDave Liu #define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */ 735e080313cSDave Liu #define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */ 736e080313cSDave Liu #define DDR_REFINT_166MHZ_7US 1302 /* exact value for 7.8125us */ 737e080313cSDave Liu #define DDR_BSTOPRE 256 /* use 256 cycles as a starting point */ 738e080313cSDave Liu #define DDR_MODE_MODEREG 0x0000 /* select mode register */ 739e080313cSDave Liu 740e080313cSDave Liu /* DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register 741e080313cSDave Liu */ 742e080313cSDave Liu #define SDRAM_INTERVAL_REFINT 0x3FFF0000 743e080313cSDave Liu #define SDRAM_INTERVAL_REFINT_SHIFT 16 744e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF 745e080313cSDave Liu #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 746e080313cSDave Liu 747e080313cSDave Liu /* DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register 748e080313cSDave Liu */ 749e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000 750e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000 751e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000 752e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000 753e080313cSDave Liu #define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000 754e080313cSDave Liu 755e080313cSDave Liu /* ECC_ERR_INJECT - Memory data path error injection mask ECC 756e080313cSDave Liu */ 757e080313cSDave Liu #define ECC_ERR_INJECT_EMB (0x80000000>>22) /* ECC Mirror Byte */ 758e080313cSDave Liu #define ECC_ERR_INJECT_EIEN (0x80000000>>23) /* Error Injection Enable */ 759e080313cSDave Liu #define ECC_ERR_INJECT_EEIM (0xff000000>>24) /* ECC Erroe Injection Enable */ 760e080313cSDave Liu #define ECC_ERR_INJECT_EEIM_SHIFT 0 761e080313cSDave Liu 762e080313cSDave Liu /* CAPTURE_ECC - Memory data path read capture ECC 763e080313cSDave Liu */ 764e080313cSDave Liu #define CAPTURE_ECC_ECE (0xff000000>>24) 765e080313cSDave Liu #define CAPTURE_ECC_ECE_SHIFT 0 766e080313cSDave Liu 767e080313cSDave Liu /* ERR_DETECT - Memory error detect 768e080313cSDave Liu */ 769e080313cSDave Liu #define ECC_ERROR_DETECT_MME (0x80000000>>0) /* Multiple Memory Errors */ 770e080313cSDave Liu #define ECC_ERROR_DETECT_MBE (0x80000000>>28) /* Multiple-Bit Error */ 771e080313cSDave Liu #define ECC_ERROR_DETECT_SBE (0x80000000>>29) /* Single-Bit ECC Error Pickup */ 772e080313cSDave Liu #define ECC_ERROR_DETECT_MSE (0x80000000>>31) /* Memory Select Error */ 773e080313cSDave Liu 774e080313cSDave Liu /* ERR_DISABLE - Memory error disable 775e080313cSDave Liu */ 776e080313cSDave Liu #define ECC_ERROR_DISABLE_MBED (0x80000000>>28) /* Multiple-Bit ECC Error Disable */ 777e080313cSDave Liu #define ECC_ERROR_DISABLE_SBED (0x80000000>>29) /* Sinle-Bit ECC Error disable */ 778e080313cSDave Liu #define ECC_ERROR_DISABLE_MSED (0x80000000>>31) /* Memory Select Error Disable */ 779e080313cSDave Liu #define ECC_ERROR_ENABLE ~(ECC_ERROR_DISABLE_MSED | ECC_ERROR_DISABLE_SBED |\ 780e080313cSDave Liu ECC_ERROR_DISABLE_MBED) 781e080313cSDave Liu /* ERR_INT_EN - Memory error interrupt enable 782e080313cSDave Liu */ 783e080313cSDave Liu #define ECC_ERR_INT_EN_MBEE (0x80000000>>28) /* Multiple-Bit ECC Error Interrupt Enable */ 784e080313cSDave Liu #define ECC_ERR_INT_EN_SBEE (0x80000000>>29) /* Single-Bit ECC Error Interrupt Enable */ 785e080313cSDave Liu #define ECC_ERR_INT_EN_MSEE (0x80000000>>31) /* Memory Select Error Interrupt Enable */ 786e080313cSDave Liu #define ECC_ERR_INT_DISABLE ~(ECC_ERR_INT_EN_MBEE | ECC_ERR_INT_EN_SBEE |\ 787e080313cSDave Liu ECC_ERR_INT_EN_MSEE) 788e080313cSDave Liu /* CAPTURE_ATTRIBUTES - Memory error attributes capture 789e080313cSDave Liu */ 790e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM (0xe0000000>>1) /* Data Beat Num */ 791e080313cSDave Liu #define ECC_CAPT_ATTR_BNUM_SHIFT 28 792e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ (0xc0000000>>6) /* Transaction Size */ 793e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0 794e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_ONE_DW 1 795e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_TWO_DW 2 796e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_THREE_DW 3 797e080313cSDave Liu #define ECC_CAPT_ATTR_TSIZ_SHIFT 24 798e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC (0xf8000000>>11) /* Transaction Source */ 799e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0 800e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2 801e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC1 0x4 802e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_TSEC2 0x5 803e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07) 804e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8 805e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_I2C 0x9 806e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_JTAG 0xA 807e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI1 0xD 808e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_PCI2 0xE 809e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_DMA 0xF 810e080313cSDave Liu #define ECC_CAPT_ATTR_TSRC_SHIFT 16 811e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP (0xe0000000>>18) /* Transaction Type */ 812e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_WRITE 0x1 813e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_READ 0x2 814e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_R_M_W 0x3 815e080313cSDave Liu #define ECC_CAPT_ATTR_TTYP_SHIFT 12 816e080313cSDave Liu #define ECC_CAPT_ATTR_VLD (0x80000000>>31) /* Valid */ 817e080313cSDave Liu 818e080313cSDave Liu /* ERR_SBE - Single bit ECC memory error management 819e080313cSDave Liu */ 820e080313cSDave Liu #define ECC_ERROR_MAN_SBET (0xff000000>>8) /* Single-Bit Error Threshold 0..255 */ 821e080313cSDave Liu #define ECC_ERROR_MAN_SBET_SHIFT 16 822e080313cSDave Liu #define ECC_ERROR_MAN_SBEC (0xff000000>>24) /* Single Bit Error Counter 0..255 */ 823e080313cSDave Liu #define ECC_ERROR_MAN_SBEC_SHIFT 0 824e080313cSDave Liu 825e080313cSDave Liu /* BR - Base Registers 826e080313cSDave Liu */ 827e080313cSDave Liu #define BR0 0x5000 /* Register offset to immr */ 828f046ccd1SEran Liberty #define BR1 0x5008 829f046ccd1SEran Liberty #define BR2 0x5010 830f046ccd1SEran Liberty #define BR3 0x5018 831f046ccd1SEran Liberty #define BR4 0x5020 832f046ccd1SEran Liberty #define BR5 0x5028 833f046ccd1SEran Liberty #define BR6 0x5030 834f046ccd1SEran Liberty #define BR7 0x5038 835f046ccd1SEran Liberty 836f046ccd1SEran Liberty #define BR_BA 0xFFFF8000 837f046ccd1SEran Liberty #define BR_BA_SHIFT 15 838f046ccd1SEran Liberty #define BR_PS 0x00001800 839f046ccd1SEran Liberty #define BR_PS_SHIFT 11 840e6f2e902SMarian Balakowicz #define BR_PS_8 0x00000800 /* Port Size 8 bit */ 841e6f2e902SMarian Balakowicz #define BR_PS_16 0x00001000 /* Port Size 16 bit */ 842e6f2e902SMarian Balakowicz #define BR_PS_32 0x00001800 /* Port Size 32 bit */ 843f046ccd1SEran Liberty #define BR_DECC 0x00000600 844f046ccd1SEran Liberty #define BR_DECC_SHIFT 9 845d87c57b2SScott Wood #define BR_DECC_OFF 0x00000000 846d87c57b2SScott Wood #define BR_DECC_CHK 0x00000200 847d87c57b2SScott Wood #define BR_DECC_CHK_GEN 0x00000400 848f046ccd1SEran Liberty #define BR_WP 0x00000100 849f046ccd1SEran Liberty #define BR_WP_SHIFT 8 850f046ccd1SEran Liberty #define BR_MSEL 0x000000E0 851f046ccd1SEran Liberty #define BR_MSEL_SHIFT 5 852e6f2e902SMarian Balakowicz #define BR_MS_GPCM 0x00000000 /* GPCM */ 853d87c57b2SScott Wood #define BR_MS_FCM 0x00000020 /* FCM */ 854e6f2e902SMarian Balakowicz #define BR_MS_SDRAM 0x00000060 /* SDRAM */ 855e6f2e902SMarian Balakowicz #define BR_MS_UPMA 0x00000080 /* UPMA */ 856e6f2e902SMarian Balakowicz #define BR_MS_UPMB 0x000000A0 /* UPMB */ 857e6f2e902SMarian Balakowicz #define BR_MS_UPMC 0x000000C0 /* UPMC */ 85824c3aca3SDave Liu #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X) 8595f820439SDave Liu #define BR_ATOM 0x0000000C 8605f820439SDave Liu #define BR_ATOM_SHIFT 2 8615f820439SDave Liu #endif 862f046ccd1SEran Liberty #define BR_V 0x00000001 863f046ccd1SEran Liberty #define BR_V_SHIFT 0 864e080313cSDave Liu 8653e78a31cSKumar Gala #if defined(CONFIG_MPC834X) 866f046ccd1SEran Liberty #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) 8675f820439SDave Liu #elif defined(CONFIG_MPC8360) 8685f820439SDave Liu #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) 8695f820439SDave Liu #endif 870f046ccd1SEran Liberty 871e080313cSDave Liu /* OR - Option Registers 872e080313cSDave Liu */ 873e080313cSDave Liu #define OR0 0x5004 /* Register offset to immr */ 874f046ccd1SEran Liberty #define OR1 0x500C 875f046ccd1SEran Liberty #define OR2 0x5014 876f046ccd1SEran Liberty #define OR3 0x501C 877f046ccd1SEran Liberty #define OR4 0x5024 878f046ccd1SEran Liberty #define OR5 0x502C 879f046ccd1SEran Liberty #define OR6 0x5034 880f046ccd1SEran Liberty #define OR7 0x503C 881f046ccd1SEran Liberty 882f046ccd1SEran Liberty #define OR_GPCM_AM 0xFFFF8000 883f046ccd1SEran Liberty #define OR_GPCM_AM_SHIFT 15 884f046ccd1SEran Liberty #define OR_GPCM_BCTLD 0x00001000 885f046ccd1SEran Liberty #define OR_GPCM_BCTLD_SHIFT 12 886f046ccd1SEran Liberty #define OR_GPCM_CSNT 0x00000800 887f046ccd1SEran Liberty #define OR_GPCM_CSNT_SHIFT 11 888f046ccd1SEran Liberty #define OR_GPCM_ACS 0x00000600 889f046ccd1SEran Liberty #define OR_GPCM_ACS_SHIFT 9 890e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b10 0x00000400 891e6f2e902SMarian Balakowicz #define OR_GPCM_ACS_0b11 0x00000600 892f046ccd1SEran Liberty #define OR_GPCM_XACS 0x00000100 893f046ccd1SEran Liberty #define OR_GPCM_XACS_SHIFT 8 894f046ccd1SEran Liberty #define OR_GPCM_SCY 0x000000F0 895f046ccd1SEran Liberty #define OR_GPCM_SCY_SHIFT 4 896e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_1 0x00000010 897e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_2 0x00000020 898e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_3 0x00000030 899e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_4 0x00000040 900e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_5 0x00000050 901e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_6 0x00000060 902e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_7 0x00000070 903e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_8 0x00000080 904e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_9 0x00000090 905e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_10 0x000000a0 906e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_11 0x000000b0 907e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_12 0x000000c0 908e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_13 0x000000d0 909e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_14 0x000000e0 910e6f2e902SMarian Balakowicz #define OR_GPCM_SCY_15 0x000000f0 911f046ccd1SEran Liberty #define OR_GPCM_SETA 0x00000008 912f046ccd1SEran Liberty #define OR_GPCM_SETA_SHIFT 3 913f046ccd1SEran Liberty #define OR_GPCM_TRLX 0x00000004 914f046ccd1SEran Liberty #define OR_GPCM_TRLX_SHIFT 2 915f046ccd1SEran Liberty #define OR_GPCM_EHTR 0x00000002 916f046ccd1SEran Liberty #define OR_GPCM_EHTR_SHIFT 1 917f046ccd1SEran Liberty #define OR_GPCM_EAD 0x00000001 918f046ccd1SEran Liberty #define OR_GPCM_EAD_SHIFT 0 919f046ccd1SEran Liberty 920d87c57b2SScott Wood #define OR_FCM_AM 0xFFFF8000 921d87c57b2SScott Wood #define OR_FCM_AM_SHIFT 15 922d87c57b2SScott Wood #define OR_FCM_BCTLD 0x00001000 923d87c57b2SScott Wood #define OR_FCM_BCTLD_SHIFT 12 924d87c57b2SScott Wood #define OR_FCM_PGS 0x00000400 925d87c57b2SScott Wood #define OR_FCM_PGS_SHIFT 10 926d87c57b2SScott Wood #define OR_FCM_CSCT 0x00000200 927d87c57b2SScott Wood #define OR_FCM_CSCT_SHIFT 9 928d87c57b2SScott Wood #define OR_FCM_CST 0x00000100 929d87c57b2SScott Wood #define OR_FCM_CST_SHIFT 8 930d87c57b2SScott Wood #define OR_FCM_CHT 0x00000080 931d87c57b2SScott Wood #define OR_FCM_CHT_SHIFT 7 932d87c57b2SScott Wood #define OR_FCM_SCY 0x00000070 933d87c57b2SScott Wood #define OR_FCM_SCY_SHIFT 4 934d87c57b2SScott Wood #define OR_FCM_SCY_1 0x00000010 935d87c57b2SScott Wood #define OR_FCM_SCY_2 0x00000020 936d87c57b2SScott Wood #define OR_FCM_SCY_3 0x00000030 937d87c57b2SScott Wood #define OR_FCM_SCY_4 0x00000040 938d87c57b2SScott Wood #define OR_FCM_SCY_5 0x00000050 939d87c57b2SScott Wood #define OR_FCM_SCY_6 0x00000060 940d87c57b2SScott Wood #define OR_FCM_SCY_7 0x00000070 941d87c57b2SScott Wood #define OR_FCM_RST 0x00000008 942d87c57b2SScott Wood #define OR_FCM_RST_SHIFT 3 943d87c57b2SScott Wood #define OR_FCM_TRLX 0x00000004 944d87c57b2SScott Wood #define OR_FCM_TRLX_SHIFT 2 945d87c57b2SScott Wood #define OR_FCM_EHTR 0x00000002 946d87c57b2SScott Wood #define OR_FCM_EHTR_SHIFT 1 947d87c57b2SScott Wood 948f046ccd1SEran Liberty #define OR_UPM_AM 0xFFFF8000 949f046ccd1SEran Liberty #define OR_UPM_AM_SHIFT 15 950f046ccd1SEran Liberty #define OR_UPM_XAM 0x00006000 951f046ccd1SEran Liberty #define OR_UPM_XAM_SHIFT 13 952f046ccd1SEran Liberty #define OR_UPM_BCTLD 0x00001000 953f046ccd1SEran Liberty #define OR_UPM_BCTLD_SHIFT 12 954f046ccd1SEran Liberty #define OR_UPM_BI 0x00000100 955f046ccd1SEran Liberty #define OR_UPM_BI_SHIFT 8 956f046ccd1SEran Liberty #define OR_UPM_TRLX 0x00000004 957f046ccd1SEran Liberty #define OR_UPM_TRLX_SHIFT 2 958f046ccd1SEran Liberty #define OR_UPM_EHTR 0x00000002 959f046ccd1SEran Liberty #define OR_UPM_EHTR_SHIFT 1 960f046ccd1SEran Liberty #define OR_UPM_EAD 0x00000001 961f046ccd1SEran Liberty #define OR_UPM_EAD_SHIFT 0 962f046ccd1SEran Liberty 963f046ccd1SEran Liberty #define OR_SDRAM_AM 0xFFFF8000 964f046ccd1SEran Liberty #define OR_SDRAM_AM_SHIFT 15 965f046ccd1SEran Liberty #define OR_SDRAM_XAM 0x00006000 966f046ccd1SEran Liberty #define OR_SDRAM_XAM_SHIFT 13 967f046ccd1SEran Liberty #define OR_SDRAM_COLS 0x00001C00 968f046ccd1SEran Liberty #define OR_SDRAM_COLS_SHIFT 10 969f046ccd1SEran Liberty #define OR_SDRAM_ROWS 0x000001C0 970f046ccd1SEran Liberty #define OR_SDRAM_ROWS_SHIFT 6 971f046ccd1SEran Liberty #define OR_SDRAM_PMSEL 0x00000020 972f046ccd1SEran Liberty #define OR_SDRAM_PMSEL_SHIFT 5 973f046ccd1SEran Liberty #define OR_SDRAM_EAD 0x00000001 974f046ccd1SEran Liberty #define OR_SDRAM_EAD_SHIFT 0 975f046ccd1SEran Liberty 9767a78f148STimur Tabi #define OR_AM_32KB 0xFFFF8000 9777a78f148STimur Tabi #define OR_AM_64KB 0xFFFF0000 9787a78f148STimur Tabi #define OR_AM_128KB 0xFFFE0000 9797a78f148STimur Tabi #define OR_AM_256KB 0xFFFC0000 9807a78f148STimur Tabi #define OR_AM_512KB 0xFFF80000 9817a78f148STimur Tabi #define OR_AM_1MB 0xFFF00000 9827a78f148STimur Tabi #define OR_AM_2MB 0xFFE00000 9837a78f148STimur Tabi #define OR_AM_4MB 0xFFC00000 9847a78f148STimur Tabi #define OR_AM_8MB 0xFF800000 9857a78f148STimur Tabi #define OR_AM_16MB 0xFF000000 9867a78f148STimur Tabi #define OR_AM_32MB 0xFE000000 9877a78f148STimur Tabi #define OR_AM_64MB 0xFC000000 9887a78f148STimur Tabi #define OR_AM_128MB 0xF8000000 9897a78f148STimur Tabi #define OR_AM_256MB 0xF0000000 9907a78f148STimur Tabi #define OR_AM_512MB 0xE0000000 9917a78f148STimur Tabi #define OR_AM_1GB 0xC0000000 9927a78f148STimur Tabi #define OR_AM_2GB 0x80000000 9937a78f148STimur Tabi #define OR_AM_4GB 0x00000000 9947a78f148STimur Tabi 9957a78f148STimur Tabi #define LBLAWAR_EN 0x80000000 9967a78f148STimur Tabi #define LBLAWAR_4KB 0x0000000B 9977a78f148STimur Tabi #define LBLAWAR_8KB 0x0000000C 9987a78f148STimur Tabi #define LBLAWAR_16KB 0x0000000D 9997a78f148STimur Tabi #define LBLAWAR_32KB 0x0000000E 10007a78f148STimur Tabi #define LBLAWAR_64KB 0x0000000F 10017a78f148STimur Tabi #define LBLAWAR_128KB 0x00000010 10027a78f148STimur Tabi #define LBLAWAR_256KB 0x00000011 10037a78f148STimur Tabi #define LBLAWAR_512KB 0x00000012 10047a78f148STimur Tabi #define LBLAWAR_1MB 0x00000013 10057a78f148STimur Tabi #define LBLAWAR_2MB 0x00000014 10067a78f148STimur Tabi #define LBLAWAR_4MB 0x00000015 10077a78f148STimur Tabi #define LBLAWAR_8MB 0x00000016 10087a78f148STimur Tabi #define LBLAWAR_16MB 0x00000017 10097a78f148STimur Tabi #define LBLAWAR_32MB 0x00000018 10107a78f148STimur Tabi #define LBLAWAR_64MB 0x00000019 10117a78f148STimur Tabi #define LBLAWAR_128MB 0x0000001A 10127a78f148STimur Tabi #define LBLAWAR_256MB 0x0000001B 10137a78f148STimur Tabi #define LBLAWAR_512MB 0x0000001C 10147a78f148STimur Tabi #define LBLAWAR_1GB 0x0000001D 10157a78f148STimur Tabi #define LBLAWAR_2GB 0x0000001E 10167a78f148STimur Tabi 1017e080313cSDave Liu /* LBCR - Local Bus Configuration Register 1018f046ccd1SEran Liberty */ 1019e080313cSDave Liu #define LBCR_LDIS 0x80000000 1020e080313cSDave Liu #define LBCR_LDIS_SHIFT 31 1021e080313cSDave Liu #define LBCR_BCTLC 0x00C00000 1022e080313cSDave Liu #define LBCR_BCTLC_SHIFT 22 1023e080313cSDave Liu #define LBCR_LPBSE 0x00020000 1024e080313cSDave Liu #define LBCR_LPBSE_SHIFT 17 1025e080313cSDave Liu #define LBCR_EPAR 0x00010000 1026e080313cSDave Liu #define LBCR_EPAR_SHIFT 16 1027e080313cSDave Liu #define LBCR_BMT 0x0000FF00 1028e080313cSDave Liu #define LBCR_BMT_SHIFT 8 1029f046ccd1SEran Liberty 1030e080313cSDave Liu /* LCRR - Clock Ratio Register 1031f046ccd1SEran Liberty */ 1032f046ccd1SEran Liberty #define LCRR_DBYP 0x80000000 1033f046ccd1SEran Liberty #define LCRR_DBYP_SHIFT 31 1034f046ccd1SEran Liberty #define LCRR_BUFCMDC 0x30000000 1035e080313cSDave Liu #define LCRR_BUFCMDC_SHIFT 28 1036f046ccd1SEran Liberty #define LCRR_BUFCMDC_1 0x10000000 1037f046ccd1SEran Liberty #define LCRR_BUFCMDC_2 0x20000000 1038f046ccd1SEran Liberty #define LCRR_BUFCMDC_3 0x30000000 1039f046ccd1SEran Liberty #define LCRR_BUFCMDC_4 0x00000000 1040f046ccd1SEran Liberty #define LCRR_ECL 0x03000000 1041e080313cSDave Liu #define LCRR_ECL_SHIFT 24 1042f046ccd1SEran Liberty #define LCRR_ECL_4 0x00000000 1043f046ccd1SEran Liberty #define LCRR_ECL_5 0x01000000 1044f046ccd1SEran Liberty #define LCRR_ECL_6 0x02000000 1045f046ccd1SEran Liberty #define LCRR_ECL_7 0x03000000 1046f046ccd1SEran Liberty #define LCRR_EADC 0x00030000 1047e080313cSDave Liu #define LCRR_EADC_SHIFT 16 1048f046ccd1SEran Liberty #define LCRR_EADC_1 0x00010000 1049f046ccd1SEran Liberty #define LCRR_EADC_2 0x00020000 1050f046ccd1SEran Liberty #define LCRR_EADC_3 0x00030000 1051f046ccd1SEran Liberty #define LCRR_EADC_4 0x00000000 1052f046ccd1SEran Liberty #define LCRR_CLKDIV 0x0000000F 1053e080313cSDave Liu #define LCRR_CLKDIV_SHIFT 0 1054f046ccd1SEran Liberty #define LCRR_CLKDIV_2 0x00000002 1055f046ccd1SEran Liberty #define LCRR_CLKDIV_4 0x00000004 1056f046ccd1SEran Liberty #define LCRR_CLKDIV_8 0x00000008 1057f046ccd1SEran Liberty 1058e080313cSDave Liu /* DMAMR - DMA Mode Register 1059f6eda7f8SDave Liu */ 1060e080313cSDave Liu #define DMA_CHANNEL_START 0x00000001 /* Bit - DMAMRn CS */ 1061e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_MODE_DIRECT 0x00000004 /* Bit - DMAMRn CTM */ 1062e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN 0x00001000 /* Bit - DMAMRn SAHE */ 1063e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_1B 0x00000000 /* 2Bit- DMAMRn SAHTS 1byte */ 1064e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_2B 0x00004000 /* 2Bit- DMAMRn SAHTS 2bytes */ 1065e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_4B 0x00008000 /* 2Bit- DMAMRn SAHTS 4bytes */ 1066e080313cSDave Liu #define DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B 0x0000c000 /* 2Bit- DMAMRn SAHTS 8bytes */ 1067e080313cSDave Liu #define DMA_CHANNEL_SNOOP 0x00010000 /* Bit - DMAMRn DMSEN */ 1068f6eda7f8SDave Liu 1069e080313cSDave Liu /* DMASR - DMA Status Register 1070e080313cSDave Liu */ 1071e080313cSDave Liu #define DMA_CHANNEL_BUSY 0x00000004 /* Bit - DMASRn CB */ 1072e080313cSDave Liu #define DMA_CHANNEL_TRANSFER_ERROR 0x00000080 /* Bit - DMASRn TE */ 10735f820439SDave Liu 1074e080313cSDave Liu /* CONFIG_ADDRESS - PCI Config Address Register 1075e080313cSDave Liu */ 1076e080313cSDave Liu #define PCI_CONFIG_ADDRESS_EN 0x80000000 1077e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_SHIFT 16 1078e080313cSDave Liu #define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000 1079e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_SHIFT 11 1080e080313cSDave Liu #define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800 1081e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_SHIFT 8 1082e080313cSDave Liu #define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700 1083e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_SHIFT 0 1084e080313cSDave Liu #define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc 1085e080313cSDave Liu 1086e080313cSDave Liu /* POTAR - PCI Outbound Translation Address Register 1087e080313cSDave Liu */ 1088e080313cSDave Liu #define POTAR_TA_MASK 0x000fffff 1089e080313cSDave Liu 1090e080313cSDave Liu /* POBAR - PCI Outbound Base Address Register 1091e080313cSDave Liu */ 1092e080313cSDave Liu #define POBAR_BA_MASK 0x000fffff 1093e080313cSDave Liu 1094e080313cSDave Liu /* POCMR - PCI Outbound Comparision Mask Register 1095e080313cSDave Liu */ 1096e080313cSDave Liu #define POCMR_EN 0x80000000 1097e080313cSDave Liu #define POCMR_IO 0x40000000 /* 0-memory space 1-I/O space */ 1098e080313cSDave Liu #define POCMR_SE 0x20000000 /* streaming enable */ 1099e080313cSDave Liu #define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */ 1100e080313cSDave Liu #define POCMR_CM_MASK 0x000fffff 1101e080313cSDave Liu #define POCMR_CM_4G 0x00000000 1102e080313cSDave Liu #define POCMR_CM_2G 0x00080000 1103e080313cSDave Liu #define POCMR_CM_1G 0x000C0000 1104e080313cSDave Liu #define POCMR_CM_512M 0x000E0000 1105e080313cSDave Liu #define POCMR_CM_256M 0x000F0000 1106e080313cSDave Liu #define POCMR_CM_128M 0x000F8000 1107e080313cSDave Liu #define POCMR_CM_64M 0x000FC000 1108e080313cSDave Liu #define POCMR_CM_32M 0x000FE000 1109e080313cSDave Liu #define POCMR_CM_16M 0x000FF000 1110e080313cSDave Liu #define POCMR_CM_8M 0x000FF800 1111e080313cSDave Liu #define POCMR_CM_4M 0x000FFC00 1112e080313cSDave Liu #define POCMR_CM_2M 0x000FFE00 1113e080313cSDave Liu #define POCMR_CM_1M 0x000FFF00 1114e080313cSDave Liu #define POCMR_CM_512K 0x000FFF80 1115e080313cSDave Liu #define POCMR_CM_256K 0x000FFFC0 1116e080313cSDave Liu #define POCMR_CM_128K 0x000FFFE0 1117e080313cSDave Liu #define POCMR_CM_64K 0x000FFFF0 1118e080313cSDave Liu #define POCMR_CM_32K 0x000FFFF8 1119e080313cSDave Liu #define POCMR_CM_16K 0x000FFFFC 1120e080313cSDave Liu #define POCMR_CM_8K 0x000FFFFE 1121e080313cSDave Liu #define POCMR_CM_4K 0x000FFFFF 1122e080313cSDave Liu 1123e080313cSDave Liu /* PITAR - PCI Inbound Translation Address Register 1124e080313cSDave Liu */ 1125e080313cSDave Liu #define PITAR_TA_MASK 0x000fffff 1126e080313cSDave Liu 1127e080313cSDave Liu /* PIBAR - PCI Inbound Base/Extended Address Register 1128e080313cSDave Liu */ 1129e080313cSDave Liu #define PIBAR_MASK 0xffffffff 1130e080313cSDave Liu #define PIEBAR_EBA_MASK 0x000fffff 1131e080313cSDave Liu 1132e080313cSDave Liu /* PIWAR - PCI Inbound Windows Attributes Register 1133e080313cSDave Liu */ 1134e080313cSDave Liu #define PIWAR_EN 0x80000000 1135e080313cSDave Liu #define PIWAR_PF 0x20000000 1136e080313cSDave Liu #define PIWAR_RTT_MASK 0x000f0000 1137e080313cSDave Liu #define PIWAR_RTT_NO_SNOOP 0x00040000 1138e080313cSDave Liu #define PIWAR_RTT_SNOOP 0x00050000 1139e080313cSDave Liu #define PIWAR_WTT_MASK 0x0000f000 1140e080313cSDave Liu #define PIWAR_WTT_NO_SNOOP 0x00004000 1141e080313cSDave Liu #define PIWAR_WTT_SNOOP 0x00005000 1142e080313cSDave Liu #define PIWAR_IWS_MASK 0x0000003F 1143e080313cSDave Liu #define PIWAR_IWS_4K 0x0000000B 1144e080313cSDave Liu #define PIWAR_IWS_8K 0x0000000C 1145e080313cSDave Liu #define PIWAR_IWS_16K 0x0000000D 1146e080313cSDave Liu #define PIWAR_IWS_32K 0x0000000E 1147e080313cSDave Liu #define PIWAR_IWS_64K 0x0000000F 1148e080313cSDave Liu #define PIWAR_IWS_128K 0x00000010 1149e080313cSDave Liu #define PIWAR_IWS_256K 0x00000011 1150e080313cSDave Liu #define PIWAR_IWS_512K 0x00000012 1151e080313cSDave Liu #define PIWAR_IWS_1M 0x00000013 1152e080313cSDave Liu #define PIWAR_IWS_2M 0x00000014 1153e080313cSDave Liu #define PIWAR_IWS_4M 0x00000015 1154e080313cSDave Liu #define PIWAR_IWS_8M 0x00000016 1155e080313cSDave Liu #define PIWAR_IWS_16M 0x00000017 1156e080313cSDave Liu #define PIWAR_IWS_32M 0x00000018 1157e080313cSDave Liu #define PIWAR_IWS_64M 0x00000019 1158e080313cSDave Liu #define PIWAR_IWS_128M 0x0000001A 1159e080313cSDave Liu #define PIWAR_IWS_256M 0x0000001B 1160e080313cSDave Liu #define PIWAR_IWS_512M 0x0000001C 1161e080313cSDave Liu #define PIWAR_IWS_1G 0x0000001D 1162e080313cSDave Liu #define PIWAR_IWS_2G 0x0000001E 1163f6eda7f8SDave Liu 1164d87c57b2SScott Wood /* PMCCR1 - PCI Configuration Register 1 1165d87c57b2SScott Wood */ 1166d87c57b2SScott Wood #define PMCCR1_POWER_OFF 0x00000020 1167d87c57b2SScott Wood 1168d87c57b2SScott Wood /* FMR - Flash Mode Register 1169d87c57b2SScott Wood */ 1170d87c57b2SScott Wood #define FMR_CWTO 0x0000F000 1171d87c57b2SScott Wood #define FMR_CWTO_SHIFT 12 1172d87c57b2SScott Wood #define FMR_BOOT 0x00000800 1173d87c57b2SScott Wood #define FMR_ECCM 0x00000100 1174d87c57b2SScott Wood #define FMR_AL 0x00000030 1175d87c57b2SScott Wood #define FMR_AL_SHIFT 4 1176d87c57b2SScott Wood #define FMR_OP 0x00000003 1177d87c57b2SScott Wood #define FMR_OP_SHIFT 0 1178d87c57b2SScott Wood 1179d87c57b2SScott Wood /* FIR - Flash Instruction Register 1180d87c57b2SScott Wood */ 1181d87c57b2SScott Wood #define FIR_OP0 0xF0000000 1182d87c57b2SScott Wood #define FIR_OP0_SHIFT 28 1183d87c57b2SScott Wood #define FIR_OP1 0x0F000000 1184d87c57b2SScott Wood #define FIR_OP1_SHIFT 24 1185d87c57b2SScott Wood #define FIR_OP2 0x00F00000 1186d87c57b2SScott Wood #define FIR_OP2_SHIFT 20 1187d87c57b2SScott Wood #define FIR_OP3 0x000F0000 1188d87c57b2SScott Wood #define FIR_OP3_SHIFT 16 1189d87c57b2SScott Wood #define FIR_OP4 0x0000F000 1190d87c57b2SScott Wood #define FIR_OP4_SHIFT 12 1191d87c57b2SScott Wood #define FIR_OP5 0x00000F00 1192d87c57b2SScott Wood #define FIR_OP5_SHIFT 8 1193d87c57b2SScott Wood #define FIR_OP6 0x000000F0 1194d87c57b2SScott Wood #define FIR_OP6_SHIFT 4 1195d87c57b2SScott Wood #define FIR_OP7 0x0000000F 1196d87c57b2SScott Wood #define FIR_OP7_SHIFT 0 1197d87c57b2SScott Wood #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 1198d87c57b2SScott Wood #define FIR_OP_CA 0x1 /* Issue current column address */ 1199d87c57b2SScott Wood #define FIR_OP_PA 0x2 /* Issue current block+page address */ 1200d87c57b2SScott Wood #define FIR_OP_UA 0x3 /* Issue user defined address */ 1201d87c57b2SScott Wood #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ 1202d87c57b2SScott Wood #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ 1203d87c57b2SScott Wood #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ 1204d87c57b2SScott Wood #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ 1205d87c57b2SScott Wood #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 1206d87c57b2SScott Wood #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 1207d87c57b2SScott Wood #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 1208d87c57b2SScott Wood #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 1209d87c57b2SScott Wood #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 1210d87c57b2SScott Wood #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 1211d87c57b2SScott Wood #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 1212d87c57b2SScott Wood #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 1213d87c57b2SScott Wood 1214d87c57b2SScott Wood /* FCR - Flash Command Register 1215d87c57b2SScott Wood */ 1216d87c57b2SScott Wood #define FCR_CMD0 0xFF000000 1217d87c57b2SScott Wood #define FCR_CMD0_SHIFT 24 1218d87c57b2SScott Wood #define FCR_CMD1 0x00FF0000 1219d87c57b2SScott Wood #define FCR_CMD1_SHIFT 16 1220d87c57b2SScott Wood #define FCR_CMD2 0x0000FF00 1221d87c57b2SScott Wood #define FCR_CMD2_SHIFT 8 1222d87c57b2SScott Wood #define FCR_CMD3 0x000000FF 1223d87c57b2SScott Wood #define FCR_CMD3_SHIFT 0 1224d87c57b2SScott Wood 1225d87c57b2SScott Wood /* FBAR - Flash Block Address Register 1226d87c57b2SScott Wood */ 1227d87c57b2SScott Wood #define FBAR_BLK 0x00FFFFFF 1228d87c57b2SScott Wood 1229d87c57b2SScott Wood /* FPAR - Flash Page Address Register 1230d87c57b2SScott Wood */ 1231d87c57b2SScott Wood #define FPAR_SP_PI 0x00007C00 1232d87c57b2SScott Wood #define FPAR_SP_PI_SHIFT 10 1233d87c57b2SScott Wood #define FPAR_SP_MS 0x00000200 1234d87c57b2SScott Wood #define FPAR_SP_CI 0x000001FF 1235d87c57b2SScott Wood #define FPAR_SP_CI_SHIFT 0 1236d87c57b2SScott Wood #define FPAR_LP_PI 0x0003F000 1237d87c57b2SScott Wood #define FPAR_LP_PI_SHIFT 12 1238d87c57b2SScott Wood #define FPAR_LP_MS 0x00000800 1239d87c57b2SScott Wood #define FPAR_LP_CI 0x000007FF 1240d87c57b2SScott Wood #define FPAR_LP_CI_SHIFT 0 1241d87c57b2SScott Wood 1242d87c57b2SScott Wood /* LTESR - Transfer Error Status Register 1243d87c57b2SScott Wood */ 1244d87c57b2SScott Wood #define LTESR_BM 0x80000000 1245d87c57b2SScott Wood #define LTESR_FCT 0x40000000 1246d87c57b2SScott Wood #define LTESR_PAR 0x20000000 1247d87c57b2SScott Wood #define LTESR_WP 0x04000000 1248d87c57b2SScott Wood #define LTESR_ATMW 0x00800000 1249d87c57b2SScott Wood #define LTESR_ATMR 0x00400000 1250d87c57b2SScott Wood #define LTESR_CS 0x00080000 1251d87c57b2SScott Wood #define LTESR_CC 0x00000001 1252d87c57b2SScott Wood 1253d87c57b2SScott Wood /* DDR Control Driver Register 1254d87c57b2SScott Wood */ 1255d87c57b2SScott Wood #define DDRCDR_EN 0x40000000 1256d87c57b2SScott Wood #define DDRCDR_PZ 0x3C000000 1257d87c57b2SScott Wood #define DDRCDR_PZ_MAXZ 0x00000000 1258d87c57b2SScott Wood #define DDRCDR_PZ_HIZ 0x20000000 1259d87c57b2SScott Wood #define DDRCDR_PZ_NOMZ 0x30000000 1260d87c57b2SScott Wood #define DDRCDR_PZ_LOZ 0x38000000 1261d87c57b2SScott Wood #define DDRCDR_PZ_MINZ 0x3C000000 1262d87c57b2SScott Wood #define DDRCDR_NZ 0x3C000000 1263d87c57b2SScott Wood #define DDRCDR_NZ_MAXZ 0x00000000 1264d87c57b2SScott Wood #define DDRCDR_NZ_HIZ 0x02000000 1265d87c57b2SScott Wood #define DDRCDR_NZ_NOMZ 0x03000000 1266d87c57b2SScott Wood #define DDRCDR_NZ_LOZ 0x03800000 1267d87c57b2SScott Wood #define DDRCDR_NZ_MINZ 0x03C00000 1268d87c57b2SScott Wood #define DDRCDR_ODT 0x00080000 1269d87c57b2SScott Wood #define DDRCDR_DDR_CFG 0x00040000 1270d87c57b2SScott Wood #define DDRCDR_M_ODR 0x00000002 1271d87c57b2SScott Wood #define DDRCDR_Q_DRN 0x00000001 1272d87c57b2SScott Wood 127349ea3b6eSScott Wood #ifndef __ASSEMBLY__ 127449ea3b6eSScott Wood struct pci_region; 127549ea3b6eSScott Wood void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); 127649ea3b6eSScott Wood #endif 127749ea3b6eSScott Wood 1278f046ccd1SEran Liberty #endif /* __MPC83XX_H__ */ 1279